IRFZ44S, IRFZ44L, SiHFZ44S, SiHFZ44L
www.vishay.com
Vishay Siliconix
Power MOSFET
FEATURES
D
•
•
•
•
•
•
D2PAK (TO-263)
I2PAK (TO-262)
G
G
G
D
S
D
S
S
N-Channel MOSFET
Available
Available
Note
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details
DESCRIPTION
PRODUCT SUMMARY
VDS (V)
RDS(on) ()
Advanced process technology
Surface-mount (IRFZ44S, SiHFZ44S)
Low-profile through-hole (IRFZ44L, SiHFZ44L)
175 °C operating temperature
Fast switching
Material categorization:
for definitions of compliance please see
www.vishay.com/doc?99912
60
VGS = 10 V
0.028
Qg (Max.) (nC)
67
Qgs (nC)
18
Qgd (nC)
Configuration
25
Single
Third generation power MOSFETs from Vishay utilize
advanced processing techniques to achieve extermely low
on resistance per silicon area. This benefit, combined with
the fast switching speed and ruggedized device design that
power MOSFETs are well known for, provides the designer
with an extermely efficient reliabel deviece for use in a wide
variety of applications.
The D2PAK is a surface-mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and lowest possible on-resistance
in any existing surface mount package. The D2PAK is
suitable for high current applications because of its low
internal connection resistance and can dissipate up to 2.0 W
in a typical surface mount application.
The through-hole version (IRFZ44L, SiHFZ44L) is available
for low profile applications.
ORDERING INFORMATION
Package
Lead (Pb)-free and Halogen-free
Lead (Pb)-free
Note
a. See device orientation
D2PAK (TO-263)
SiHFZ44S-GE3
IRFZ44SPbF
D2PAK (TO-263)
SiHFZ44STRR-GE3a
-
D2PAK (TO-263)
SiHFZ44STRL-GE3a
IRFZ44STRLPbFa
I2PAK (TO-262)
SIHFZ44L-GE3
IRFZ44LPbF
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
Drain-Source Voltagef
Gate-Source Voltagef
TC = 25 °C
Continuous Drain Currente
VGS at 10 V
Continuous Drain Current
TC = 100 °C
Pulsed Drain Currenta, e
Linear Derating Factor
Single Pulse Avalanche Energyb
TA = 25 °C
Maximum Power Dissipation
TC = 25 °C
Peak Diode Recovery dV/dtc, f
Operating Junction and Storage Temperature Range
for 10 s
Soldering Recommendations (Peak Temperatured)
SYMBOL
VDS
VGS
ID
IDM
EAS
PD
dV/dt
TJ, Tstg
LIMIT
60
± 20
50
36
200
1.0
100
3.7
150
4.5
- 55 to + 175
300
UNIT
V
A
W/°C
mJ
W
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. VDD = 25 V; starting TJ = 25 °C, L = 44 μH, Rg = 25 , IAS = 51 A (see fig. 12)
c. ISD 51 A, dI/dt 250 A/μs, VDD VDS, TJ 175 °C
d. 1.6 mm from case
e. Calculated continuous current based on maximum allowable junction temperature
f. Uses IRFZ44, SiHFZ44 data and test conditions
S21-0932-Rev. D, 13-Sep-2021
Document Number: 91293
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFZ44S, IRFZ44L, SiHFZ44S, SiHFZ44L
www.vishay.com
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum Junction-to-Ambient
(PCB Mounted, steady-state)a
Maximum Junction-to-Case
SYMBOL
TYP.
MAX.
RthJA
-
40
RthJC
-
1.0
UNIT
°C/W
Note
a. When mounted on 1” square PCB (FR-4 or G-10 material)
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
VDS
VGS = 0, ID = 250 μA
60
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.06
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
Gate-Source Leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 60 V, VGS = 0 V
-
-
25
VDS = 48 V, VGS = 0 V, TJ = 150 °C
-
-
250
-
-
0.028
15
-
-
S
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = 31 Ab
VGS = 10 V
VDS = 25 V, ID = 31
Ab
μA
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Turn-On Delay Time
td(on)
Rise Time
Turn-Off Delay Time
tr
td(off)
Fall Time
tf
Internal Source Inductance
LS
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5 d
VGS = 10 V
ID = 51 A, VDS = 48 V,
see fig. 6 and 13b
VDD = 30 V, ID = 51 A,
Rg = 9.1 , RD = 0,55 ,
see fig. 10b
Between lead, and center of die contact
-
1900
-
-
920
-
-
170
-
-
-
67
-
-
18
-
-
25
-
14
-
-
110
-
-
45
-
-
92
-
-
7.5
-
-
-
50d
-
-
200
-
-
2.5
-
120
180
ns
-
530
800
nC
pF
nC
ns
nH
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 51 A, VGS = 0 Vb
TJ = 25 °C, IF = 51 A, dI/dt = 100 A/μsb, d
V
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width 300 μs; duty cycle 2 %
c. Uses IRFZ44, SiHFZ44 data and test conditions
d. Calculated continuous current based on maximum allowable junction temperature
S21-0932-Rev. D, 13-Sep-2021
Document Number: 91293
2
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFZ44S, IRFZ44L, SiHFZ44S, SiHFZ44L
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics
Fig. 2 - Typical Transfer Characteristics
Fig. 1 - Typical Output Characteristics
Fig. 3 - Normalized On-Resistance vs. Temperature
S21-0932-Rev. D, 13-Sep-2021
Document Number: 91293
3
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFZ44S, IRFZ44L, SiHFZ44S, SiHFZ44L
www.vishay.com
Fig. 4 - Typical Capacitance vs. Drain-to-Source Voltage
Vishay Siliconix
Fig. 6 - Typical Source-Drain Diode Forward Voltage
’
Fig. 5 - Typical Gate Charge vs. Gate-to-Source Voltage
S21-0932-Rev. D, 13-Sep-2021
Fig. 7 - Maximum Safe Operating Area
Document Number: 91293
4
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFZ44S, IRFZ44L, SiHFZ44S, SiHFZ44L
www.vishay.com
Vishay Siliconix
rD
VDS
VGS
D.U.T.
Rg
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 2a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on)
Fig. 8 - Maximum Drain Current vs. Case Temperature
tr
td(off) tf
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
S21-0932-Rev. D, 13-Sep-2021
Document Number: 91293
5
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFZ44S, IRFZ44L, SiHFZ44S, SiHFZ44L
www.vishay.com
Vishay Siliconix
VDS
L
Vary tp to obtain
required IAS
VDS
tp
VDD
D.U.T
Rg
+
-
IAS
V DD
VDS
10 V
tp
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
IAS
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
S21-0932-Rev. D, 13-Sep-2021
Fig. 13b - Gate Charge Test Circuit
Document Number: 91293
6
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFZ44S, IRFZ44L, SiHFZ44S, SiHFZ44L
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91293.
S21-0932-Rev. D, 13-Sep-2021
Document Number: 91293
7
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
A
(Datum A)
3
A
4
4
L1
B
A
E
c2
H
Gauge
plane
4
0° to 8°
5
D
B
Detail A
Seating plane
H
1
2
C
3
C
L
L3
L4
Detail “A”
Rotated 90° CW
scale 8:1
L2
B
A1
B
A
2 x b2
c
2xb
E
0.010 M A M B
± 0.004 M B
2xe
Plating
5
b1, b3
Base
metal
c1
(c)
D1
4
5
(b, b2)
Lead tip
MILLIMETERS
DIM.
MIN.
MAX.
View A - A
INCHES
MIN.
4
E1
Section B - B and C - C
Scale: none
MILLIMETERS
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1
6.86
-
0.270
-
A1
0.00
0.25
0.000
0.010
E
9.65
10.67
0.380
0.420
6.22
-
0.245
-
b
0.51
0.99
0.020
0.039
E1
b1
0.51
0.89
0.020
0.035
e
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
L
1.78
2.79
0.070
0.110
2.54 BSC
0.100 BSC
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.066
c1
0.38
0.58
0.015
0.023
L2
-
1.78
-
0.070
c2
1.14
1.65
0.045
0.065
L3
D
8.38
9.65
0.330
0.380
L4
0.25 BSC
4.78
5.28
0.010 BSC
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364
Revision: 15-Sep-08
www.vishay.com
1
Package Information
Vishay Siliconix
I2PAK (TO-262) (HIGH VOLTAGE)
A
(Datum A)
E
B
c2
A
E
A
L1
Seating
plane
D1
D
C
L2
C
B
B
L
A
c
3 x b2
E1
A1
3xb
Section A - A
Base
metal
2xe
b1, b3
Plating
0.010 M A M B
c1
c
(b, b2)
Lead tip
Section B - B and C - C
Scale: None
MILLIMETERS
INCHES
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
DIM.
MIN.
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D
8.38
9.65
0.330
0.380
A1
2.03
3.02
0.080
0.119
D1
6.86
-
0.270
-
b
0.51
0.99
0.020
0.039
E
9.65
10.67
0.380
0.420
b1
0.51
0.89
0.020
0.035
E1
6.22
-
0.245
-
b2
1.14
1.78
0.045
0.070
e
b3
1.14
1.73
0.045
0.068
L
13.46
14.10
0.530
0.555
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.065
c1
0.38
0.58
0.015
0.023
L2
3.56
3.71
0.140
0.146
c2
1.14
1.65
0.045
0.065
2.54 BSC
0.100 BSC
ECN: S-82442-Rev. A, 27-Oct-08
DWG: 5977
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outmost
extremes of the plastic body.
3. Thermal pad contour optional within dimension E, L1, D1, and E1.
4. Dimension b1 and c1 apply to base metal only.
Document Number: 91367
Revision: 27-Oct-08
www.vishay.com
1
AN826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead
0.420
0.355
0.635
(16.129)
(9.017)
(10.668)
0.145
(3.683)
0.135
(3.429)
0.200
0.050
(5.080)
(1.257)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 73397
11-Apr-05
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1
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Revision: 01-Jan-2022
1
Document Number: 91000