IRL640S, SiHL640S
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Vishay Siliconix
Power MOSFET
D
FEATURES
S
•
•
•
•
•
•
•
•
D2PAK (TO-263)
G
G D
S
N-Channel MOSFET
Note
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details
PRODUCT SUMMARY
VDS (V)
RDS(on) ()
200
VGS = 5 V
66
Qgs (nC)
9.0
Qgd (nC)
38
Configuration
DESCRIPTION
0.18
Qg max. (nC)
Surface-mount
Available in tape and reel
Dynamic dV/dt rating
Available
Repetitive avalanche rated
Logic-level gate drive
Available
RDS(on) specified at VGS = 4 V and 5 V
Fast switching
Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
Third generation power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The D2PAK is a surface-mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible
on-resistance in any existing surface-mount package. The
D2PAK is suitable for high current applications because of
its low internal connection resistance and can dissipate up
to 2.0 W in a typical surface mount application.
Single
ORDERING INFORMATION
Package
D2PAK (TO-263)
D2PAK (TO-263)
D2PAK (TO-263)
Lead (Pb)-free and Halogen-free
SiHL640S-GE3
SiHL640STRL-GE3 a
SiHL640STRR-GE3 a
Lead (Pb)-free
IRL640SPbF
IRL640STRLPbF a
IRL640STRRPbF a
Note
a. See device orientation
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
Drain-Source Voltage
SYMBOL
VDS
LIMIT
200
Gate-Source Voltage
VGS
± 10
Continuous Drain Current
VGS at 5.0 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Current a
ID
IDM
Linear Derating Factor
V
17
11
A
68
1.0
Linear Derating Factor (PCB mount) e
UNIT
0.025
W/°C
Single Pulse Avalanche Energy b
EAS
580
Repetitive Avalanche Current a
IAR
10
A
Repetitive Avalanche Energy a
EAR
13
mJ
Maximum Power Dissipation
TC = 25 °C
Maximum Power Dissipation (PCB mount) e
TA = 25 °C
Peak Diode Recovery dV/dt c
Operating Junction and Storage Temperature Range
Soldering Temperature d
For 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. VDD = 50 V, starting TJ = 25 °C, L = 3.0 mH, Rg = 25 , IAS = 17 A (see fig. 12)
c. ISD 17 A, dI/dt 150 A/μs, VDD VDS, TJ 150 °C
d. 1.6 mm from case
e. When mounted on 1” square PCB (FR-4 or G-10 material)
S21-0932-Rev. E, 13-Sep-2021
PD
125
3.1
dV/dt
5.0
TJ, Tstg
-55 to +150
300
mJ
W
V/ns
°C
Document Number: 91306
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL640S, SiHL640S
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Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
-
62
Maximum Junction-to-Ambient
(PCB mount) a
RthJA
-
-
40
Maximum Junction-to-Case (Drain)
RthJC
-
-
1.0
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material)
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
VDS
VGS = 0, ID = 250 μA
200
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.27
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
1.0
-
2.0
V
Gate-Source Leakage
IGSS
VGS = ± 10 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 200 V, VGS = 0 V
-
-
25
VDS = 160 V, VGS = 0 V, TJ = 125 °C
-
-
250
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
VGS = 5.0 V
ID = 10 A b
-
-
0.18
VGS = 4.0 V
ID = 8.5 A b
-
-
0.27
gfs
VDS = 50 V, ID = 10 A b
16
-
-
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
-
1800
-
-
400
-
-
120
-
-
-
66
-
-
9.0
μA
S
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
-
-
38
Turn-On Delay Time
td(on)
-
8.0
-
tr
-
83
-
-
44
-
-
52
-
-
4.5
-
-
7.5
-
0.3
-
1.2
-
-
17
-
-
68
Rise Time
Turn-Off Delay Time
Fall Time
td(off)
VGS = 5.0 V
ID = 17 A, VDS = 160 V,
see fig. 6 and 13 b
VDD = 100 V, ID = 17 A,
Rg = 4.6 , RD = 5.7 , see fig. 10 b
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
Gate Input Resistance
Rg
Between lead,
6 mm (0.25") from
package and center of
die contact
D
pF
nC
ns
nH
G
S
f = 1 MHz, open drain
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Current a
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 17 A, VGS = 0 V b
TJ = 25 °C, IF = 17 A, dI/dt = 100 A/μs b
-
-
2.0
V
-
310
470
ns
-
3.2
4.8
μC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width 300 μs; duty cycle 2 %
S21-0932-Rev. E, 13-Sep-2021
Document Number: 91306
2
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL640S, SiHL640S
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Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Fig. 4 - Normalized On-Resistance vs. Temperature
S21-0932-Rev. E, 13-Sep-2021
Document Number: 91306
3
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL640S, SiHL640S
www.vishay.com
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 8 - Maximum Safe Operating Area
S21-0932-Rev. E, 13-Sep-2021
Document Number: 91306
4
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL640S, SiHL640S
www.vishay.com
Vishay Siliconix
RD
VDS
VGS
D.U.T.
Rg
+
- VDD
5V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on)
tr
td(off) tf
Fig. 10b - Switching Time Waveforms
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
S21-0932-Rev. E, 13-Sep-2021
Document Number: 91306
5
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL640S, SiHL640S
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Vishay Siliconix
L
Vary tp to obtain
required IAS
VDS
VDS
tp
Rg
D.U.T.
VDD
+
-
I AS
V DD
VDS
5V
tp
0.01 W
IAS
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
5V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
S21-0932-Rev. E, 13-Sep-2021
Fig. 13b - Gate Charge Test Circuit
Document Number: 91306
6
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL640S, SiHL640S
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Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91306.
S21-0932-Rev. E, 13-Sep-2021
Document Number: 91306
7
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
A
(Datum A)
3
A
4
4
L1
B
A
E
c2
H
Gauge
plane
4
0° to 8°
5
D
B
Detail A
Seating plane
H
1
2
C
3
C
L
L3
L4
Detail “A”
Rotated 90° CW
scale 8:1
L2
B
A1
B
A
2 x b2
c
2xb
E
0.010 M A M B
± 0.004 M B
2xe
Plating
5
b1, b3
Base
metal
c1
(c)
D1
4
5
(b, b2)
Lead tip
MILLIMETERS
DIM.
MIN.
MAX.
View A - A
INCHES
MIN.
4
E1
Section B - B and C - C
Scale: none
MILLIMETERS
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1
6.86
-
0.270
-
A1
0.00
0.25
0.000
0.010
E
9.65
10.67
0.380
0.420
6.22
-
0.245
-
b
0.51
0.99
0.020
0.039
E1
b1
0.51
0.89
0.020
0.035
e
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
L
1.78
2.79
0.070
0.110
2.54 BSC
0.100 BSC
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.066
c1
0.38
0.58
0.015
0.023
L2
-
1.78
-
0.070
c2
1.14
1.65
0.045
0.065
L3
D
8.38
9.65
0.330
0.380
L4
0.25 BSC
4.78
5.28
0.010 BSC
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364
Revision: 15-Sep-08
www.vishay.com
1
AN826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead
0.420
0.355
0.635
(16.129)
(9.017)
(10.668)
0.145
(3.683)
0.135
(3.429)
0.200
0.050
(5.080)
(1.257)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 73397
11-Apr-05
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1
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Disclaimer
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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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Statements regarding the suitability of products for certain types of applications are based on Vishay's knowledge of typical
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Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited
to the warranty expressed therein.
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Revision: 01-Jan-2022
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