IRLI630G
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Vishay Siliconix
Power MOSFET
FEATURES
D
TO-220 FULLPAK
• Isolated package
• High voltage isolation = 2.5 kVRMS (t = 60 s;
f = 60 Hz)
• Sink to lead creepage distance = 4.8 mm
• Logic-level gate drive
• RDS(on) specified at VGS = 4 V and 5 V
G
G
D
S
• Fast switching
• Ease of paralleling
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
S
N-Channel MOSFET
PRODUCT SUMMARY
DESCRIPTION
VDS (V)
RDS(on) (Ω)
200
VGS = 5.0 V
Qg (Max.) (nC)
40
Qgs (nC)
5.5
Qgd (nC)
24
Configuration
Third generation power MOSFETs from Vishay provides the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and cost
effectiveness.
The TO-220 FULLPAK eliminates the need for additional
insulating hardware in commercial-industrial applications.
The molding compound used provides a high isolation
capability and a low thermal resistance between the tab and
external heatsink. This isolation is equivalent to using a 100
micron mica barrier with standard TO-220 product. The
FULLPAK is mounted to a heatsink using a single clip or by
a single screw fixing.
0.40
Single
ORDERING INFORMATION
Package
TO-220 FULLPAK
Lead (Pb)-free
IRLI630GPbF
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
Drain-source voltage
VDS
200
Gate-source voltage
VGS
± 10
Continuous drain current
VGS at 5.0 V
TC = 25 °C
TC = 100 °C
Pulsed drain current a
ID
IDM
Linear derating factor
UNIT
V
6.2
3.9
A
25
0.28
W/°C
Single pulse avalanche energy b
EAS
125
mJ
Repetitive avalanche current a
IAR
6.2
A
Repetitive avalanche energy a
EAR
3.5
mJ
Maximum power dissipation
TC = 25 °C
Peak diode recovery dV/dt c
Operating junction and storage temperature range
Soldering recommendations (peak temperature) d
Mounting torque
For 10 s
M3 screw
PD
35
W
dV/dt
5.0
V/ns
TJ, Tstg
-55 to +150
300
0.6
°C
Nm
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. VDD = 25 V, starting TJ = 25 °C, L = 2.4 mH, RG = 25 Ω, IAS = 6.2 A (see fig. 12)
c. ISD ≤ 9.0 A, dI/dt ≤ 120 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
d. 1.6 mm from case
S21-0978-Rev. C, 11-Oct-2021
Document Number: 91313
1
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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IRLI630G
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Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum junction-to-ambient
RthJA
-
65
Maximum junction-to-case (drain)
RthJC
-
3.6
UNIT
°C/W
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS
VGS = 0 V, ID = 250 μA
200
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.27
-
V/°C
Static
Drain-ssource breakdown voltage
VDS temperature coefficient
VGS(th)
VDS = VGS, ID = 250 μA
1.0
-
2.0
V
Gate-source leakage
IGSS
VGS = ± 10 V
-
-
± 100
nA
Zero gate voltage drain current
IDSS
VDS = 200 V, VGS = 0 V
-
-
25
VDS = 160 V, VGS = 0 V, TJ = 125 °C
-
-
250
Gate-source threshold voltage
Drain-source on-state resistance
Forward transconductance
RDS(on)
gfs
VGS = 5.0 V
ID = 3.7 A b
-
-
0.40
VGS =4.0 V
ID = 3.1 A b
-
-
0.50
4.8
-
-
-
1100
-
-
220
-
-
70
-
-
-
40
-
-
5.5
VDS = 50 V, ID = 5.4 A b
μA
Ω
S
Dynamic
Input capacitance
Ciss
Output capacitance
Coss
Reverse transfer capacitance
Crss
Total gate charge
Qg
Gate-source charge
Qgs
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
VGS = 10 V
ID = 9.0 A, VDS = 160 V,
see fig. 6 and 13 b
Gate-drain charge
Qgd
-
-
24
Turn-on delay time
td(on)
-
8.0
-
Rise time
Turn-off delay time
Fall time
tr
td(off)
VDD = 100 V, ID = 9.0 A,
RG = 6.0 Ω, RD= 11Ω,
see fig. 10 b
tf
Internal drain inductance
LD
Internal source inductance
LS
Between lead,
6 mm (0.25") from
package and center of
die contact
D
-
57
-
-
38
-
-
33
-
-
4.5
-
-
7.5
-
-
-
6.2
-
-
25
pF
nC
ns
nH
G
S
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
Pulsed diode forward current a
Body diode voltage
IS
ISM
VSD
Body diode reverse recovery time
trr
Body diode reverse recovery charge
Qrr
Forward turn-on time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 6.2 A, VGS = 0
S
Vb
TJ = 25 °C, IF = 9.0 A, dI/dt = 100 A/μs b
-
-
2.0
V
-
230
350
ns
-
1.7
2.6
μC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %
S21-0978-Rev. C, 11-Oct-2021
Document Number: 91313
2
For technical questions, contact: hvmos.techsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRLI630G
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Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Fig. 4 - Normalized On-Resistance vs. Temperature
S21-0978-Rev. C, 11-Oct-2021
Document Number: 91313
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRLI630G
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Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
S21-0978-Rev. C, 11-Oct-2021
Vishay Siliconix
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
Document Number: 91313
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IRLI630G
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Vishay Siliconix
RD
VDS
VGS
D.U.T.
RG
+
- VDD
5V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
tr
td(off) tf
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
S21-0978-Rev. C, 11-Oct-2021
Document Number: 91313
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRLI630G
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Vishay Siliconix
L
Vary tp to obtain
required IAS
VDS
VDS
tp
VDD
D.U.T.
RG
+
-
I AS
V DD
VDS
5V
0.01 Ω
tp
Fig. 12a - Unclamped Inductive Test Circuit
IAS
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
QG
5V
QGS
QGD
50 kΩ
12 V
0.2 µF
0.3 µF
VG
+
D.U.T.
Charge
-
VDS
VGS
3 mA
Fig. 13a - Basic Gate Charge Waveform
IG
ID
Current sampling resistors
Fig. 13b - Gate Charge Test Circuit
S21-0978-Rev. C, 11-Oct-2021
Document Number: 91313
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRLI630G
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Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91313.
S21-0978-Rev. C, 11-Oct-2021
Document Number: 91313
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
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Vishay Siliconix
TO-220 FULLPAK (High Voltage)
OPTION 1: FACILITY CODE = 9
A
F
G
Q1
E
D
ØR
A3
L1
3 x b2
3 x b1
Mold flash
bleeding
Q
L
Exposed Cu
3xb
2xe
C
Bottom view
MILLIMETERS
DIM.
MIN.
NOM.
A
4.60
4.70
4.80
b
0.70
0.80
0.91
b1
1.20
1.30
1.47
b2
1.10
1.20
1.30
C
0.45
0.50
0.63
D
15.80
15.87
15.97
e
MAX.
2.54 BSC
E
10.00
10.10
F
2.44
2.54
10.30
2.64
G
6.50
6.70
6.90
L
12.90
13.10
13.30
L1
3.13
3.23
3.33
Q
2.65
2.75
2.85
Q1
3.20
3.30
3.40
ØR
3.08
3.18
3.28
Notes
1. To be used only for process drawing
2. These dimensions apply to all TO-220 FULLPAK leadframe versions 3 leads
3. All critical dimensions should C meet Cpk > 1.33
4. All dimensions include burrs and plating thickness
5. No chipping or package damage
6. Facility code will be the 1st character located at the 2nd row of the unit marking
Revision: 08-Apr-2019
Document Number: 91359
1
For technical questions, contact: hvmos.techsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
OPTION 2: FACILITY CODE = Y
A
A1
E
ØP
n
d1
d3
D
u
L1
V
L
b3
A2
b2
c
b
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
A
4.570
4.830
0.180
0.190
A1
2.570
2.830
0.101
0.111
A2
2.510
2.850
0.099
0.112
b
0.622
0.890
0.024
0.035
b2
1.229
1.400
0.048
0.055
b3
1.229
1.400
0.048
0.055
c
0.440
0.629
0.017
0.025
D
8.650
9.800
0.341
0.386
d1
15.88
16.120
0.622
0.635
d3
12.300
12.920
0.484
0.509
E
10.360
10.630
0.408
e
2.54 BSC
0.419
0.100 BSC
L
13.200
13.730
0.520
0.541
L1
3.100
3.500
0.122
0.138
n
6.050
6.150
0.238
0.242
ØP
3.050
3.450
0.120
0.136
u
2.400
2.500
0.094
0.098
V
0.400
0.500
0.016
0.020
ECN: E19-0180-Rev. D, 08-Apr-2019
DWG: 5972
Notes
1. To be used only for process drawing
2. These dimensions apply to all TO-220 FULLPAK leadframe versions 3 leads
3. All critical dimensions should C meet Cpk > 1.33
4. All dimensions include burrs and plating thickness
5. No chipping or package damage
6. Facility code will be the 1st character located at the 2nd row of the unit marking
Revision: 08-Apr-2019
Document Number: 91359
2
For technical questions, contact: hvmos.techsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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