IRLU110PBF

IRLR110, IRLU110, SiHLR110, SiHLU110 Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Halogen-free According to IEC 61249-2-21 Definition • Dynamic dV/dt Rating • Repetitive Avalanche Rated • Surface Mount (IRLR110, SiHLR110) • Straight Lead (IRLU110, SiHLU110) • Available in Tape and Reel • Logic-Level Gate Drive • RDS(on) Specified at VGS = 4 V and 5 V • Compliant to RoHS Directive 2002/95/EC 100 RDS(on) (Ω) VGS = 5.0 V 0.54 Qg (Max.) (nC) 6.1 Qgs (nC) 2.0 Qgd (nC) 3.3 Configuration Single D DPAK (TO-252) DESCRIPTION IPAK (TO-251) Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The DPAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRLU, SiHLU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 W are possible in typical surface mount applications. D D G G S G D S S N-Channel MOSFET ORDERING INFORMATION Package Lead (Pb)-free and Halogen-free Lead (Pb)-free SnPb DPAK (TO-252) SiHLR110-GE3 IRLR110PbF SiHLR110-E3 IRLR110 SiHLR110 DPAK (TO-252) SiHLR110TR-GE3 IRLR110TRPbFa SiHLR110T-E3a IRLR110TRa SiHLR110Ta DPAK (TO-252) SiHLR110TRL-GE3 IRLR110TRLPbF SiHLR110TL-E3 IRLR110TRLa SiHLR110TLa IPAK (TO-251) SiHLU110-GE3 IRLU110PbF SiHLU110-E3 IRLU110 SiHLU110 Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta Linear Derating Factor Linear Derating Factor (PCB Mount)e Single Pulse Avalanche Energyb Repetitive Avalanche Currenta Repetitive Avalanche Energya Maximum Power Dissipation Maximum Power Dissipation (PCB Mount)e Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) SYMBOL VDS VGS VGS at 5.0 V TC = 25 °C TC = 100 °C ID IDM EAS IAR EAR TC = 25 °C TA = 25 °C PD dV/dt TJ, Tstg for 10 s LIMIT 100 ± 10 4.3 2.7 17 0.20 0.020 100 4.3 2.5 25 2.5 5.5 - 55 to + 150 260d UNIT V A W/°C mJ A mJ W V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 25 V, starting TJ = 25 °C, L = 8.1 mH, Rg = 25 Ω, IAS = 4.3 A (see fig. 12). c. ISD ≤ 5.6 A, dI/dt ≤ 140 A/μs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. e. When mounted on 1" square PCB (FR-4 or G-10 material). * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91323 S10-1139-Rev. C, 17-May-10 www.vishay.com 1 IRLR110, IRLU110, SiHLR110, SiHLU110 Vishay Siliconix THERMAL RESISTANCE RATINGS SYMBOL MIN. TYP. MAX. Maximum Junction-to-Ambient PARAMETER RthJA - - 110 Maximum Junction-to-Ambient (PCB Mount)a RthJA - - 50 Maximum Junction-to-Case (Drain) RthJC - - 5.0 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient VDS VGS = 0 V, ID = 250 μA 100 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.12 - V/°C VGS(th) VDS = VGS, ID = - 250 μA 1.0 - 2.0 V Gate-Source Leakage IGSS VGS = ± 10 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 100 V, VGS = 0 V - - 25 VDS = 80 V, VGS = 0 V, TJ = 125 °C - - 250 Gate-Source Threshold Voltage Drain-Source On-State Resistance Forward Transconductance RDS(on) gfs VGS = 5.0 V ID = 2.6 Ab - - 0.54 VGS = 4.0 V Ab - - 0.76 2.3 - - - 250 - - 80 - ID = 2.2 VDS = 50 V, ID = 2.6 A μA Ω S Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 VGS = 5.0 V ID = 5.6 A, VDS = 80 V, see fig. 6 and 13b - 15 - - - 6.1 - - 2.0 Gate-Drain Charge Qgd - - 3.3 Turn-On Delay Time td(on) - 9.3 - Rise Time Turn-Off Delay Time tr td(off) Fall Time tf Internal Drain Inductance LD Internal Source Inductance LS VDD = 50 V, ID = 5.6 A, Rg = 12 Ω, RD = 8.4 Ω, see fig. 10b Between lead, 6 mm (0.25") from package and center of die contactc D - 47 - - 16 - - 17 - - 4.5 - - 7.5 - - - 4.3 - - 17 - - 2.5 pF nC ns nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS =4.3 A, VGS = 0 Vb TJ = 25 °C, IF = 5.6 A, dI/dt = 100 A/μsb V - 100 130 ns - 0.50 0.65 μC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %. www.vishay.com 2 Document Number: 91323 S10-1139-Rev. C, 17-May-10 IRLR110, IRLU110, SiHLR110, SiHLU110 Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 2 - Typical Output Characteristics, TC = 150 °C Document Number: 91323 S10-1139-Rev. C, 17-May-10 Fig. 3 - Typical Transfer Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature www.vishay.com 3 IRLR110, IRLU110, SiHLR110, SiHLU110 Vishay Siliconix Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.vishay.com 4 Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area Document Number: 91323 S10-1139-Rev. C, 17-May-10 IRLR110, IRLU110, SiHLR110, SiHLU110 Vishay Siliconix VDS VGS RD D.U.T. Rg + - VDD 5.0 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % 10 % VGS td(on) tr td(off) tf Fig. 9 - Maximum Drain Current vs. Case Temperature Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Document Number: 91323 S10-1139-Rev. C, 17-May-10 www.vishay.com 5 IRLR110, IRLU110, SiHLR110, SiHLU110 Vishay Siliconix L Vary tp to obtain required IAS VDS VDS tp VDD D.U.T Rg + - I AS V DD VDS 5.0 V 0.01 Ω tp Fig. 12a - Unclamped Inductive Test Circuit IAS Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG VGS 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.vishay.com 6 Fig. 13b - Gate Charge Test Circuit Document Number: 91323 S10-1139-Rev. C, 17-May-10 IRLR110, IRLU110, SiHLR110, SiHLU110 Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + + - - Rg • • • • dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91323. Document Number: 91323 S10-1139-Rev. C, 17-May-10 www.vishay.com 7 Package Information www.vishay.com Vishay Siliconix TO-252AA Case Outline VERSION 1: FACILITY CODE = Y E A C2 H D D1 L3 b3 e b2 e1 L gage plane height (0.5 mm) L4 b L5 E1 C A1 MILLIMETERS DIM. MIN. A 2.18 MAX. 2.38 A1 - 0.127 b 0.64 0.88 b2 0.76 1.14 b3 4.95 5.46 C 0.46 0.61 C2 0.46 0.89 D 5.97 6.22 D1 4.10 - E 6.35 6.73 E1 4.32 - H 9.40 10.41 e 2.28 BSC e1 4.56 BSC L 1.40 1.78 L3 0.89 1.27 L4 - 1.02 L5 1.01 1.52 Note • Dimension L3 is for reference only Revision: 16-Dec-2019 Document Number: 71197 1 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix VERSION 2: FACILITY CODE = N E e A b3 E1 E1/2 c2 θ e L4 L5 L6 H D L3 D1 θ 0.25 (3°) DETAIL "B" C A B (3°) DETAIL "B" A1 C L (L1) b1 SEATING C PLANE θ L2 GAUGE PLANE H C (b) c1 3x b 2x e c 2x b2 MILLIMETERS MILLIMETERS DIM. A MIN. 2.18 MAX. DIM. MIN. 2.39 L 1.50 A1 - 0.13 L1 b 0.65 0.89 L2 MAX. 1.78 2.74 ref. 0.51 BSC b1 0.64 0.79 L3 b2 0.76 1.13 L4 - 1.02 b3 4.95 5.46 L5 1.14 1.49 c 0.46 0.61 L6 0.65 0.85 c1 0.41 0.56  0° 10° 1 0° 15° 2 25° 35° c2 0.46 0.60 D 5.97 6.22 D1 5.21 - E 6.35 6.73 E1 4.32 e H 2.29 BSC 9.94 0.89 1.27 Notes • Dimensioning and tolerance confirm to ASME Y14.5M-1994 • All dimensions are in millimeters. Angles are in degrees • Heat sink side flash is max. 0.8 mm • Radius on terminal is optional 10.34 ECN: E19-0649-Rev. Q, 16-Dec-2019 DWG: 5347 Revision: 16-Dec-2019 Document Number: 71197 2 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-251AA (HIGH VOLTAGE) 4 3 E1 E Thermal PAD 4 b4 θ2 4 A 0.010 0.25 M C A B L2 4 c2 A θ1 B D D1 A C 3 Seating plane 5 C L1 L3 (Datum A) C L B B A A1 3 x b2 View A - A 2xe c 3xb 0.010 0.25 M C A B Plating 5 b1, b3 Base metal Lead tip c1 (c) 5 (b, b2) Section B - B and C - C MILLIMETERS DIM. MIN. MAX. INCHES MIN. MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 2.18 2.39 0.086 0.094 D1 5.21 - 0.205 - A1 0.89 1.14 0.035 0.045 E 6.35 6.73 0.250 0.265 4.32 - 0.170 - b 0.64 0.89 0.025 0.035 E1 b1 0.65 0.79 0.026 0.031 e b2 0.76 1.14 0.030 0.045 L 8.89 9.65 0.350 0.380 b3 0.76 1.04 0.030 0.041 L1 1.91 2.29 0.075 0.090 b4 4.95 5.46 0.195 0.215 L2 0.89 1.27 0.035 0.050 2.29 BSC 2.29 BSC c 0.46 0.61 0.018 0.024 L3 1.14 1.52 0.045 0.060 c1 0.41 0.56 0.016 0.022 θ1 0' 15' 0' 15' c2 0.46 0.86 0.018 0.034 θ2 25' 35' 25' 35' D 5.97 6.22 0.235 0.245 ECN: S-82111-Rev. A, 15-Sep-08 DWG: 5968 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimension are shown in inches and millimeters. 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body. 4. Thermal pad contour optional with dimensions b4, L2, E1 and D1. 5. Lead dimension uncontrolled in L3. 6. Dimension b1, b3 and c1 apply to base metal only. 7. Outline conforms to JEDEC outline TO-251AA. Document Number: 91362 Revision: 15-Sep-08 www.vishay.com 1 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR DPAK (TO-252) 0.224 0.243 0.087 (2.202) 0.090 (2.286) (10.668) 0.420 (6.180) (5.690) 0.180 0.055 (4.572) (1.397) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE Document Number: 72594 Revision: 21-Jan-08 www.vishay.com 3 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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