IRLZ24STRL

IRLZ24S, IRLZ24L, SiHLZ24S, SiHLZ24L Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Halogen-free According to IEC 61249-2-21 Definition • Surface Mount • Available in Tape and Reel • Dynamic dV/dt Rating • Logic-Level Gate Drive • RDS (on) Specified at VGS = 4 V and 5 V • 175°C Operating Temperature • Fast Switching • Compliant to RoHS Directive 2002/95/EC 60 RDS(on) (:) VGS = 5 V 0.10 Qg (Max.) (nC) 18 Qgs (nC) 4.5 Qgd (nC) 12 Configuration Single D G G DESCRIPTION D2PAK (TO-263) I2PAK (TO-262) D S Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The D2PAK is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. The D2PAK is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0 W in a typical surface mount application. The through-hole version (IRLZ24L, SiHLZ24L) is available for low-profile application. G D S S N-Channel MOSFET ORDERING INFORMATION Package Lead (Pb)-free and Halogen-free Lead (Pb)-free D2PAK (TO-263) SiHLZ24S-GE3 - I2PAK (TO-262) SiHLZ24L-GE3 IRLZ24LPbF SiHLZ24L-E3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT VDS VGS 60 ± 10 17 12 68 0.40 0.025 110 60 3.7 4.5 - 55 to + 175 300d Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta Linear Derating Factor Linear Derating Factor (PCB Mount)e Single Pulse Avalanche Energyb Maximum Power Dissipation Maximum Power Dissipation (PCB Mount)e Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) VGS at 5 V TC = 25 °C TC = 100 °C ID IDM EAS TC = 25 °C TA = 25 °C PD dV/dt TJ, Tstg for 10 s UNIT V A W/°C mJ W V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 25 V, starting TJ = 25 °C, L = 444 μH, Rg = 25 :, IAS = 17 A (see fig. 12). c. ISD d 17 A, dI/dt d 140 A/μs, VDD d VDS, TJ d 175 °C. d. 1.6 mm from case. e. When mounted on 1" square PCB (FR-4 or G-10 material) * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 90416 S11-1044-Rev. C, 30-May-11 www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLZ24S, IRLZ24L, SiHLZ24S, SiHLZ24L Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. - 62 - 40 - 2.5 Maximum Junction-to-Ambient RthJA Maximum Junction-to-Ambient RthJA (PCB Mount)a Maximum Junction-to-Case (Drain) RthJC Note a. When mounted on 1" square PCB (FR-4 or G-10 material). UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0, ID = 250 μA 60 - - V 'VDS/TJ Reference to 25 °C, ID = 1 mA - 0.060 - V/°C VGS(th) VDS = VGS, ID = 250 μA 1.0 - 2.0 V nA Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance IGSS IDSS RDS(on) gfs VGS = ± 10 V - - ± 100 VDS = 60 V, VGS = 0 V - - 25 VDS = 48 V, VGS = 0 V, TJ = 150 °C - - 250 μA VGS = 5 V ID = 10 Ab - - 0.10 VGS = 4 V Ab - - 0.14 7.3 - - - 870 - - 360 - - 53 - - - 18 ID = 8.5 VDS = 25 V, ID = 10 Ab : S Dynamic Input Capacitance Ciss Output Capacitance Coss VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs - - 4.5 Gate-Drain Charge Qgd - - 12 Turn-On Delay Time td(on) - 11 - tr - 110 - - 23 - - 41 - - 4.5 - - 7.5 - - - 17 - - 68 Rise Time Turn-Off Delay Time Fall Time td(off) VGS = 5 V ID = 17 A, VDS = 48 V, see fig. 6 and 13b VDD = 30 V, ID = 17 A, Rg = 9 :, RD = 1.7 :, see fig. 10b tf pF nC ns Dynamic Internal Drain Inductance LD Internal Source Inductance LS Between lead, 6 mm (0.25") from package and center of die contact D nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = 17 A, VGS = 0 Vb TJ = 25 °C, IF = 17 A, dI/dt = 100 A/μsb - - 1.5 V - 110 260 ns - 0.49 1.5 μC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width d 300 μs; duty cycle d 2 %. www.vishay.com 2 Document Number: 90416 S11-1044-Rev. C, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLZ24S, IRLZ24L, SiHLZ24S, SiHLZ24L Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 3 - Typical Transfer Characteristics Fig. 2 - Typical Output Characteristics, TC = 175 °C Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 90416 S11-1044-Rev. C, 30-May-11 www.vishay.com 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLZ24S, IRLZ24L, SiHLZ24S, SiHLZ24L Vishay Siliconix Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.vishay.com 4 Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area Document Number: 90416 S11-1044-Rev. C, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLZ24S, IRLZ24L, SiHLZ24S, SiHLZ24L Vishay Siliconix RD VDS VGS D.U.T. Rg + - VDD 5V Pulse width ≤ 1 μs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % Fig. 9 - Maximum Drain Current vs. Case Temperature 10 % VGS td(on) tr td(off) tf Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Document Number: 90416 S11-1044-Rev. C, 30-May-11 www.vishay.com 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLZ24S, IRLZ24L, SiHLZ24S, SiHLZ24L Vishay Siliconix L VDS VDS Vary tp to obtain required IAS tp VDD Rg D.U.T + - I AS V DD VDS 5V 0.01 W tp Fig. 12a - Unclamped Inductive Test Circuit IAS Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG 5V 12 V 0.2 μF 0.3 μF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.vishay.com 6 Fig. 13b - Gate Charge Test Circuit Document Number: 90416 S11-1044-Rev. C, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLZ24S, IRLZ24L, SiHLZ24S, SiHLZ24L Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer D.U.T. + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?90416. Document Number: 90416 S11-1044-Rev. C, 30-May-11 www.vishay.com 7 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-252AA (HIGH VOLTAGE) E b3 E1 L3 D1 D H L4 b2 b A c2 e A1 L1 L c θ L2 MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. E 6.40 6.73 0.252 0.265 L 1.40 1.77 0.055 L1 2.743 REF L2 0.070 0.108 REF 0.508 BSC 0.020 BSC L3 0.89 1.27 0.035 0.050 L4 0.64 1.01 0.025 0.040 D 6.00 6.22 0.236 0.245 H 9.40 10.40 0.370 0.409 b 0.64 0.88 0.025 0.035 b2 0.77 1.14 0.030 0.045 b3 5.21 5.46 0.205 e 2.286 BSC 0.215 0.090 BSC A 2.20 2.38 0.087 A1 0.00 0.13 0.000 0.094 0.005 c 0.45 0.60 0.018 0.024 c2 0.45 0.58 0.018 0.023 D1 5.30 - 0.209 - E1 4.40 - 0.173 - T 0' 10' 0' 10' ECN: S-81965-Rev. A, 15-Sep-08 DWG: 5973 Notes 1. Package body sizes exclude mold flash, protrusion or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side. 2. Package body sizes determined at the outermost extremes of the plastic body exclusive of mold flash, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 3. The package top may be smaller than the package bottom. 4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10 mm total in excess of "b" dimension at maximum material condition. The dambar cannot be located on the lower radius of the foot. Document Number: 91344 Revision: 15-Sep-08 www.vishay.com 1 Package Information Vishay Siliconix TO-251AA (HIGH VOLTAGE) 4 3 E1 E Thermal PAD 4 b4 θ2 4 A 0.010 0.25 M C A B L2 4 c2 A θ1 B D D1 A C 3 Seating plane 5 C L1 L3 (Datum A) C L B B A A1 3 x b2 View A - A 2xe c 3xb 0.010 0.25 M C A B Plating 5 b1, b3 Base metal Lead tip c1 (c) 5 (b, b2) Section B - B and C - C MILLIMETERS DIM. MIN. MAX. INCHES MIN. MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 2.18 2.39 0.086 0.094 D1 5.21 - 0.205 - A1 0.89 1.14 0.035 0.045 E 6.35 6.73 0.250 0.265 4.32 - 0.170 - b 0.64 0.89 0.025 0.035 E1 b1 0.65 0.79 0.026 0.031 e b2 0.76 1.14 0.030 0.045 L 8.89 9.65 0.350 0.380 b3 0.76 1.04 0.030 0.041 L1 1.91 2.29 0.075 0.090 b4 4.95 5.46 0.195 0.215 L2 0.89 1.27 0.035 0.050 2.29 BSC 2.29 BSC c 0.46 0.61 0.018 0.024 L3 1.14 1.52 0.045 0.060 c1 0.41 0.56 0.016 0.022 T1 0' 15' 0' 15' c2 0.46 0.86 0.018 0.034 T2 25' 35' 25' 35' D 5.97 6.22 0.235 0.245 ECN: S-82111-Rev. A, 15-Sep-08 DWG: 5968 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimension are shown in inches and millimeters. 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body. 4. Thermal pad contour optional with dimensions b4, L2, E1 and D1. 5. Lead dimension uncontrolled in L3. 6. Dimension b1, b3 and c1 apply to base metal only. 7. Outline conforms to JEDEC outline TO-251AA. Document Number: 91362 Revision: 15-Sep-08 www.vishay.com 1 Package Information Vishay Siliconix I2PAK (TO-262) (HIGH VOLTAGE) A (Datum A) E B c2 A E A L1 Seating plane D1 D C L2 C B B L A c 3 x b2 E1 A1 3xb Section A - A Base metal 2xe b1, b3 Plating 0.010 M A M B c1 c (b, b2) Lead tip Section B - B and C - C Scale: None MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D 8.38 9.65 0.330 0.380 A1 2.03 3.02 0.080 0.119 D1 6.86 - 0.270 - b 0.51 0.99 0.020 0.039 E 9.65 10.67 0.380 0.420 b1 0.51 0.89 0.020 0.035 E1 6.22 - 0.245 - b2 1.14 1.78 0.045 0.070 e b3 1.14 1.73 0.045 0.068 L 13.46 14.10 0.530 0.555 c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.065 c1 0.38 0.58 0.015 0.023 L2 3.56 3.71 0.140 0.146 c2 1.14 1.65 0.045 0.065 2.54 BSC 0.100 BSC ECN: S-82442-Rev. A, 27-Oct-08 DWG: 5977 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outmost extremes of the plastic body. 3. Thermal pad contour optional within dimension E, L1, D1, and E1. 4. Dimension b1 and c1 apply to base metal only. Document Number: 91367 Revision: 27-Oct-08 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer  ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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