SI1304BDL-T1-E3

Si1304BDL Vishay Siliconix N-Channel 30 V (D-S) MOSFET FEATURES PRODUCT SUMMARY RDS(on) (Ω) ID (A)a 0.270 at VGS = 4.5 V 0.90 0.385 at VGS = 2.5 V 0.75 VDS (V) 30 Qg (Typ.) 1.1 • Halogen-free According to IEC 61249-2-21 Definition • TrenchFET® Power MOSFET • 100 % Rg Tested • Compliant to RoHS Directive 2002/95/EC SC-70 (3-LEADS) G 1 D 3 S D KF XX YY Marking Code Lot Traceability and Date Code 2 G Part # Code Top View S Ordering Information: Si1304BDL-T1-E3 (Lead (Pb)-free) Si1304BDL-T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) Parameter Symbol Limit Drain-Source Voltage VDS 30 Gate-Source Voltage VGS ± 12 TC = 25 °C Continuous Drain Current (TJ = 150 °C) TC = 70 °C TA = 25 °C Continuous Source-Drain Diode Current 0.71 ID 0.85b, c 0.68b, c IDM TC = 25 °C TA = 25 °C TC = 70 °C TA = 25 °C 0.31 IS 0.28b, c 0.37 0.24 PD W 0.34b, c 0.22b, c TA = 70 °C Operating Junction and Storage Temperature Range A 4 TC = 25 °C Maximum Power Dissipation V 0.90 TA = 70 °C Pulsed Drain Current Unit TJ, Tstg - 55 to 150 °C THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Maximum Junction-to-Ambientb, d t≤5s RthJA 315 375 Maximum Junction-to-Foot (Drain) Steady State RthJF 285 340 Unit °C/W Notes: a. Based on TC = 25 °C. b. Surface mounted on 1" x 1" FR4 board. c. t = 5 s. d. Maximum under steady state conditions is 360 °C/W. Document Number: 73480 S11-2000-Rev. D, 10-Oct-11 www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si1304BDL Vishay Siliconix SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) Parameter Symbol Test Conditions Min. VDS VGS = 0 V, ID = 250 µA 30 Typ. Max. Unit Static Drain-Source Breakdown Voltage VDS Temperature Coefficient ΔVDS/TJ ID = 250 µA VGS(th) Temperature Coefficient ΔVGS(th)/TJ Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA IGSS Gate-Source Leakage Zero Gate Voltage Drain Current IDSS On-State Drain Currenta ID(on) Drain-Source On-State Resistancea Forward Transconductancea gfs mV/°C 3 1.3 V VDS = 0 V, VGS = ± 12 V ± 100 nA VDS = 30 V, VGS = 0 V 1 VDS = 30 V, VGS = 0 V, TJ = 70 °C 5 VDS ≥ 5 V, VGS = 4.5 V RDS(on) V 27.3 0.6 4 µA A VGS = 4.5 V, ID = 0.9 0.216 0.270 VGS = 2.5 V, ID = 0.75 0.308 0.385 VDS = 15 V, ID = 0.9 2 Ω S Dynamicb Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Gate Resistance Turn-On Delay Time 30 VDS = 15 V, VGS = 4.5 V, ID = 0.9 1.8 2.7 1.1 1.7 VDS = 15 V, VGS = 2.5 V, ID = 0.9 td(off) Fall Time 0.4 nC 0.6 f = 1 MHz Rg tr pF 20 td(on) Rise Time Turn-Off Delay Time 100 VDS = 15 V, VGS = 0 V, f = 1 MHz VDD = 15 V, RL = 22 Ω ID ≅ 0.68 A, VGEN = 4.5 V, Rg = 1 Ω tf 0.5 1.5 2.3 10 15 30 45 5 25 10 15 Ω ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode IS Pulse Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Reverse Recovery Fall Time ta Reverse Recovery Rise Time tb TC = 25 °C 0.31 4 IS = 0.28 A IF = 0.28 A, dI/dt = 100 A/µs, TJ = 25 °C A 0.8 1.2 V 50 75 ns 105 160 nC 34 16 ns Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com 2 Document Number: 73480 S11-2000-Rev. D, 10-Oct-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si1304BDL Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 2.0 4 1.5 3 I D - Drain Current (A) I D - Drain Current (A) VGS = 5 V thru 3 V VGS = 2.5 V 2 VGS = 2.0 V 1.0 TA = - 55 °C 0.5 1 TA = 25 °C TA = 125 °C VGS = 1.5 V 0 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.0 3.0 0.5 1.5 2.0 2.5 VGS - Gate-to-Source Voltage (V) VDS - Drain-to-Source Voltage (V) Output Characteristics Transfer Characteristics Curves vs. Temperature 0.6 180 150 0.5 C - Capacitance (pF) R DS(on) - On-Resistance (Ω) 1.0 VGS = 2.5 V 0.4 0.3 VGS = 4.5 V 120 Ciss 90 60 0.2 Coss 30 Crss 0.1 0 0 1 2 3 4 0 5 15 20 25 ID - Drain Current (A) VDS - Drain-Source Voltage (V) Capacitance 30 2.0 ID = 0.91 A ID = 0.90 A 4 1.7 3 VDS = 24 V 2 1 VGS = 4.5 V, ID = 0.9 A (Normalized) VDS = 15 V R DS(on) - On-Resistance VGS - Gate-to-Source Voltage (V) 10 On-Resistance vs. Drain Current 5 0 0.0 5 1.4 1.1 VGS = 2.5 V, ID = 0.75 A 0.8 0.5 1.0 1.5 2.0 0.5 - 50 - 25 0 25 50 75 100 125 Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C) Gate Charge On-Resistance vs. Junction Temperature Document Number: 73480 S11-2000-Rev. D, 10-Oct-11 150 www.vishay.com 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si1304BDL Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 0.8 10 R DS(on) - On-Resistance (Ω) I S - Source Current (A) ID = 0.9 A TJ = 150 °C 1 TJ = 25 °C 0.1 0.6 TA = 125 °C 0.4 0.2 TA = 25 °C 0 0.01 0.3 0.6 0.9 0 1.2 1 2 3 4 5 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) Forward Diode Voltage vs. Temperature RDS(on) vs. VGS vs. Temperature 1.4 20 1.3 16 ID = 250 µA 1.1 Power (W) VGS(th) Variance (V) 1.2 1.0 0.9 12 TA = 25 °C 8 0.8 4 0.7 0.6 - 50 - 25 0 25 50 75 100 125 0 10-3 150 10-2 TJ - Temperature (°C) 10-1 1 10 100 600 Time (s) Single Pulse Power, Junction-to-Ambient Threshold Voltage 10 Limited by RDS(on)* 1 ms I D - Drain Current (A) 1 10 ms 100 ms 0.1 1s 10 s 0.01 TA = 25 °C Single Pulse DC BVDSS Limited 0.001 0.1 1000 1 100 10 VDS - Drain-to-Source Voltage (V) * VGS > minimum V GS at which R DS(on) is specified Safe Operating Area www.vishay.com 4 Document Number: 73480 S11-2000-Rev. D, 10-Oct-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si1304BDL Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 1.2 0.4 Power Dissipation (W) I D - Drain Current (A) 1.0 0.8 0.6 0.4 0.3 0.2 0.1 0.2 0.0 0.0 0 25 50 75 100 TC - Case Temperature (°C) Current Derating* 125 150 25 50 75 100 125 150 T C - Case Temperature (°C) Power, Derating * The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. Document Number: 73480 S11-2000-Rev. D, 10-Oct-11 www.vishay.com 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si1304BDL Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 0.2 Notes: 0.1 PDM 0.1 0.05 t1 t2 1. Duty Cycle, D = 0.02 t1 t2 2. Per Unit Base = R thJA = 360 °C/W 3. T JM - TA = PDMZthJA(t) Single Pulse 0.01 10-4 10-3 4. Surface Mounted 10-2 10-1 1 Square Wave Pulse Duration (s) 10 100 600 Normalized Thermal Transient Impedance, Junction-to-Ambient Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10-1 Square Wave Pulse Duration (s) 1 10 Normalized Thermal Transient Impedance, Junction-to-Foot Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?73480. www.vishay.com 6 Document Number: 73480 S11-2000-Rev. D, 10-Oct-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix SCĆ70: 3ĆLEADS MILLIMETERS 3 E1 E 1 2 e b e1 D c A2 A L 0.08 c A1 Dim A A1 A2 b c D E E1 e e1 L INCHES Min Nom Max Min Nom Max 0.90 – 1.10 0.035 – 0.043 – – 0.10 – – 0.004 0.80 – 1.00 0.031 – 0.039 0.25 – 0.40 0.010 – 0.016 0.10 – 0.25 0.004 – 0.010 1.80 2.00 2.20 0.071 0.079 0.087 1.80 2.10 2.40 0.071 0.083 0.094 1.15 1.25 1.35 0.045 0.049 0.053 0.65BSC 0.026BSC 1.20 1.30 1.40 0.047 0.051 0.055 0.10 0.20 0.30 0.004 0.008 0.012 7_Nom 7_Nom ECN: S-03946—Rev. C, 09-Jul-01 DWG: 5549 Document Number: 71153 06-Jul-01 www.vishay.com 1 AN813 Vishay Siliconix Single-Channel LITTLE FOOTR SC-70 3-Pin and 6-Pin MOSFET Recommended Pad Pattern and Thermal Peformance INTRODUCTION BASIC PAD PATTERNS This technical note discusses pin-outs, package outlines, pad patterns, evaluation board layout, and thermal performance for single-channel LITTLE FOOT power MOSFETs in the SC-70 package. These new Vishay Siliconix devices are intended for small-signal applications where a miniaturized package is needed and low levels of current (around 350 mA) need to be switched, either directly or by using a level shift configuration. Vishay provides these single devices with a range of on-resistance specifications and in both traditional 3-pin and new 6-pin versions. The new 6-pin SC-70 package enables improved on-resistance values and enhanced thermal performance compared to the 3-pin package. See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/doc?72286) for the basic pad layout and dimensions for the 3-pin SC-70 and the 6-pin SC-70. These pad patterns are sufficient for the low-power applications for which this package is intended. Increasing the pad pattern has little effect on thermal resistance for the 3-pin device, reducing it by only 10% to 15%. But for the 6-pin device, increasing the pad patterns yields a reduction in thermal resistance on the order of 35% when using a 1-inch square with full copper on both sides of the printed circuit board (PCB). The availability of four drain leads rather than the traditional single drain lead allows a better thermal path from the package to the PCB and external environment. PIN-OUT Figure 1 shows the pin-out description and Pin 1 identification for the single-channel SC-70 device in both 3-pin and 6-pin configurations. The pin-out of the 6-pin device allows the use of four pins as drain leads, which helps to reduce on-resistance and junction-to-ambient thermal resistance. SOT-323 SC-70 (3-LEADS) SOT-363 SC-70 (6-LEADS) Top View G Top View 1 3 S D 2 D 1 6 D 2 5 G 3 4 EVALUATION BOARDS FOR THE SINGLE SC70-3 AND SC70-6 Figure 2 shows the 3-pin and 6-pin SC-70 evaluation boards (EVB). Both measure 0.6 inches by 0.5 inches. Their copper pad traces are the same as described in the previous section, Basic Pad Patterns. Both boards allow interrogation from the outer pins to 6-pin DIP connections, permitting test sockets to be used in evaluation testing. The thermal performance of the single SC-70 has been measured on the EVB for both the 3-pin and 6-pin devices, the results shown in Figures 3 and 4. The minimum recommended footprint on the evaluation board was compared with the industry standard of 1-inch square FR4 PCB with copper on both sides of the board. FIGURE 1. For package dimensions see outline drawings: SC-70 (3-Leads) (http://www.vishay.com/doc?71153) SC-70 (6-Leads) (http://www.vishay.com/doc?71154) Front of Board SC70-3 Back of Board, SC70-3 and SC70-6 Front of Board SC70-6 ChipFETr ChipFETr vishay.com FIGURE 2. Document Number: 71236 12-Dec-03 www.vishay.com 1 AN813 Vishay Siliconix THERMAL PERFORMANCE Junction-to-Foot Thermal Resistance (the Package Performance) SC-70 (6-PIN) Thermal performance for the 3-pin SC-70 measured as junction-to-foot thermal resistance is 285_C/W typical, 340_C/W maximum. Junction-to-foot thermal resistance for the 6-pin SC70-6 is 105_C/W typical, 130_C/W maximum — a nearly two-thirds reduction compared with the 3-pin device. The “foot” is the drain lead of the device as it connects with the body. This improved performance is obtained by the increase in drain leads from one to four on the 6-pin SC-70. Note that these numbers are somewhat higher than other LITTLE FOOT devices due to the limited thermal performance of the Alloy 42 lead-frame compared with a standard copper lead-frame. The typical RθJAfor the single 3-pin SC-70 is 360_C/W steady state, compared with 180_C/W for the 6-pin SC-70. Maximum ratings are 430_C/W for the 3-pin device versus 220_C/W for the 6-pin device. All figures are based on the 1-inch square FR4 test board.The following table shows how the thermal resistance impacts power dissipation for the two different pin-outs at two different ambient temperatures. TJ(max) * TA PD + Rq JA o o PD + 150 Co* 25 C 180 CńW Room Ambient 25 _C Elevated Ambient 60 _C TJ(max) * TA PD + Rq JA TJ(max) * TA Rq JA o o PD + 150 Co* 25 C 360 CńW o o PD + 150 Co* 60 C 360 CńW PD + 347 mW PD + 250 mW PD + 694 mW PD + 500 mW To aid comparison further, Figures 3 and 4 illustrate single-channel SC-70 thermal performance on two different board sizes and two different pad patterns. The results display the thermal performance out to steady state and produce a graphic account of the thermal performance variation between the two packages. The measured steady state values of RθJA for the single 3-pin and 6-pin SC-70 are as follows: LITTLE FOOT SC-70 Thermal Resistance (C/W) 320 3-pin 6-pin 160 80 329.7_C/W 360_C/W 211.8_C/W 3-pin 6-pin 160 80 1” Square FR4 PCB 0 10-3 10-2 10-1 1 10 100 1000 10-5 10-4 Comparison of SC70-3 and SC70-6 on EVB 10-3 10-2 10-1 1 10 100 1000 Time (Secs) Time (Secs) 2 410.31_C/W 240 0.5 in x 0.6 in EVB 0 www.vishay.com 6-Pin The results show that designers can reduce thermal resistance RθJA on the order of 20% simply by using the 6-pin device rather than the 3-pin device. In this example, a 80_C/W reduction was achieved without an increase in board area. If increasing board size is an option, a further 118_C/W reduction could be obtained by utilizing a 1-inch square PCB area. 320 240 3-Pin 2) Industry standard 1” square PCB with maximum copper both sides. 400 FIGURE 3. Rq JA NOTE: Although they are intended for low-power applications, devices in the 6-pin SC-70 will handle power dissipation in excess of 0.5 W. 400 10-5 10-4 TJ(max) * TA o o PD + 150 Co* 60 C 180 CńW 1) Minimum recommended pad pattern (see Figure 4) on the EVB. SC-70 (3-PIN) Thermal Resistance (C/W) PD + Elevated Ambient 60 _C Testing Junction-to-Ambient Thermal Resistance (dependent on PCB size) PD + Room Ambient 25 _C FIGURE 4. Comparison of SC70-3 and SC70-6 on 1” Square FR4 PCB Document Number: 71236 12-Dec-03 Application Note 826 Vishay Siliconix 0.045 (1.143) (0.648) 0.022 (0.559) 0.026 0.025 (0.622) (2.438) 0.096 RECOMMENDED MINIMUM PADS FOR SC-70: 3-Lead 0.027 (0.686) 0.071 (1.803) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE Document Number: 72601 Revision: 21-Jan-08 www.vishay.com 17 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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ALL RIGHTS RESERVED Revision: 01-Jan-2022 1 Document Number: 91000