SI3552DV-T1-GE3

Si3552DV www.vishay.com Vishay Siliconix N- and P-Channel 30 V (D-S) MOSFET FEATURES TSOP-6 Dual D1 6 S1 5 • TrenchFET® power MOSFET D2 4 • 100 % Rg tested • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 Available 3 G2 2 S2 1 G1 Top View S2 D1 G2 PRODUCT SUMMARY G1 N-CHANNEL VDS (V) P-CHANNEL 30 -30 RDS(on) () at VGS = ± 10 V 0.105 0.200 RDS(on) () at VGS = ± 4.5 V 0.175 0.360 Qg typ. (nC) 2.1 2.4 ID (A) a 2.5 Configuration D2 S1 -1.8 P-Channel MOSFET N-Channel MOSFET N- and p-pair ORDERING INFORMATION Package TSOP-6 Lead (Pb)-free Si3552DV-T1-E3 Lead (Pb)-free and halogen-free Si3552DV-T1-GE3 ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) PARAMETER SYMBOL N-CHANNEL P-CHANNEL Drain-source voltage VDS 30 -30 Gate-source voltage VGS ± 20 ± 20 Continuous drain current (TJ = 150 °C) a, b TA = 25 °C TA = 70 °C Pulsed drain current Continuous source current (diode conduction) a, b maximum power dissipation a, b TA = 25 °C TA = 70 °C Operating junction and storage temperature range 2.5 -1.8 2 -1.2 IDM 8 -7 IS 1.05 ID V A -1.05 1.15 PD W 0.73 TJ, Tstg UNIT -55 to +150 °C THERMAL RESISTANCE RATINGS PARAMETER Maximum junction-to-ambient a Maximum junction-to-lead SYMBOL t5s Steady state Steady state RthJA RthJL TYPICAL MAXIMUM 93 110 130 150 75 90 UNIT °C/W Notes a. Surface mounted on FR4 board b. t  5 s S09-2110-Rev. C, 12-Oct-09 Document Number: 70971 1 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si3552DV www.vishay.com Vishay Siliconix SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Gate threshold voltage Gate-body leakage Zero gate voltage drain current On-state drain current a Drain-source on-state resistance a VGS(th) Diode forward voltage a VSD - - -1 - - N-Ch - - ± 100 P-Ch - - ± 100 VDS = 24 V, VGS = 0 V N-Ch - - 1 P-Ch - - -1 VDS = 24 V, VGS = 0 V, TJ = 55 °C N-Ch - - 5 VDS = -24 V, VGS = 0 V, TJ = 55 °C P-Ch - - -5 VDS = 5 V, VGS = 10 V N-Ch 5 - - VDS = -5 V, VGS = -10 V P-Ch -5 - - RDS(on) gfs 1 P-Ch VDS = -24 V, VGS = 0 V ID(on) Forward transconductance a N-Ch VDS = 0 V, VGS = ± 20 V IGSS IDSS VDS = VGS, ID = 250 μA VDS = VGS, ID = -250 μA VGS = 10 V, ID = 2.5 A N-Ch - 0.085 0.105 VGS = -10 V, ID = -1.8 A P-Ch - 0.165 0.200 VGS = 4.5 V, ID = 2 A N-Ch - 0.140 0.175 VGS = -4.5 V, ID = -1.2 A P-Ch - 0.298 0.360 VDS = 10 V, ID = 2.5 A N-Ch - 4.3 - VDS = -15 V, ID = -1.8 A P-Ch - 2.4 - IS = 1.05 A, VGS = 0 V N-Ch - 0.81 1.1 IS = -1.05 A, VGS = 0 V P-Ch - -0.83 -1.1 N-Ch - 2.1 3.2 V nA μA A  S V Dynamic b Total gate charge Gate-source charge Gate-drain charge Gate resistance Turn-on delay time Rise time Turn-off delay time Qg N-Channel VDS = 15 V, VGS = 5 V, ID = 1.8 A Qgs Qgd P-Channel VDS = -15 V, VGS = -5 V, ID = -1.8 A Rg td(on) tr td(off) Fall time tf Source-drain reverse recovery time trr P-Ch - 2.4 3.6 N-Ch - 0.7 - P-Ch - 0.9 - N-Ch - 0.7 - P-Ch - 0.8 - N-Ch 0.5 - 2.4 P-Ch 3 - 11 N-Ch - 7 11 P-Ch - 8 12 N-Ch - 9 14 P-Ch - 12 18 N-Ch - 13 20 P-Ch - 12 18 N-Ch - 5 8 P-Ch - 7 11 IF = 1.05 A, di/dt = 100 A/μs N-Ch - 35 60 IF = -1.05 A, di/dt = 100 A/μs P-Ch - 30 60 N-Channel VDD = 15 V, RL = 15  ID  1 A, VGEN = 10 V, Rg = 6  P-Channel VDD = -15 V, RL = 15  ID  -1 A, VGEN = -10 V, Rg = 6  nC  ns Notes a. Pulse test; pulse width  300 μs, duty cycle  2 % b. Guaranteed by design, not subject to production testing    Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S09-2110-Rev. C, 12-Oct-09 Document Number: 70971 2 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si3552DV www.vishay.com Vishay Siliconix N-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 10 10 TC = - 55 °C VGS = 10 V thru 5 V 6 I D - Drain Current (A) I D - Drain Current (A) 25 °C 8 8 4V 4 2 125 °C 6 4 2 3V 2V 0 0 0 1 2 3 4 5 0 1 0.25 4 5 6 300 250 C - Capacitance (pF) 0.20 VGS = 4.5 V 0.15 VGS = 10 V 0.10 0.05 Ciss 200 150 100 Coss 50 0.00 Crss 0 0 1 2 3 4 5 ID - Drain Current (A) 6 7 0 5 10 15 20 25 VDS - Drain-to-Source Voltage (V) 30 Capacitance On-Resistance vs. Drain Current 1.8 R DS(on) - On-Resistance (Normalized) 10 VGS - Gate-to-Source Voltage (V) 3 Transfer Characteristics Output Characteristics R DS(on) - On-Resistance () 2 VGS - Gate-to-Source Voltage (V) VDS - Drain-to-Source Voltage (V) VDS = 15 V ID = 1.8 A 8 6 4 2 0 0 1 2 3 Qg - Total Gate Charge (nC) Gate Charge S09-2110-Rev. C, 12-Oct-09 4 1.6 VGS = 10 V ID = 2.5 A 1.4 1.2 1.0 0.8 0.6 0.4 - 50 - 25 0 25 50 75 100 125 150 TJ - Junction Temperature (°C) On-Resistance vs. Junction Temperature Document Number: 70971 3 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si3552DV www.vishay.com Vishay Siliconix N-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 0.40 10 R DS(on) - On-Resistance () I S - Source Current (A) ID = 2 A TJ = 150 °C 1 TJ = 25 °C 0.32 ID = 2.5 A 0.24 0.16 0.08 0.00 0.1 0 0.2 0.4 0.6 0.8 1.0 VSD - Source-to-Drain Voltage (V) 1.2 0 2 4 6 8 10 VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage 0.4 8 ID = 250 µA 0.2 0.0 Power (W) V GS(th) Variance (V) 6 - 0.2 4 - 0.4 2 - 0.6 - 0.8 - 50 0 - 25 0 25 50 75 100 TJ - Temperature (°C) Threshold Voltage S09-2110-Rev. C, 12-Oct-09 125 150 0.01 0.1 1 10 30 Time (s) Single Pulse Power (Junction-to-Ambient) Document Number: 70971 4 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si3552DV www.vishay.com Vishay Siliconix N-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 Notes: 0.2 PDM 0.1 0.1 t1 0.05 t2 1. Duty Cycle, D = t1 t2 2. Per Unit Base = RthJA = 130 °C/W 0.02 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted Single Pulse 0.01 10 -4 10 -3 10 -2 10 -1 1 100 10 600 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10 -4 10 -3 10 -2 10 -1 Square Wave Pulse Duration (s) 1 10 Normalized Thermal Transient Impedance, Junction-to-Foot S09-2110-Rev. C, 12-Oct-09 Document Number: 70971 5 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si3552DV www.vishay.com Vishay Siliconix P-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 10 8 VGS = 10 V thru 7 V 6V TC = - 55 °C 8 I D - Drain Current (A) I D - Drain Current (A) 6 5V 6 4 4V 25 °C 125 °C 4 2 2 2V 3V 0 0 1 2 3 0 45 0 1 VDS - Drain-to-Source Voltage (V) 6 Transfer Characteristics Output Characteristics 300 0.6 0.5 240 C - Capacitance (pF) R DS(on) - On-Resistance () 2 3 4 5 VGS - Gate-to-Source Voltage (V) 0.4 VGS = 4.5 V 0.3 VGS = 10 V 0.2 Ciss 180 120 Coss 60 0.1 Crss 0 0.0 0 ID - Drain Current (A) 6 12 18 24 VDS - Drain-to-Source Voltage (V) On-Resistance vs. Drain Current Capacitance 1 2 3 4 5 6 0 7 1.8 VDS = 15 V ID = 1.8 A R DS(on) - On-Resistance (Normalized) V GS - Gate-to-Source Voltage (V) 10 30 8 6 4 2 0 0 1 2 3 4 Qg - Total Gate Charge (nC) Gate Charge S09-2110-Rev. C, 12-Oct-09 5 VGS = 10 V ID = 1.8 A 1.6 1.4 1.2 1.0 0.8 0.6 0.4 - 50 - 25 0 5 50 75 100 TJ - Junction Temperature (°C) 125 150 On-Resistance vs. Junction Temperature Document Number: 70971 6 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si3552DV www.vishay.com Vishay Siliconix P-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 0.6 10 ID = 1.8 A R DS(on) - On-Resistance () I S - Source Current (A) 0.5 TJ = 150 °C 1 TJ = 25 °C ID = 1 A 0.4 0.3 0.2 0.1 0.1 0.0 0 0.3 0.6 0.9 1.2 1.5 0 VSD - Source-to-Drain Voltage (V) 4 6 8 10 VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage 0.6 8 0.4 6 0.2 Power (W) V GS(th) Variance (V) 2 ID = 250 µA 0.0 4 2 - 0.2 - 0.4 - 50 - 25 0 25 50 75 TJ - Temperature (°C) Threshold Voltage S09-2110-Rev. C, 12-Oct-09 100 125 150 0 0.01 0.1 1 10 30 Time (s) Single Pulse Power (Junction-to-Ambient) Document Number: 70971 7 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si3552DV www.vishay.com Vishay Siliconix P-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 Notes: 0.2 PDM 0.1 0.1 t1 0.05 t2 1. Duty Cycle, D = t1 t2 2. Per Unit Base = RthJA = 130 °C/W 0.02 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted Single Pulse 0.01 10 -4 10 -3 10 -2 10 -1 1 100 10 600 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10 -4 10 -3 10 -2 10 -1 Square Wave Pulse Duration (s) 1 10 Normalized Thermal Transient Impedance, Junction-to-Foot                       Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see www.vishay.com/ppg?70971. S09-2110-Rev. C, 12-Oct-09 Document Number: 70971 8 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TSOP: 5/6−LEAD JEDEC Part Number: MO-193C e1 e1 5 4 6 E1 1 2 5 4 E E1 1 3 2 3 -B- e b E -B- e 0.15 M C B A 5-LEAD TSOP b 0.15 M C B A 6-LEAD TSOP 4x 1 -A- D 0.17 Ref c R R A2 A L2 Gauge Plane Seating Plane Seating Plane 0.08 C L A1 -C- (L1) 4x 1 MILLIMETERS Dim A A1 A2 b c D E E1 e e1 L L1 L2 R Min Nom Max Min Nom Max 0.91 - 1.10 0.036 - 0.043 0.01 - 0.10 0.0004 - 0.004 0.90 - 1.00 0.035 0.038 0.039 0.30 0.32 0.45 0.012 0.013 0.018 0.10 0.15 0.20 0.004 0.006 0.008 2.95 3.05 3.10 0.116 0.120 0.122 2.70 2.85 2.98 0.106 0.112 0.117 1.55 1.65 1.70 0.061 0.065 0.067 0.95 BSC 0.0374 BSC 1.80 1.90 2.00 0.071 0.075 0.079 0.32 - 0.50 0.012 - 0.020 0.60 Ref 0.024 Ref 0.25 BSC 0.010 BSC 0.10 - - 0.004 - - 0 4 8 0 4 8 7 Nom 1 ECN: C-06593-Rev. I, 18-Dec-06 DWG: 5540 Document Number: 71200 18-Dec-06 INCHES 7 Nom www.vishay.com 1 AN823 Vishay Siliconix Mounting LITTLE FOOTR TSOP-6 Power MOSFETs Surface mounted power MOSFET packaging has been based on integrated circuit and small signal packages. Those packages have been modified to provide the improvements in heat transfer required by power MOSFETs. Leadframe materials and design, molding compounds, and die attach materials have been changed. What has remained the same is the footprint of the packages. The basis of the pad design for surface mounted power MOSFET is the basic footprint for the package. For the TSOP-6 package outline drawing see http://www.vishay.com/doc?71200 and see http://www.vishay.com/doc?72610 for the minimum pad footprint. In converting the footprint to the pad set for a power MOSFET, you must remember that not only do you want to make electrical connection to the package, but you must made thermal connection and provide a means to draw heat from the package, and move it away from the package. In the case of the TSOP-6 package, the electrical connections are very simple. Pins 1, 2, 5, and 6 are the drain of the MOSFET and are connected together. For a small signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. Since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. The total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board. Since surface mounted packages are small, and reflow soldering is the most common form of soldering for surface mount components, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.020 inches. The use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. REFLOW SOLDERING Vishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a test preconditioning and are then reliability-tested using temperature cycle, bias humidity, HAST, or pressure pot. The solder reflow temperature profile used, and the temperatures and time duration, are shown in Figures 2 and 3. Figure 1 shows the copper spreading recommended footprint for the TSOP-6 package. This pattern shows the starting point for utilizing the board area available for the heat spreading copper. To create this pattern, a plane of copper overlays the basic pattern on pins 1,2,5, and 6. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. Notice that the planar copper is shaped like a “T” to move heat away from the drain leads in all directions. This pattern uses all the available area underneath the body for this purpose. 0.167 4.25 0.074 1.875 0.014 0.35 0.122 3.1 0.026 0.65 0.049 1.25 0.049 1.25 0.010 0.25 FIGURE 1. Recommended Copper Spreading Footprint Document Number: 71743 27-Feb-04 Ramp-Up Rate +6_C/Second Maximum Temperature @ 155 " 15_C 120 Seconds Maximum Temperature Above 180_C 70 − 180 Seconds Maximum Temperature 240 +5/−0_C Time at Maximum Temperature 20 − 40 Seconds Ramp-Down Rate +6_C/Second Maximum FIGURE 2. Solder Reflow Temperature Profile www.vishay.com 1 AN823 Vishay Siliconix 10 s (max) 255 − 260_C 1X4_C/s (max) 3-6_C/s (max) 217_C 140 − 170_C 60 s (max) 60-120 s (min) Pre-Heating Zone 3_C/s (max) Reflow Zone Maximum peak temperature at 240_C is allowed. FIGURE 3. Solder Reflow Temperature and Time Durations THERMAL PERFORMANCE TABLE 1. Equivalent Steady State Performance—TSOP-6 Thermal Resistance Rqjf 30_C/W On-Resistance vs. Junction Temperature 1.6 VGS = 4.5 V ID = 6.1 A 1.4 rDS(on) − On-Resiistance (Normalized) A basic measure of a device’s thermal performance is the junction-to-case thermal resistance, Rqjc, or the junction-to-foot thermal resistance, Rqjf. This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table 1 shows the thermal performance of the TSOP-6. 1.2 1.0 0.8 0.6 −50 SYSTEM AND ELECTRICAL IMPACT OF TSOP-6 −25 0 25 50 75 100 125 150 TJ − Junction Temperature (_C) FIGURE 4. Si3434DV In any design, one must take into account the change in MOSFET rDS(on) with temperature (Figure 4). www.vishay.com 2 Document Number: 71743 27-Feb-04 PAD Pattern www.vishay.com Vishay Siliconix Recommended Land Pattern For TSOP-5L / TSOP-6L 5 1 2 4 6 5 4 3 1 2 3 TSOP 5L TSOP 6L 0.036 [0.922] 0.136 [3.444] 0.064 [1.626] 0.095 [2.408] 0.037 [0.950] 0.020 [0.508] 0.017 [0.442] Note • All dimensions are in inches (millimeter) ECN: C22-0860-Rev. B, 24-Oct-2022 DWG: 3010 Revision: 24-Oct-2022 Document Number: 72610 1 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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