Si5448DU
www.vishay.com
Vishay Siliconix
N-Channel 40 V (D-S) MOSFET
FEATURES
PowerPAK®
ChipFET®
• TrenchFET® Gen IV power MOSFET
Single
D
D
D 7 8
S 6
5
9
1.
m
m
1
m
0m
3.
S
9
Top View
• 100 % Rg and UIS tested
• Thermally enhanced PowerPAK ChipFET package
-Compact footprint area - less than 6.09 mm2
-Thin 0.8 mm profile
1
2
3 D D
4 D
G
Bottom View
• 56 % lower RDS(ON) than the prior generation
• Material categorization:
for definitions of compliance
www.vishay.com/doc?99912
APPLICATIONS
PRODUCT SUMMARY
VDS (V)
RDS(on) max. () at VGS = 10 V
RDS(on) max. () at VGS = 4.5 V
Qg typ. (nC)
ID (A) a, g
Configuration
please
40
0.00775
0.00947
12.6
25
Single
see
D
• DC/DC converters
• Motor drive control
G
• Synchronous rectification
• Battery management
• Load switch
N-Channel MOSFET
S
ORDERING INFORMATION
Package
Lead (Pb)-free and halogen-free
PowerPAK ChipFET
Si5448DU-T1-GE3
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER
Drain-source voltage
Gate-source voltage
Continuous drain current (TJ = 150 °C)
SYMBOL
VDS
VGS
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
Pulsed drain current (t = 100 μs)
ID
IDM
Continuous source-drain diode current
TC = 25 °C
TA = 25 °C
IS
Single pulse avalanche current
Single pulse avalanche energy
L = 0.1 mH
IAS
EAS
TC = 25 °C
TC = 70 °C
Maximum power dissipation
TA = 25 °C
TA = 70 °C
Operating junction and storage temperature range
Soldering recommendations (peak temperature) d, e
PD
TJ, Tstg
LIMIT
40
+20 / -16
25 a
25 a
15.9 b, c
12.7 b, c
100
25 a
2.6 b, c
15
11.25
31
20
3.1 b, c
2 b, c
-55 to +150
260
UNIT
V
A
mJ
W
°C
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYPICAL
MAXIMUM
UNIT
t 10 s
RthJA
34
40
Maximum junction-to-ambient b, f
°C/W
4
4
Maximum junction-to-case (drain)
Steady state
RthJC
Notes
a. Package limited.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. See solder profile (www.vishay.com/doc?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed
and is not required to ensure adequate bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under steady state conditions is 90 °C/W.
g. TC = 25 °C.
S16-2343-Rev. A, 14-Nov-16
Document Number: 76149
1
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si5448DU
www.vishay.com
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS
VGS = 0 V, ID = 250 μA
40
-
-
V
-
21.2
-
-
-5.1
-
Static
Drain-source breakdown voltage
VDS temperature coefficient
VDS/TJ
VGS(th) temperature coefficient
VGS(th)/TJ
Gate-source threshold voltage
ID = 250 μA
mV/°C
VGS(th)
VDS = VGS, ID = 250 μA
1
-
2.5
V
Gate-source leakage
IGSS
VDS = 0 V, VGS = +20 V / -16 V
-
-
± 100
nA
Zero gate voltage drain current
IDSS
On-state drain current a
ID(on)
Drain-source on-state resistance a
Forward transconductance a
RDS(on)
gfs
VDS = 40 V, VGS = 0 V
-
-
1
VDS = 40 V, VGS = 0 V, TJ = 70 °C
-
-
10
VDS 10 V, VGS = 10 V
20
-
-
A
VGS = 10 V, ID = 15 A
-
0.00646
0.00775
VGS = 4.5 V, ID = 10 A
-
0.00790
0.00947
VDS = 10 V, ID = 15 A
-
80
-
-
1765
-
-
278
-
-
45
-
-
26.2
40
μA
S
Dynamic b
Input capacitance
Ciss
Output capacitance
Coss
Reverse transfer capacitance
Crss
Total gate charge
Qg
Gate-source charge
Qgs
Gate-drain charge
Qgd
Gate resistance
Rg
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Turn-on delay time
Rise time
Turn-off delay time
Fall time
VDS = 20 V, VGS = 0 V, f = 1 MHz
VDS = 20 V, VGS = 10 V, ID = 15 A
-
12.6
20
VDS = 20 V, VGS = 4.5 V, ID = 15 A
-
5.1
-
-
2.5
-
f = 1 MHz
0.3
1.5
3
-
10
20
-
35
53
-
15
30
tf
-
10
20
td(on)
-
15
30
-
60
90
-
18
36
-
33
50
td(on)
tr
td(off)
tr
td(off)
VDD = 20 V, RL = 1.7 , ID 12 A,
VGEN = 10 V, Rg = 1
VDD = 20 V, RL = 1.7 , ID 12 A,
VGEN = 4.5 V, Rg = 1
tf
pF
nC
ns
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
IS
Pulse diode forward current
ISM
Body diode voltage
VSD
TC = 25 °C
IS = 13 A, VGS = 0 V
-
-
25
-
-
100
-
0.8
1.2
A
V
Body diode reverse recovery time
trr
-
33
50
ns
Body diode reverse recovery charge
Qrr
-
30
45
nC
Reverse recovery fall time
ta
-
18
-
Reverse recovery rise time
tb
-
15
-
IF = 13 A, dI/dt = 100 A/μs, TJ = 25 °C
ns
Notes
a. Pulse test; pulse width 300 μs, duty cycle 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S16-2343-Rev. A, 14-Nov-16
Document Number: 76149
2
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si5448DU
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Axis Title
Axis Title
100
100
10000
10000
VGS = 10 V thru 4 V
VGS = 3 V
40
100
1000
60
1st line
2nd line
1000
60
2nd line
ID - Drain Current (A)
80
1st line
2nd line
2nd line
ID - Drain Current (A)
80
TC = 25 °C
40
100
20
20
TC = 125 °C
0
0
1
2
3
4
TC = -55 °C
0
10
5
10
0
1
2
3
4
VDS - Drain-to-Source Voltage (V)
2nd line
VGS - Gate-to-Source Voltage (V)
2nd line
Output Characteristics
Transfer Characteristics
Axis Title
5
Axis Title
0.015
2100
10000
10000
0.006
VGS = 10 V
100
0.003
1000
1260
1st line
2nd line
1000
VGS = 4.5 V
0.009
2nd line
C - Capacitance (pF)
1680
1st line
2nd line
2nd line
RDS(on) - On-Resistance (Ω)
Ciss
0.012
840
Coss
100
420
Crss
0
0
10
20
40
60
80
100
10
0
5
10
20
ID - Drain Current (A)
2nd line
VDS - Drain-to-Source Voltage (V)
2nd line
On-Resistance vs. Drain Current and Gate Voltage
Capacitance
Axis Title
Axis Title
10
1.7
VDS = 20 V
ID = 16 A
8
1000
VDS = 10 V
6
VDS = 32 V
4
100
2
0
10
0
7
14
21
28
2nd line
RDS(on) - On-Resistance (Normalized)
10000
1st line
2nd line
2nd line
VGS - Gate-to-Source Voltage (V)
15
10000
VGS = 10 V, ID = 15 A
1.5
1000
1.3
VGS = 4.5 V, 10 A
1.1
100
0.9
0.7
10
-50
-25
0
25
50
75
100 125 150
Qg - Total Gate Charge (nC)
2nd line
TJ - Junction Temperature (°C)
2nd line
Gate Charge
On-Resistance vs. Junction Temperature
S16-2343-Rev. A, 14-Nov-16
1st line
2nd line
0
Document Number: 76149
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si5448DU
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Axis Title
Axis Title
10000
2nd line
RDS(on) - On-Resistance (Ω)
TJ = 150 °C
1000
1st line
2nd line
2nd line
IS - Source Current (A)
10
1
TJ = 25 °C
0.1
100
0.01
0.001
0.025
0.2
0.4
0.6
0.8
1.0
1000
0.020
0.015
TJ = 150 °C
0.010
0.005
100
TJ = 25 °C
0
10
0
10000
0.030
1st line
2nd line
100
1.2
10
0
2
4
6
8
10
VSD - Source-to-Drain Voltage (V)
2nd line
VGS - Gate-to-Source Voltage (V)
2nd line
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
Axis Title
10000
2.0
50
40
Power (W)
1000
1st line
2nd line
2nd line
VGS(th) (V)
ID = 250 μA
1.7
1.4
30
20
100
1.1
10
0.8
0
0.001 0.01
10
-50
-25
0
25
50
75
100 125 150
0.1
1
10
100
1000
TJ - Temperature (°C)
2nd line
Time (s)
Threshold Voltage
Single Pulse Power, Junction-to-Ambient
Axis Title
1000
10000
IDM limited
100 μs
1000
10
1st line
2nd line
2nd line
ID - Drain Current (A)
100
Limited by RDS(on) (1)
1 ms
10 ms
1
100 ms
0.1
100
10 s, 1 s
BVDSS limited
TA = 25 °C
Single pulse
DC
0.01
10
0.1
(1)
1
10
100
VDS - Drain-to-Source Voltage (V)
VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient
S16-2343-Rev. A, 14-Nov-16
Document Number: 76149
4
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si5448DU
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Axis Title
10000
45
1000
30
1st line
2nd line
2nd line
ID - Drain Current (A)
60
Package limited
100
15
0
10
0
25
50
75
100
125
150
TC - Case Temperature (°C)
2nd line
Current Derating a
Axis Title
Axis Title
10000
40
10000
1.8
30
1.35
1st line
2nd line
20
2nd line
Power (W)
1000
1st line
2nd line
2nd line
Power (W)
1000
0.9
100
10
100
0.45
0
10
0
25
50
75
100
125
150
0
10
0
25
50
75
100
125
TC - Case Temperature (°C)
2nd line
TA - Ambient Temperature (°C)
2nd line
Power, Junction-to-Case
Power, Junction-to-Ambient
150
Note
a. The power dissipation PD is based on TJ max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the
package limit.
S16-2343-Rev. A, 14-Nov-16
Document Number: 76149
5
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si5448DU
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
Notes:
0.1
0.1
PDM
0.05
t1
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = RthJA = 90 °C/W
0.02
3. TJM - TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10-4
10-3
10-2
10-1
1
Square Wave Pulse Duration (s)
10
100
1000
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
0.1
10-4
Single Pulse
10-3
10-2
Square Wave Pulse Duration (s)
10-1
1
Normalized Thermal Transient Impedance, Junction-to-Case
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?76149.
S16-2343-Rev. A, 14-Nov-16
Document Number: 76149
6
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
PowerPAK® ChipFET® Case Outline
D
(7)
(6)
(5)
(1)
(2)
(3)
(4)
E
(8)
Pin #1
indicator
Side view of single
e
b
H
D1
D(2)
D2
K
D(3)
L
G(4)
K1
D2
SI(1)
GI(2)
S2(3)
D1(8)
D1(7)
D2(6)
Detail Z
G2(4)
K2
L
D(1)
A1
C
A
Z
Side view of dual
E1
E2
E3
H
D3
D(8)
D(7)
D(6)
S(5)
K3
Backside view of dual pad
Backside view of single pad
DIM.
D2(5)
MILLIMETERS
INCHES
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A
0.70
0.75
0.85
0.028
0.030
0.033
A1
0
-
0.05
0
-
0.002
b
0.25
0.30
0.35
0.010
0.012
0.014
C
0.15
0.20
0.25
0.006
0.008
0.010
D
2.92
3.00
3.08
0.115
0.118
0.121
D1
1.75
1.87
2.00
0.069
0.074
0.079
D2
1.07
1.20
1.32
0.042
0.047
0.052
D3
0.20
0.25
0.30
0.008
0.010
0.012
E
1.82
1.90
1.98
0.072
0.075
0.078
E1
1.38
1.50
1.63
0.054
0.059
0.064
E2
0.92
1.05
1.17
0.036
0.041
0.046
E3
0.45
0.50
0.55
0.018
0.020
0.022
e
0.65 BSC
0.026 BSC
H
0.15
0.20
0.25
0.006
0.008
0.010
K
0.25
-
-
0.010
-
-
K1
0.30
-
-
0.012
-
-
K2
0.20
-
-
0.008
-
-
K3
0.20
-
-
0.008
-
-
L
0.30
0.35
0.40
0.012
0.014
0.016
C14-0630-Rev. E, 21-Jul-14
DWG: 5940
Note
• Millimeters will govern
Document Number: 73203
1
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Revision: 21-Jul-14
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR PowerPAK® ChipFET® Single
0.225
(0.009)
0.350
(0.014)
0.650
(0.026)
0.200
(0.008)
0.300
(0.012)
0.300
(0.012)
0.100
(0.004)
1.500
(0.059)
1.900
(0.075)
0.250
(0.010)
0.500
(0.020)
0.350
(0.014)
0.350
(0.014)
1.870
(0.074)
0.305
(0.012)
2.575
(0.101)
Recommended Minimum Pads
Dimensions in mm/(Inches)
Return to Index
APPLICATION NOTE
Document Number: 69948
Revision: 21-Jan-08
www.vishay.com
9
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Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
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Statements regarding the suitability of products for certain types of applications are based on Vishay's knowledge of typical
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about the suitability of products for a particular application. It is the customer's responsibility to validate that a particular product
with the properties described in the product specification is suitable for use in a particular application. Parameters provided in
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parameters, including typical parameters, must be validated for each customer application by the customer's technical experts.
Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited
to the warranty expressed therein.
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Revision: 01-Jan-2022
1
Document Number: 91000
