SI5457DC-T1-GE3

Si5457DC www.vishay.com Vishay Siliconix P-Channel 20 V (D-S) MOSFET FEATURES 1206-8 ChipFET® Single D D 8 D 7 S 6 5 1. 9 m m 1 3.0 mm Top View • TrenchFET® power MOSFET • 100 % Rg tested • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 1 2 D 3 D 4 D G APPLICATIONS Bottom View • Portable devices - Load switch - Charger switch - Battery switch - DC/DC converter Marking code: BT PRODUCT SUMMARY VDS (V) -20 RDS(on) max. () at VGS = -4.5 V 0.036 RDS(on) max. () at VGS = -3.6 V 0.041 RDS(on) max. () at VGS = -2.5 V 0.056 Qg typ. (nC) 12.5 ID (A) a Configuration S G D P-Channel MOSFET -6 Single ORDERING INFORMATION Package Lead (Pb)-free and halogen-free 1206-8 ChipFET Si5457DC-T1-GE3 ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) PARAMETER Drain-source voltage Gate-source voltage Continuous drain current (TJ = 150 °C) TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C Pulsed drain current Continuous source-drain diode current Maximum power dissipation SYMBOL LIMIT VDS VGS -20 ± 12 -6 a -6 a -6 a, b, c -5.2 b, c -20 -4.8 -1.9 b, c 5.7 3 2.3 b, c 1.2 b, c -55 to +150 260 ID IDM TC = 25 °C TA = 25 °C TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C Operating junction and storage temperature range Soldering recommendations (peak temperature) d, e IS PD TJ, Tstg UNIT V A W °C THERMAL RESISTANCE RATINGS PARAMETER Maximum junction-to-ambient b, f Maximum junction-to-foot (drain) t5s Steady state SYMBOL TYPICAL MAXIMUM UNIT RthJA RthJF 45 18 55 22 °C/W Notes a. Package limited b. Surface mounted on 1" x 1" FR4 board c. t = 5 s d. See solder profile (www.vishay.com/doc?73257). The 1206-8 ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components f. Maximum under steady state conditions is 95 °C/W S10-2011-Rev. A, 06-Sep-10 Document Number: 67013 1 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5457DC www.vishay.com Vishay Siliconix SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0 V, ID = -250 μA -20 - - V - -14 - - 3.2 - Static Drain-source breakdown voltage VDS temperature coefficient VDS/TJ VGS(th) temperature coefficient VGS(th)/TJ Gate-source threshold voltage ID = -250 μA mV/°C VGS(th) VDS = VGS, ID = -250 μA -0.6 - -1.4 V Gate-source leakage IGSS VDS = 0 V, VGS = ± 12 V - - ± 100 nA Zero gate voltage drain current IDSS On-state drain current a Drain-source on-state resistance a Forward transconductance a VDS = -20 V, VGS = 0 V - - -1 VDS = -20 V, VGS = 0 V, TJ = 85 °C - - -5 ID(on) VDS  -5 V, VGS = -4.5 V -20 - - VGS = -4.5 V, ID = -4.9 A - 0.030 0.036 RDS(on) VGS = -3.6 V, ID = -4.6 A - 0.034 0.041 VGS = -2.5 V, ID = -2 A - 0.046 0.056 VDS = -10 V, ID = -4.9 A - 16 - - 1000 - - 225 - - 195 - - 25 38 - 12.5 19 VDS = -10 V, VGS = -4.5 V, ID = -6.5 A - 2 - - 4 - f = 1 MHz 0.9 4.6 9.2 - 25 50 - 20 40 - 30 60 gfs μA A  S Dynamic b Input capacitance Ciss Output capacitance Coss Reverse transfer capacitance Crss Total gate charge Qg Gate-source charge Qgs Gate-drain charge Qgd Gate resistance Rg Turn-on delay time Rise time Turn-off delay time Fall time Turn-on delay time Rise time Turn-off delay time Fall time VDS = -10 V, VGS = 0 V, f = 1 MHz VDS = -10 V, VGS = -10 V, ID = -6.5 A td(on) tr td(off) VDD = -10 V, RL = 1.9  ID  -5.2 A, VGEN = -4.5 V, Rg = 1  tf - 12 25 td(on) - 10 20 - 10 20 - 27 55 - 12 25 tr td(off) VDD = -10 V, RL = -1.9  ID  -5.2 A, VGEN = -10 V, Rg = 1  tf pF nC  ns Drain-Source Body Diode Characteristics Continuous source-drain diode current IS Pulse diode forward current ISM Body diode voltage VSD Body diode reverse recovery time trr Body diode reverse recovery charge Qrr Reverse recovery fall time ta Reverse recovery rise time tb TC = 25 °C IS = -5.2 A, VGS = 0 V IF = -5.2 A, di/dt = 100 A/μs, TJ = 25 °C - - -6 - - -20 - -0.8 -1.2 V - 20 40 ns - 10 20 nC - 10 - - 10 - A ns Notes a. Pulse test; pulse width  300 μs, duty cycle  2% b. Guaranteed by design, not subject to production testing  Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S10-2011-Rev. A, 06-Sep-10 Document Number: 67013 2 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5457DC www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 5 20 V GS = 5 V thru 3 V V GS = 2.5 V 4 ID - Drain Current (A) ID - Drain Current (A) 16 12 V GS = 2 V 8 3 2 T C = 25 °C 1 4 T C = 125 °C V GS = 1.5 V T C = - 55 °C 0 0 0 0.5 1.0 1.5 2.0 2.5 0 3.0 0.5 1.0 1.5 VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics 0.08 2.0 1800 V GS = 2.5 V C - Capacitance (pF) RDS(on) - On-Resistance (Ω) 1500 0.06 0.04 V GS = 3.6 V V GS = 4.5 V 0.02 1200 Ciss 900 600 Coss Crss 300 0 0 0 4 8 12 16 20 0 3 9 VDS - Drain-to-Source Voltage (V) On Resistance vs. Drain Current Capacitance 10 12 1.6 ID = 6.5 A V GS = 4.5 V; 3.6 V; I D = 4.9 A 8 V DS = 10 V 6 V DS = 5 V V DS = 16 V 4 2 (Normalized) 1.4 RDS(on) - On-Resistance VGS - Gate-to-Source Voltage (V) 6 ID - Drain Current (A) 1.2 V GS = 2.5 V; I D = 2 A 1.0 0.8 0 0 5 10 15 20 Qg - Total Gate Charge (nC) Gate Charge S10-2011-Rev. A, 06-Sep-10 25 30 0.6 - 50 - 25 0 25 50 75 100 125 150 TJ - Junction Temperature (°C) On-Resistance vs. Junction Temperature Document Number: 67013 3 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5457DC www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 0.12 100 ID = 4.9 A RDS(on) - On-Resistance (Ω) IS - Source Current (A) 0.10 T J = 150 °C 10 T J = 25 °C 1 0.08 0.06 T J = 125 °C 0.04 T J = 25 °C 0.02 0 0.1 0 0.2 0.4 0.6 0.8 1.0 1.2 0 1 VSD - Source-to-Drain Voltage (V) 2 3 4 5 VGS - Gate-to-Source Voltage (V) Forward Diode Voltage vs. Temperature On-Resistance vs. Gate-to-Source Voltage 1.2 50 1.1 40 1.0 Power (W) VGS(th) (V) ID = 250 μA 0.9 0.8 30 20 0.7 10 0.6 0.5 - 50 - 25 0 25 50 75 100 125 0 10-3 150 10-2 10-1 1 10 TJ - Temperature (°C) Time (s) Threshold Voltage Single Pulse Power 100 600 100 Limited by RDS(on) * ID - Drain Current (A) 10 1 ms 1 10 ms 100 ms 1s 10 s DC 0.1 TA = 25 °C Single Pulse 0.01 0.1 BVDSS Limited 1 10 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Safe Operating Area, Junction-to-Ambient S10-2011-Rev. A, 06-Sep-10 Document Number: 67013 4 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5457DC www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 6 12 5 4 Power (W) ID - Drain Current (A) 9 Package Limited 6 3 2 3 1 0 0 0 25 50 75 100 TC - Case Temperature (°C) Current Derating a 125 150 25 50 75 100 125 150 TC - Case Temperature (°C) Power Derating Note a. The power dissipation PD is based on TJ max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit S10-2011-Rev. A, 06-Sep-10 Document Number: 67013 5 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5457DC www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 Notes: 0.1 PDM 0.1 0.05 t1 t2 1. Duty Cycle, D = t1 t2 2. Per Unit Base = R thJA = 95 °C/W 0.02 3. T JM - TA = PDMZthJA(t) Single Pulse 4. Surface Mounted 0.01 10-4 10-3 10-2 10-1 1 10 100 600 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10-1 1 10 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Foot                      Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for silicon technology and package reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see www.vishay.com/ppg?67013. S10-2011-Rev. A, 06-Sep-10 Document Number: 67013 6 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix 1206-8 ChipFETR 4 L D 8 7 6 5 4 1 S 2 e 3 E1 5 6 7 8 4 3 2 1 E 4 b x c Backside View 2X 0.10/0.13 R C1 A DETAIL X NOTES: 1. All dimensions are in millimeaters. 2. Mold gate burrs shall not exceed 0.13 mm per side. 3. Leadframe to molded body offset is horizontal and vertical shall not exceed 0.08 mm. 4. Dimensions exclusive of mold gate burrs. 5. No mold flash allowed on the top and bottom lead surface. MILLIMETERS Dim A b c c1 D E E1 e L S INCHES Min Nom Max Min Nom Max 1.00 − 1.10 0.039 − 0.043 0.25 0.30 0.35 0.010 0.012 0.014 0.1 0.15 0.20 0.004 0.006 0.008 0 − 0.038 0 − 0.0015 2.95 3.05 3.10 0.116 0.120 0.122 1.825 1.90 1.975 0.072 0.075 0.078 1.55 1.65 1.70 0.061 0.065 0.067 0.65 BSC 0.28 − 0.0256 BSC 0.42 0.011 − 0.55 BSC 0.022 BSC 5_Nom 5_Nom 0.017 ECN: C-03528—Rev. F, 19-Jan-04 DWG: 5547 Document Number: 71151 15-Jan-04 www.vishay.com 1 AN811 Vishay Siliconix Single-Channel 1206-8 ChipFETr Power MOSFET Recommended Pad Pattern and Thermal Performance INTRODUCTION New Vishay Siliconix ChipFETs in the leadless 1206-8 package feature the same outline as popular 1206-8 resistors and capacitors but provide all the performance of true power semiconductor devices. The 1206-8 ChipFET has the same footprint as the body of the LITTLE FOOTR TSOP-6, and can be thought of as a leadless TSOP-6 for purposes of visualizing board area, but its thermal performance bears comparison with the much larger SO-8. 80 mil 68 mil This technical note discusses the single-channel ChipFET 1206-8 pin-out, package outline, pad patterns, evaluation board layout, and thermal performance. 28 mil 26 mil PIN-OUT Figure 1 shows the pin-out description and Pin 1 identification for the single-channel 1206-8 ChipFET device. The pin-out is similar to the TSOP-6 configuration, with two additional drain pins to enhance power dissipation and thermal performance. The legs of the device are very short, again helping to reduce the thermal path to the external heatsink/pcb and allowing a larger die to be fitted in the device if necessary. Single 1206-8 ChipFET 1 D D D D The pad pattern with copper spreading shown in Figure 2 improves the thermal area of the drain connections (pins 1,2,3,6.7,8) while remaining within the confines of the basic footprint. The drain copper area is 0.0054 sq. in. or 3.51 sq. mm). This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. An example of this method is implemented on the Vishay Siliconix Evaluation Board described in the next section (Figure 3). D D G S Bottom View FIGURE 1. For package dimensions see the 1206-8 ChipFET package outline drawing (http://www.vishay.com/doc?71151). BASIC PAD PATTERNS The basic pad layout with dimensions is shown in Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/doc?72286). This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. Document Number: 71126 12-Dec-03 FIGURE 2. Footprint With Copper Spreading THE VISHAY SILICONIX EVALUATION BOARD FOR THE SINGLE 1206-8 The ChipFET 1206-08 evaluation board measures 0.6 in by 0.5 in. Its copper pad pattern consists of an increased pad area around the six drain leads on the top-side—approximately 0.0482 sq. in. 31.1 sq. mm—and vias added through to the underside of the board, again with a maximized copper pad area of approximately the board-size dimensions. The outer package outline is for the 8-pin DIP, which will allow test sockets to be used to assist in testing. The thermal performance of the 1206-8 on this board has been measured with the results following on the next page. The testing included comparison with the minimum recommended footprint on the evaluation board-size pcb and the industry standard one-inch square FR4 pcb with copper on both sides of the board. www.vishay.com 1 AN811 Vishay Siliconix Front of Board Back of Board ChipFETr vishay.com FIGURE 3. Junction-to-Foot Thermal Resistance (the Package Performance) Thermal performance for the 1206-8 ChipFET measured as junction-to-foot thermal resistance is 15_C/W typical, 20_C/W maximum for the single device. The “foot” is the drain lead of the device as it connects with the body. This is identical to the SO-8 package RQjf performance, a feat made possible by shortening the leads to the point where they become only a small part of the total footprint area. Junction-to-Ambient Thermal Resistance (dependent on pcb size) The typical RQja for the single-channel 1206-8 ChipFET is 80_C/W steady state, compared with 68_C/W for the SO-8. Maximum ratings are 95_C/W for the 1206-8 versus 80_C/W for the SO-8. The results show that a major reduction can be made in the thermal resistance by increasing the copper drain area. In this example, a 45_C/W reduction was achieved without having to increase the size of the board. If increasing board size is an option, a further 33_C/W reduction was obtained by maximizing the copper from the drain on the larger 1” square pcb. 160 Thermal Resistance (C/W) THERMAL PERFORMANCE 120 Single EVB Min. Footprint 80 1” Square PCB 40 Testing To aid comparison further, Figure 4 illustrates ChipFET 1206-8 thermal performance on two different board sizes and three different pad patterns. The results display the thermal performance out to steady state and produce a graphic account of how an increased copper pad area for the drain connections can enhance thermal performance. The measured steady state values of RQja for the single 1206-8 ChipFET are : 1) Minimum recommended pad pattern (see Figure 2) on the evaluation board size of 0.5 in x 0.6 in. 156_C/W 2) The evaluation board with the pad pattern described on Figure 3. 111_C/W 3) Industry standard 1” square pcb with maximum copper both sides. 78_C/W www.vishay.com 2 0 10-5 10-4 10-3 10-2 10-1 1 10 100 1000 Time (Secs) FIGURE 4. Single 1206−8 ChipFET SUMMARY The thermal results for the single-channel 1206-8 ChipFET package display similar power dissipation performance to the SO-8 with a footprint reduction of 80%. Careful design of the package has allowed for this performance to be achieved. The short leads allow the die size to be maximized and thermal resistance to be reduced within the confines of the TSOP-6 body size. ASSOCIATED DOCUMENT 1206-8 ChipFET Dual Thermal performance, AN812 (http://www.vishay.com/doc?71127). Document Number: 71126 12-Dec-03 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR 1206-8 ChipFET® 0.093 0.026 0.016 0.010 (0.650) (0.406) (0.244) 0.036 (0.914) 0.022 (0.559) (2.032) 0.080 (2.357) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index APPLICATION NOTE Return to Index www.vishay.com 2 Document Number: 72593 Revision: 21-Jan-08 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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ALL RIGHTS RESERVED Revision: 01-Jan-2022 1 Document Number: 91000