SI5922DU-T1-GE3

Si5922DU www.vishay.com Vishay Siliconix Dual N-Channel 30 V (D-S) MOSFET FEATURES PowerPAK® ChipFET® Dual • TrenchFET® power MOSFET D1 D1 8 D2 7 D2 6 5 9 1. m 1 m 3.0 mm Top View • 100 % Rg and UIS tested 1 2 S 1 3 4 S G1 2 G2 Bottom View Marking code: CH • DC/DC power supply 30 RDS(on) max. (Ω) at VGS = 10 V 0.0192 RDS(on) max. (Ω) at VGS = 6 V 0.0220 RDS(on) max. (Ω) at VGS = 4.5 V 0.0245 Qg typ. (nC) ID (A) a Configuration • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 APPLICATIONS PRODUCT SUMMARY VDS (V) • New thermally enhanced PowerPAK® ChipFET® package - Small footprint area - Low on-resistance - Thin 0.8 mm profile D1 4.7 G1 6 D2 G2 Dual N-Channel MOSFET N-Channel MOSFET S1 S2 ORDERING INFORMATION Package PowerPAK ChipFET Lead (Pb)-free and halogen-free Si5922DU-T1-GE3 ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-source voltage VDS 30 Gate-source voltage VGS +20 / -16 Continuous drain current (TJ = 150 °C) TA = 25 °C ID Continuous source-drain diode current Single pulse avalanche current Avalanche energy IDM TC = 25 °C TA = 25 °C L = 0.1 mH IS IAS EAS TC = 25 °C Maximum power dissipation TC = 70 °C TA = 25 °C TA = 70 °C 6a 6 a, b, c 6 a, b, c TA = 70 °C Pulsed drain current (t = 100 μs) V 6a TC = 25 °C TC = 70 °C UNIT 24 A 6a 1.9 b, c 10 5 mJ 10.4 PD 6.7 2.3 b, c W 1.5 b, c Operating junction and storage temperature range TJ, Tstg -55 to +150 °C 260 Soldering recommendations (peak temperature) d, e Notes a. Package limited b. Surface mounted on 1" x 1" FR4 board c. t = 5 s d. See solder profile (www.vishay.com/doc?73257). The PowerPAK ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components S22-0374-Rev. B, 25-Apr-2022 Document Number: 76056 1 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5922DU www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER Maximum junction-to-ambient a, b Maximum junction-to-case (drain) t≤5s Steady state SYMBOL RthJA RthJC TYPICAL 43 9.5 MAXIMUM 55 12 UNIT °C/W Notes a. Surface mounted on 1" x 1" FR4 board b. Maximum under steady state conditions is 105 °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER Static Drain-source breakdown voltage VDS temperature coefficient VGS(th) temperature coefficient Gate-source threshold voltage Gate-source leakage SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS ΔVDS/TJ ΔVGS(th)/TJ VGS(th) IGSS VGS = 0 V, ID = 250 μA 30 1.2 5 - 14.3 -4.7 0.0155 0.0170 0.0190 22 2.2 ± 100 1 10 0.0192 0.0220 0.0245 - V 1.3 - 765 225 14 0.018 10 4.7 2.2 0.65 6.5 6.3 6 25 15 10 17 45 16 27 0.036 15 7.1 12.6 15 50 30 20 35 90 30 50 - 0.81 21 10 12 9 6 24 1.2 40 20 - Zero gate voltage drain current IDSS On-state drain current a ID(on) Drain-source on-state resistance a Forward transconductance a Dynamic b Input capacitance Output capacitance Reverse transfer capacitance Crss/Ciss ratio Total gate charge Gate-source charge Gate-drain charge Output charge Gate resistance Turn-on delay time Rise time Turn-off delay time Fall time Turn-on delay time Rise time Turn-off delay time Fall time Drain-Source Body Diode Characteristics Continuous source-drain diode current Pulse diode forward current (t = 100 μs) Body diode voltage Body diode reverse recovery time Body diode reverse recovery charge Reverse recovery fall time Reverse recovery rise time ID = 250 μA VDS = VGS, ID = 250 μA VDS = 0 V, VGS = +20 V / -16 V VDS = 30 V, VGS = 0 V. VDS = 30 V, VGS = 0 V, TJ = 55 °C VDS ≥ 5 V, VGS = 10 V VGS = 10 V, ID = 5 A VGS = 6 V, ID = 4 A VGS = 4.5 V, ID = 4 A VDS = 10 V, ID = 5 A RDS(on) gfs Ciss Coss Crss VDS = 15 V, VGS = 0 V, f = 1 MHz VDS = 15 V, VGS = 10 V, ID = 5 A Qg Qgs Qgd Qoss Rg td(on) tr td(off) tf td(on) tr td(off) tf VDS = 15 V, VGS = 4.5 V, ID = 5 A IS ISM VSD trr Qrr ta tb TC = 25 °C VDS = 15 V, VGS = 0 V f = 1 MHz VDD = 15 V, RL = 3 Ω, ID ≅ 5 A, VGEN = 10 V, Rg = 1 Ω VDD = 15 V, RL = 3 Ω, ID ≅ 5 A, VGEN = 4.5 V, Rg = 1 Ω IS = 5 A, VGS = 0 V IF = 5 A, dI/dt = 100 A/μs, TJ = 25 °C mV/°C V nA μA A Ω S pF - nC Ω ns A V ns nC ns Notes a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 % b. Guaranteed by design, not subject to production testing Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S22-0374-Rev. B, 25-Apr-2022 Document Number: 76056 2 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5922DU www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Axis Title Axis Title 25 25 10000 10000 VGS = 10 V thru 4 V 10 100 5 1000 15 1st line 2nd line 1000 VGS = 3 V 15 2nd line ID - Drain Current (A) 20 1st line 2nd line 2nd line ID - Drain Current (A) 20 TC = 25 °C 10 100 5 TC = 125 °C 0 0 0.5 1 1.5 2 2.5 TC = -55 °C 0 10 3 10 0 1 2 3 VDS - Drain-to-Source Voltage (V) 2nd line VGS - Gate-to-Source Voltage (V) 2nd line Output Characteristics Transfer Characteristics Axis Title 4 Axis Title 10000 0.030 10000 900 0.020 100 0.015 VGS = 10 V 1000 600 1st line 2nd line 1000 VGS = 6 V VGS = 4.5 V 2nd line C - Capacitance (pF) 750 0.025 1st line 2nd line 2nd line RDS(on) - On-Resistance (Ω) Ciss Coss 450 300 100 150 Crss 0.010 0 10 5 10 15 20 25 10 0 5 10 ID - Drain Current (A) 2nd line VDS - Drain-to-Source Voltage (V) 2nd line On-Resistance vs. Drain Current and Gate Voltage Capacitance 1.5 VDS = 15 V 8 1000 1st line 2nd line VDS = 7.5 V 6 VDS = 24 V 4 100 2 0 10 0 3 6 9 12 2nd line RDS(on) - On-Resistance (Normalized) 10000 ID = 5 A 20 Axis Title Axis Title 10 2nd line VGS - Gate-to-Source Voltage (V) 15 10000 ID = 5 A 1.4 VGS = 10 V; 6 V 1.3 1000 1.2 VGS = 4.5 V 1.1 1.0 100 0.9 0.8 0.7 10 -50 -25 0 25 50 75 100 125 150 Qg - Total Gate Charge (nC) 2nd line TJ - Junction Temperature (°C) 2nd line Gate Charge On-Resistance vs. Junction Temperature S22-0374-Rev. B, 25-Apr-2022 1st line 2nd line 0 Document Number: 76056 3 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5922DU www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Axis Title Axis Title 10000 1 100 0.1 0.03 0.2 0.4 0.6 0.8 1.0 TJ = 150 °C 0.02 100 TJ = 25 °C 0.01 10 0 1000 0.04 1st line 2nd line 1000 TJ = 25 °C ID = 5 A 0.05 2nd line RDS(on) - On-Resistance (Ω) TJ = 150 °C 10 10000 0.06 1st line 2nd line 2nd line IS - Source Current (A) 100 0 0 1.2 2 4 6 8 10 10 VSD - Source-to-Drain Voltage (V) 2nd line VGS - Gate-to-Source Voltage (V) 2nd line Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage Axis Title 1.8 30 10000 1.7 25 1.5 1000 20 Power (W) 1.4 1st line 2nd line 2nd line VGS(th) (V) 1.6 1.3 1.2 100 ID = 250 μA 1.1 15 10 1.0 5 0.9 0.8 10 -50 -25 0 25 50 75 0 0.001 0.01 100 125 150 0.1 TJ - Temperature (°C) 2nd line Threshold Voltage 1 Time (s) 10 100 1000 Single Pulse Power, Junction-to-Ambient Axis Title 10000 100 10 100 μs 1 1000 1st line 2nd line 2nd line ID - Drain Current (A) Limited by RDS(on) (1) 1 ms 10 ms 100 ms 1s 10 s DC 0.1 TA = 25 °C Single pulse 0.01 100 10 0.1 (1) 1 10 100 VDS - Drain-to-Source Voltage (V) VGS > minimum VGS at which RDS(on) is specified Safe Operating Area S22-0374-Rev. B, 25-Apr-2022 Document Number: 76056 4 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5922DU www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Axis Title 25 12 10000 10 10 100 Package limited 5 Power Dissipation (W) 1000 15 1st line 2nd line 2nd line ID - Drain Current (A) 20 8 6 4 2 0 10 0 25 50 75 100 125 150 0 25 50 75 100 125 TC - Case Temperature (°C) 2nd line TC - Case Temperature (°C) Current Derating a Power Derating 150 Note a. The power dissipation PD is based on TJ (max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit S22-0374-Rev. B, 25-Apr-2022 Document Number: 76056 5 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5922DU www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 Notes: 0.1 PDM t1 0.05 t2 t 1. Duty Cycle, D = t1 2 2. Per Unit Base = R thJA = 105 °C/W 0.02 3. TJM - TA = PDM Z thJA(t) 4. Surface Mounted Single Pulse 0.01 10-4 10-3 10-2 10-1 1 10 100 1000 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.05 0.1 Single Pulse 0.01 10-4 0.02 10-3 10-2 10-1 1 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Case Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?76056. S22-0374-Rev. B, 25-Apr-2022 Document Number: 76056 6 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix PowerPAK® ChipFET® Case Outline D (7) (6) (5) (1) (2) (3) (4) E (8) Pin #1 indicator Side view of single e b H D1 D(2) D2 K D(3) L G(4) K1 D2 SI(1) GI(2) S2(3) D1(8) D1(7) D2(6) Detail Z G2(4) K2 L D(1) A1 C A Z Side view of dual E1 E2 E3 H D3 D(8) D(7) D(6) S(5) K3 Backside view of dual pad Backside view of single pad DIM. D2(5) MILLIMETERS INCHES MIN. NOM. MAX. MIN. NOM. MAX. A 0.70 0.75 0.85 0.028 0.030 0.033 A1 0 - 0.05 0 - 0.002 b 0.25 0.30 0.35 0.010 0.012 0.014 C 0.15 0.20 0.25 0.006 0.008 0.010 D 2.92 3.00 3.08 0.115 0.118 0.121 D1 1.75 1.87 2.00 0.069 0.074 0.079 D2 1.07 1.20 1.32 0.042 0.047 0.052 D3 0.20 0.25 0.30 0.008 0.010 0.012 E 1.82 1.90 1.98 0.072 0.075 0.078 E1 1.38 1.50 1.63 0.054 0.059 0.064 E2 0.92 1.05 1.17 0.036 0.041 0.046 E3 0.45 0.50 0.55 0.018 0.020 0.022 e 0.65 BSC 0.026 BSC H 0.15 0.20 0.25 0.006 0.008 0.010 K 0.25 - - 0.010 - - K1 0.30 - - 0.012 - - K2 0.20 - - 0.008 - - K3 0.20 - - 0.008 - - L 0.30 0.35 0.40 0.012 0.014 0.016 C14-0630-Rev. E, 21-Jul-14 DWG: 5940 Note • Millimeters will govern Document Number: 73203 1 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Revision: 21-Jul-14 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR PowerPAK® ChipFET® Single 0.225 (0.009) 0.350 (0.014) 0.650 (0.026) 0.200 (0.008) 0.300 (0.012) 0.300 (0.012) 0.100 (0.004) 1.500 (0.059) 1.900 (0.075) 0.250 (0.010) 0.500 (0.020) 0.350 (0.014) 0.350 (0.014) 1.870 (0.074) 0.305 (0.012) 2.575 (0.101) Recommended Minimum Pads Dimensions in mm/(Inches) Return to Index APPLICATION NOTE Document Number: 69948 Revision: 21-Jan-08 www.vishay.com 9 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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