SI5948DU-T1-GE3

Si5948DU www.vishay.com Vishay Siliconix Dual N-Channel 40 V (D-S) MOSFET FEATURES PRODUCT SUMMARY VDS (V) RDS(on) () MAX. 0.082 at VGS = 10 V 0.094 at VGS = 4.5 V 40 ID (A) 6a 6a Qg (TYP.) 2.2 nC PowerPAK® ChipFET® Dual D1 D1 8 D2 7 D2 6 5 9 1. m m 1 3.0 mm Top View • TrenchFET® power MOSFET • 100 % Rg and UIS tested • New thermally enhanced PowerPAK® ChipFET® package - Small footprint area - Low on-resistance - Thin 0.8 mm profile • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 APPLICATIONS • DC/DC power supply 1 2 3 G S1 1 4 S 2 G2 Bottom View D1 D2 G1 G2 Marking Code: CG Ordering Information: Si5948DU-T1-GE3 (lead (Pb)-free and halogen-free) N-Channel MOSFET N-Channel MOSFET S1 S2 ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current (TJ = 150 °C) SYMBOL VDS VGS TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C Pulsed Drain Current (t = 100 μs) ID IDM Continuous Source-Drain Diode Current TC = 25 °C TA = 25 °C IS Single Pulse Avalanche Current Avalanche Energy L = 0.1 mH IAS EAS Maximum Power Dissipation TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C PD Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) d, e TJ, Tstg LIMIT 40 ± 20 6a 5.5 3.7 b, c 2.9 b, c 10 5.8 1.7 b, c 6 1.8 7 4.4 2 b, c 1.3 b, c -55 to +150 260 UNIT V A mJ W °C THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambient b, f Maximum Junction-to-Case (Drain) t5s Steady State SYMBOL RthJA RthJC TYPICAL 52 15 MAXIMUM 62 18 UNIT °C/W Notes a. Package limited. b. Surface mounted on 1" x 1" FR4 board. c. t = 5 s. d. See solder profile (www.vishay.com/ppg?73257). The PowerPAK ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under steady state conditions is 105 °C/W. S16-1127-Rev. A, 06-Jun-16 Document Number: 76424 1 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5948DU www.vishay.com Vishay Siliconix SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0 V, ID = 250 μA 40 - - V - 45.3 - - -4.1 - 1 - 2.5 V nA Static Drain-Source Breakdown Voltage VDS/TJ VDS Temperature Coefficient ID = 250 μA mV/°C VGS(th) Temperature Coefficient VGS(th)/TJ Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA IGSS VDS = 0 V, VGS = ± 20 V - - ± 100 VDS = 40 V, VGS = 0 V - - -1 VDS = 40 V, VGS = 0 V, TJ = 55 °C - - -10 VDS  5 V, VGS = 10 V 5 - - A VGS = 10 V, ID = 5 A - 0.065 0.082 VGS = 4.5 V, ID = 3 A - 0.074 0.094  VDS = 20 V, ID = 5 A - 11 - - 165 - - 30 - - 13 - - 3.3 5 - 1.7 2.6 VDS = 20 V, VGS = 4.5 V, ID = 10 A - 0.53 - - 0.63 - f = 1 MHz 1.3 6.5 13 - 5 10 VDD = 20 V, RL = 4  ID  5 A, VGEN = 10 V, Rg = 1  - 25 50 Gate-Source Leakage Zero Gate Voltage Drain Current IDSS On-State Drain Current a ID(on) Drain-Source On-State Resistance a Forward Transconductance a RDS(on) gfs μA S Dynamic b Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Gate Resistance Rg Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time VDS = 20 V, VGS = 0 V, f = 1 MHz VDS = 20 V, VGS = 10 V, ID = 10 A td(on) tr td(off) - 7 15 tf - 10 20 td(on) - 11 20 VDD = 20 V, RL = 4  ID  5 A, VGEN = 4.5 V, Rg = 1  tr td(off) tf - 41 80 - 9 20 - 25 50 pF nC  ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulse Diode Forward Current (t = 100 μs) ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Reverse Recovery Fall Time ta Reverse Recovery Rise Time tb TC = 25 °C IS = 5 A, VGS = 0 V IF = 5 A, dI/dt = 100 A/μs, TJ = 25 °C - - 5.8 - - 10 - 0.9 1.2 V - 15 30 ns - 8 15 nC - 9 - - 6 - A ns Notes a. Pulse test; pulse width  300 μs, duty cycle  2 %. b. Guaranteed by design, not subject to production testing.   Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S16-1127-Rev. A, 06-Jun-16 Document Number: 76424 2 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5948DU www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 20 10 VGS = 10 V thru 4 V 16 ID - Drain Current (A) ID - Drain Current (A) 8 6 4 VGS = 3 V 2 12 TC = 25 °C 8 TC = 125 °C 4 TC = - 55 °C 0 0.0 0.5 1.0 1.5 0 2.0 0.0 0.5 1.0 VDS - Drain-to-Source Voltage (V) 2.0 2.5 3.0 3.5 4.0 Transfer Characteristics Output Characteristics 0.1200 250 0.1000 200 Ciss C - Capacitance (pF) RDS(on) - On-Resistance (Ω) 1.5 VGS - Gate-to-Source Voltage (V) VGS = 4.5 V 0.0800 0.0600 VGS = 10 V 150 100 Coss 0.0400 50 Crss 0.0200 0 0 2 4 6 8 10 0 10 15 20 25 VDS - Drain-to-Source Voltage (V) On-Resistance vs. Drain Current and Gate Voltage Capacitance 10 30 1.8 VDS = 10 V ID = 10 A 8 RDS(on) - On-Resistance (Normalized) VGS - Gate-to-Source Voltage (V) 5 ID - Drain Current (A) VDS = 20 V 6 VDS = 32 V 4 2 0 0.0 1.0 2.0 3.0 4.0 VGS = 10 V ID = 5 A 1.6 1.4 VGS = 4.5 V 1.2 1.0 0.8 0.6 - 50 - 25 0 25 50 75 100 125 150 Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C) Gate Charge On-Resistance vs. Junction Temperature S16-1127-Rev. A, 06-Jun-16 Document Number: 76424 3 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5948DU www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 0.200 100 ID = 5 A 10 RDS(on) - On-Resistance (Ω) IS - Source Current (A) 0.160 TJ = 150 °C TJ = 25 °C 1 0.1 0.120 TJ = 125 °C 0.080 TJ = 25 °C 0.040 0.000 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 2 4 6 8 10 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage 2.0 30 25 1.8 1.4 Power (W) VGS(th) (V) 20 1.6 ID = 250 μA 15 10 1.2 5 1.0 - 50 - 25 0 25 50 75 100 125 0 0.0001 0.001 150 0.01 0.1 1 10 100 1000 TJ - Temperature (°C) Time (s) Threshold Voltage Single Pulse Power, Junction-to-Ambient 100 Limited by RDS(on)* IDM limited ID - Drain Current (A) 10 ID limited 100 μs 1 1 ms 10 ms 100 ms 10 s 1s 0.1 TA = 25 °C BVDSS limited DC 0.01 0.1 1 10 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Safe Operating Area S16-1127-Rev. A, 06-Jun-16 Document Number: 76424 4 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5948DU www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 8 10 8 Power Dissipation (W) ID - Drain Current (A) 6 Package Limited 4 2 6 4 2 0 0 0 25 50 75 100 125 150 0 25 50 75 100 TC - Case Temperature (°C) TC - Case Temperature (°C) Current Derating a Power Derating 125 150 Note a. The power dissipation PD is based on TJ (max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. S16-1127-Rev. A, 06-Jun-16 Document Number: 76424 5 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5948DU www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 0.0001 0.001 0.01 0.1 1 10 100 1000 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient Normalized N ormalliz izzed Effective Efff ffe ffe ective Transient Trransient T Thermal Thermal IImpedance Th mpedance Duty y Cycle Cyycle = 0.5 0.2 0 .2 2 0.1 0 .1 0.05 0 .05 0.02 0 .0 02 Single S ing ngle P Pulse ulsse e 0.1 0.0001 0.001 0.01 0.01 0.1 Square Wave Puls Pulse se Duration Duration (s) Normalized Thermal Transient Impedance, Junction-to-Case                       Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?76424. S16-1127-Rev. A, 06-Jun-16 Document Number: 76424 6 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix PowerPAK® ChipFET® Case Outline D (7) (6) (5) (1) (2) (3) (4) E (8) Pin #1 indicator Side view of single e b H D1 D(2) D2 K D(3) L G(4) K1 D2 SI(1) GI(2) S2(3) D1(8) D1(7) D2(6) Detail Z G2(4) K2 L D(1) A1 C A Z Side view of dual E1 E2 E3 H D3 D(8) D(7) D(6) S(5) K3 Backside view of dual pad Backside view of single pad DIM. D2(5) MILLIMETERS INCHES MIN. NOM. MAX. MIN. NOM. MAX. A 0.70 0.75 0.85 0.028 0.030 0.033 A1 0 - 0.05 0 - 0.002 b 0.25 0.30 0.35 0.010 0.012 0.014 C 0.15 0.20 0.25 0.006 0.008 0.010 D 2.92 3.00 3.08 0.115 0.118 0.121 D1 1.75 1.87 2.00 0.069 0.074 0.079 D2 1.07 1.20 1.32 0.042 0.047 0.052 D3 0.20 0.25 0.30 0.008 0.010 0.012 E 1.82 1.90 1.98 0.072 0.075 0.078 E1 1.38 1.50 1.63 0.054 0.059 0.064 E2 0.92 1.05 1.17 0.036 0.041 0.046 E3 0.45 0.50 0.55 0.018 0.020 0.022 e 0.65 BSC 0.026 BSC H 0.15 0.20 0.25 0.006 0.008 0.010 K 0.25 - - 0.010 - - K1 0.30 - - 0.012 - - K2 0.20 - - 0.008 - - K3 0.20 - - 0.008 - - L 0.30 0.35 0.40 0.012 0.014 0.016 C14-0630-Rev. E, 21-Jul-14 DWG: 5940 Note • Millimeters will govern Document Number: 73203 1 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Revision: 21-Jul-14 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR PowerPAK® ChipFET® Dual 2.700 (0.106) 0.300 (0.012) 0.350 (0.014) 0.650 (0.026) 1.900 (0.075) 0.300 (0.012) 1.050 (0.041) 0.350 (0.014) 0.200 (0.008) 0.300 (0.012) 0.225 (0.009) 0.650 (0.026) 1.175 (0.046) 1.525 (0.060) Recommended Minimum Pads Dimensions in mm/(Inches) APPLICATION NOTE Note: This is Flipped Mirror Image Pin #1 Location is Top Left Corner Return to Index www.vishay.com 10 Document Number: 69949 Revision: 21-Jan-08 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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