SI9122DQ-T1-E3

Product is End of Life 12/2014 Si9122 Vishay Siliconix 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers DESCRIPTION FEATURES Si9122 is a dedicated half-bridge IC ideally suited to fixed telecom applications where efficiency is required at low output voltages (e.g. < 3.3 V). Designed to operate within the fixed telecom voltage range of 33 to 72 V, the IC is capable of controlling and driving both the low and high-side switching devices of a half bridge circuit and also controlling the switching devices on the secondary side of the bridge. Due to the very low on-resistance of the secondary MOSFETs, a significant increase in the efficiency can be achieved as compared with conventional Schottky diodes. Control of the secondary devices is by means of a pulse transformer and a pair of inverters. Such a system has efficiencies well in excess of 90 % even for low output voltages. On-chip control of the dead time delays between the primary and secondary synchronous signals keep efficiencies high and prevent accidental destruction of the power transformer. An external resistor sets the switching frequency from 200 kHz to 625 kHz. • 12 V to 72 V input voltage range • Integrated half-bridge primary drivers (1 A drive capability) RoHS COMPLIANT • Secondary synchronous signals with programmable deadtime delay • Voltage mode control • Voltage feedforward compensation • High voltage pre-regulator operates during start-up • Current sensing on low-side primary device • Frequency foldback eliminates constant current tail • Advanced maximum current control during start-up and shorted load • Low input voltage detection • Programmable soft-start function • Over temperature protections Si9122 has advanced current monitoring and control circuitry which allow the user to set the maximum current in the primary circuit. Such a feature acts as protection against output shorting and also provides constant current into large capacitive loads during start-up or when paralleling power supplies. Current sensing is by means of a sense resistor on the low-side primary device. APPLICATIONS • Network cards • Power supply modules FUNCTIONAL BLOCK DIAGRAM VCC REG_COMP VIN 12 V to 72 V BST Synchronous Rectifiers DH LX Si9122 1 V to 12 V Typ. + VOUT - DL CS2 VIN_DET CS1 SRH CL_CONT VCC PGND GND B BM ROSC VREF SS SRL Error Amplifier + - EP VREF Opto Isolator Figure 1. Document Number: 71815 S-80038-Rev. J, 14-Jan-08 www.vishay.com 1 Si9122 Vishay Siliconix TECHNICAL DESCRIPTION Si9122 is a voltage mode controller for the half-bridge topology. With 100 V depletion mode MOSFET capability, the Si9122 is capable of powering directly from the high voltage bus to VCC through an external PNP pass transistor, or may be powered through an external regulator directly through the VCC pin. With PWM control, Si9122 provides peak efficiency throughout the entire line and load range. In order to simplify the traditional secondary synchronous rectification, Si9122 provides intelligent gate drive signals to control the secondary MOSFETs. With independent gate drive signals from the controller, transformer design is no longer limited by the gate to a source rating of the MOSFETs. Si9122 provides constant VGS voltage, independent of line voltage to minimize the gate charge loss as well as conduction loss. A break-before-make function is included to prevent shoot through current or transformer shorting. Adjustable Break-Before-Make time is incorporated into the IC and is programmable by an external resistor value. Si9122 is packaged in TSSOP-20 and MLP65-20 packages. Both TSSOP-20 and MLP65-20 packages are available in lead (Pb)-free option. In order to satisfy the stringent ambient temperature requirements, Si9122 is rated to handle the industrial temperature range of - 40 °C to 85 °C. When a situation arises which results in a rapid increase in primary (or secondary current) such as output shorted or start-up with a large output capacitor, control of the PWM generator is handed over to the current loop. Monitoring of the load current is by means of a sense resistor on the primary lowside switch. DETAILED BLOCK DIAGRAM VIN REG_COMP VCC Pre-Regulator VREF ROSC 9.1 V + - High-Side Primary Driver VUVLO BST DH Int 8.8 V LX VINDET VREF + - VUV + - VSD Low-Side Driver VFF VCC DL OSC Ramp 132 kΩ 550 mV 60 kΩ EP + Error Amplifier + PWM Comparator V REF 20 µA SS PGND 2 CS1 SRH SYNC Driver High ISS OTP 8V CS2 VCC Driver Control and Timing VCC + - Peak DET SRL Duty Cycle Control Si9122 Over Current Protection GND CL_CONT SYNC Driver Low BBM Figure 2. www.vishay.com 2 Document Number: 71815 S-80038-Rev. J, 14-Jan-08 Si9122 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS All voltages referenced to GND = 0 V Parameter Limit VIN (Continuous) VIN (100 ms) 100 VCC 14.5 VBST Continuous 90 100 ms 115 VLX 75 VBST - VLX 15 VREF, ROSC - 0.3 to VCC + 0.3 Logic Inputs - 0.3 to VCC + 0.3 Analog Inputs - 0.3 to VCC + 0.3 HV Pre-Regulator Input Current (Continuous) 5 Storage Temperature - 65 to 150 Operating Junction Temperature Power Dissipationa Thermal Impedance (ΘJA) Unit 75 150 V mA °C TSSOP-20 MLP65-20 850 2500 mW TSSOP-20b 75 38 °C/W MLP65-20c Notes: a. Device Mounted on JEDEC compliant 1S2P test board. b. Derate - 14 mW/°C above 25 °C. c. Derate - 26 mW/°C above 25 °C. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE All voltages referenced to GND = 0 V Parameter VIN Limit Unit 12 to 72 V CVIN1 || CVIN2 100 µF/ESR ≤ 100 mΩ, 0.1 µF VCC Operating 10 to 13.2 V CVCC 4.7 µF kHz fOSC 200 to 600 ROSC 24 to 72 RBBM 22 to 50 CBBMh > 680 pF CSS 4.7 nF CREF 0.1 CBOOST 0.1 CLOAD 150 Analog Inputs 0 V to VCC - 2 V Digital Inputs 0 V to VCC Reference Voltage Output Current Document Number: 71815 S-80038-Rev. J, 14-Jan-08 0 to 2.5 kΩ µF V mA www.vishay.com 3 Si9122 Vishay Siliconix SPECIFICATIONSa Limits - 40 to 85 °C Symbol Test Conditions Unless Otherwise Specified fNOM = 500 kHz, VIN = 72 V VINDET = 7.2 V; 10 V ≤ VCC ≤ 13.2 V Min.b Typ.c Max.b Unit Output Voltage VREF VCC = 12 V, 25 °C Load = 0 mA 3.2 3.3 3.4 V Short Circuit Current ISREF VREF = 0 V - 50 mA Load Regulation dVr/dir IREF = 0 to - 2.5 mA - 30 - 75 mV Power Supply Rejection PSRR at 100 Hz 60 Parameter Reference (3.3 V) dB Oscillator Accuracy (1 % ROSC) i ROSC = 30 kΩ, fNOM = 500 kHz - 20 500 Max Frequency FMAX ROSC = 22.6 kΩ Foldback Frequencyd FFOBK fNOM = 500 kHz, VCS2 - VCS1 > 150 mV IBIAS VEP = 0 V 20 625 750 100 % kHz Error Amplifier Input Bias Current - 40 AV Gain Bandwidth BW Power Supply Rejection Slew Rate PSRR at 100 Hz SR - 15 µA - 2.2 V/V 5 MHz 60 dB 0.5 V/µs ± 150 mV Current Sense Amplifier VCS1 - GND, VCS2 - GND Input Voltage CM Range VCM Input Amplifier Gain AVOL 17.5 dB Input Amplifier Bandwidth BW 5 MHz Input Amplifier Offset Voltage VOS ±5 mV dVCS = 0 120 ICL_CONT dVCS = 100 mV 0 dVCS = 170 mV >2 Lower Current Limit Threshold VTLCL IPD = IPU - ICL_CONT = 0 See Figure 6 100 Upper Current Limit Threshold VTHCL IPD > 2 mA 150 CL_CONT Current IPU < 500 µA Hysteresis CL_CONT Clamp Level CL_CONT(min) µA mA mV - 50 IPU = 500 µA 0.6 1.5 V PWM Operation DMAX Duty Cycle e DMIN fOSC = 500 kHz VEP = 0 V 90 VEP = 1.75 V 92 95 % < 15 VCS2 - VCS1 > 150 mV 3 Pre-Regulator Input Voltage + VIN IIN = 10 µA 72 Input Leakage Current ILKG VIN = 72 V, VCC > VREG 10 IREG1 VIN = 72 V, VINDET < VSD IREG2 VIN = 72 V, VINDET > VREF Regulator Bias Current Regulator_Comp Pre-Regulator Drive Capacility www.vishay.com 4 ISOURCE ISINK ISTART VCC = 12 V VCC < VREG 86 200 8 14 - 29 - 19 -9 50 82 110 20 V µA mA µA mA Document Number: 71815 S-80038-Rev. J, 14-Jan-08 Si9122 Vishay Siliconix SPECIFICATIONSa Parameter Symbol Test Conditions Unless Otherwise Specified fNOM = 500 kHz, VIN = 72 V VINDET = 7.2 V; 10 V ≤ VCC ≤ 13.2 V Limits - 40 to 85 °C Min.b Typ.c Max.b 7.4 9.1 10.4 8.5 9.1 9.7 Unit Pre-Regulator VCC Pre-Regulator Turn Off Threshold Voltage Undervoltage Lockout VUVLO Hysteresis g VREG1 VREG2 VUVLO VINDET > VREF TA = 25 °C VINDET = 0 V VCC Rising 9.2 TA = 25 °C 7.15 8.8 9.8 8.1 8.8 9.3 VUVLOHYS V 0.5 Soft-Start Soft-Start Current Output Soft-Start Completion Voltage ISS Start-Up Condition 12 20 28 µA VSS_COMP Normal Operation 7.35 8.05 8.85 V VSD VINDET Rising 350 550 720 Shutdown VINDET Shutdown FN VINDET Hysteresis VINDET 200 mV VINDET Input Threshold Voltages VINDET - VIN Under Voltage VUV VUV Hysteresis VINDET Rising 3.13 3.3 3.46 VINDET 0.23 0.3 0.35 V Over Temperature Protection Activating Temperature TJ Increasing 160 De-Activating Temperature TJ Decreasing 130 °C Converter Supply Current (VCC) Shutdown ICC1 Shutdown, VINDET = 0 V 50 Switching Disabled ICC2 VINDET < VREF 4 8 12 Switching w/o Load ICC3 VINDET > VREF, fNOM = 500 kHz 5 10 15 ICC4 VCC = 12 V, CDH = CDL = 3 nF CSRH = CSRL = 0.3 nF Switching with CLOAD 350 µA mA 21 Output MOSFET DH Driver (High-Side) VBST - 0.3 Output High Voltage VOH Sourcing 10 mA Output Low Voltage VOL Sinking 10 mA Boost Current IBST VLX = 72 V, VBST = VLX + VCC 1.3 1.9 2.7 LX Current ILX VLX = 72 V, VBST = VLX + VCC - 1.3 - 0.7 - 0.4 - 1.0 - 0.75 Peak Output Source Peak Output Sink ISOURCE ISINK Rise Time tr Fall Time tf VCC = 10 V VLX + 0.3 0.75 1.0 35 CDL = 3 nF V mA A ns 35 Output MOSFET DL Driver (Low-Side) Output High Voltage VOH Sourcing 10 mA Output Low Voltage VOL Sinking 10 mA Peak Output Source ISOURCE Peak Output Sink ISINK Rise Time tr Fall Time tf Document Number: 71815 S-80038-Rev. J, 14-Jan-08 VCC = 10 V CDH = 3 nF VCC - 0.3 0.3 - 1.0 0.75 1.0 35 35 - 0.75 V A ns www.vishay.com 5 Si9122 Vishay Siliconix SPECIFICATIONSa Parameter Symbol Limits - 40 to 85 °C Test Conditions Unless Otherwise Specified fNOM = 500 kHz, VIN = 72 V VINDET = 7.2 V; 10 V ≤ VCC ≤ 13.2 V Min.b VCC - 0.4 Typ.c Max.b Unit Synchronous Rectifier (SRH, SRL) Drivers Output High Voltage VOH Sourcing 10 mA Output Low Voltage VOL Sinking 10 mA tBBM1 Break-Before-Make Timef tBBM2 tBBM3 tBBM4 Peak Output Source Peak Output Sink ISOURCE ISINK Rise Time tr Fall Time tf TA = 25 °C, RBBM = 33 kΩ, See Figure 3 TA = 25 °C, RBBM = 33 kΩ, LX = 72 V VCC = 10 V CSRH = CSRL = 0.3 nF 0.4 V 55 40 35 ns 55 - 100 100 35 35 mA ns Voltage Mode Error Amplifier td1DH Input to High-Side Switch Off < 200 td2DL Input to Low-Side Switch Off < 200 td3DH Input to High-Side Switch Off < 200 td4DL Input to Low-Side Switch Off < 200 ns Current Mode Current Amplifier ns Notes: a. Refer to PROCESS OPTION FLOWCHART for additional information. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (- 40 °C to 85 °C). c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. FMIN when VCL_CONT at clamp level. Typical foldback frequency change + 20 %, - 30 % over temperature. e. Measured on SRL or SRH outputs. f. See figure 3 for Break-Before-Make time definition. g. VUVLO tracks VREG1 by a diode drop. h. CBBM may be required to reduce noise into BBM pin for non-optimum layout. i. Guaranteed by design and characterization, not tested in production. www.vishay.com 6 Document Number: 71815 S-80038-Rev. J, 14-Jan-08 Si9122 Vishay Siliconix TIMING DIAGRAM FOR MOS DRIVERS VCC PWM PWM PWM PWM GND VCC DL DL SRL SRL GND VCC GND VBST DH DH VMID DH DH GND VCC SRH SRH GND Time tBBM1 tBBM2 tBBM3 DH tBBM4 BST = LX + VCC 50 % V LX LX DH, LX DH, LX VMID VCC SRH 50 % DH, LX GND tBBM3 DL tBBM4 SRL SRL VCC GND Return to: Specification Table Rectification Timing Sequence tBBM1 tBBM2 Primary MOSFET Drivers Secondary MOSFET Drivers Figure 3. Document Number: 71815 S-80038-Rev. J, 14-Jan-08 www.vishay.com 7 Si9122 Vishay Siliconix PIN CONFIGURATION Si9122DQ (TSSOP-20) Si9122DLP (MLP65-20) 20 BST 2 19 DH VIN 1 20 3 18 LX REG_COMP 2 19 DH VREF 4 17 DL VCC 3 18 LX GND 5 16 PGND VREF 4 17 DL ROSC 6 15 SRH GND 5 16 PGND ROSC 6 15 SRH EP 7 14 SRL VINDET 8 13 SS CS1 9 12 BBM CS2 10 11 CL_CONT VIN REG_COMP VCC 1 EP 7 14 SRL VINDET 8 13 SS CS1 9 12 BBM CS2 10 11 CL_CONT BST Top View Top View ORDERING INFORMATION Lead (Pb)-free Part Number Temperature Range Si9122DQ-T1-E3 Package TSSOP-20 - 40 °C to 85 °C Si9122DLP-T1-E3 Eval Kit Si9122DB Issue 3 MLP65-20 Temperature Range Board Type - 10 °C to 70 °C Surface Mount and Thru-Hole PIN DESCRIPTION Pin Number Name 1 VIN 2 REG_COMP Function Input supply voltage for the start-up circuit Control signal for an external pass transistor 3 VCC Supply voltage for internal circuitry 4 VREF 3.3 V reference, decoupled with 1 µF capacitor 5 GND Ground 6 ROSC External resistor connection to oscillator 7 EP 8 VINDET Voltage control input VIN under voltage detect and shutdown function input. Shuts down or disables switching when VINDET falls below preset threshold voltages and provides the feed forward voltage. 9 CS1 Current limit amplifier negative input 10 CS2 Current limit amplifier positive input 11 CL_CONT 12 BBM Current limit compensation Programmable break-before-make time connection to an external resistor to set time delay 13 SS Soft-start control - external capacitor connection 14 SRL Signal transformer drive, sequenced with the primary side 15 SRH 16 PGND 17 DL Low-side gate drive signal - primary 18 LX High-side source and transformer connection node 19 DH 20 BST www.vishay.com 8 Signal transformer drive, sequenced with the primary side Power ground High-side gate drive signal - primary Bootstrap voltage to drive the high-side N-Channel MOSFET switch Document Number: 71815 S-80038-Rev. J, 14-Jan-08 Si9122 Vishay Siliconix VCC VIN Pre-Regulator + - VREG Bandgap Reference 3.3 V VREF 9.1 V VUVLO + VINDET VUV 8.8 V BST 160 °C Temp Protection 550 mV VSD OSC Oscillator DH LX VUV VUVLO OTP Clock Clock High Voltage Interface VCC Logic Low-Side Driver 132 kΩ DL 60 kΩ EP + − + VREF/2 Current Control CS2 CS1 Logic PGND PWM Generator Gain Timer VCC Loop Control + 100 mV Blanking VCC CL_CONT GND VCC 8V High-Side Primary Driver VSD + - Frequency Foldback ROSC + - VREF CL_CONT Voltage Feedforward 9.1 V BBM Synchronous Driver (Low) SRL Si9122 20 µA SS Synchronous Driver (High) SRH Soft-Start SS Enable Figure 4. Detailed Functional Block DETAILED OPERATION Start-Up When VINEXT rises above 0 V, the internal pre-regulator begins to charge up the VCC capacitor. Current into the external VCC capacitor is limited to typically 40 mA by the internal DMOS device. When Vcc exceeds the UVLO voltage of 8.8 V a soft-start cycle of the switch mode supply is initiated. The VCC supply continues to be charged by the pre-regulator until VCC equals VREG. During this period, between VUVLO and VREG, excessive load current will result in VCC falling below VUVLO and stopping switch mode operation. This situation is avoided by the hysteresis between VREG and VUVLO and correct sizing of the VCC Document Number: 71815 S-80038-Rev. J, 14-Jan-08 capacitor, bootstrap capacitor and the soft-start capacitor. The value of the VCC capacitor should therefore be chosen to be capable of maintaining switch mode operation until the VCC can be supplied from the external circuit (e.g via a power transformer winding and zener regulator). Feedback from the output of the switch mode supply charges VCC above VREG and fully disconnects the pre-regulator, isolating VCC from VIN. VCC is then maintained above VREG for the duration of switch mode operation. In the event of an over voltage condition on VCC, an internal voltage clamp turns on at 14.5 V to shunt excessive current to GND. www.vishay.com 9 Si9122 Vishay Siliconix Care needs to be taken if there is a delay prior to the external circuit feeding back to the VCC supply. To prevent excessive power dissipation within the IC it is advisable to use an external PNP device. A pin has been incorporated on the IC, (REG_COMP) to provide compensation when employing the external device. In this case the VIN pin is connected to the base of the PNP device and controls the current, while the REG_COMP pin determines the frequency compensation of the circuit. The value of the REG_COMP capacitor cannot be too big, otherwise it will slow down the response of the pre-regulator in the case that fault situations occur and pre-regulator needs to be turned on again. To understand the operation please refer to Figure 5. The soft-start circuit is designed for the dc-dc converter to start-up in an orderly manner and reduce component stress on the IC. This feature is programmable by selecting an external CSS. An internal 20 µA current source charges CSS from 0 V to the final clamped voltage of 8 V. In the event of UVLO or shutdown, VSS will be held low (< 1 V) disabling driver switching. To prevent oscillations, a longer soft-start time may be needed for high capacitive loads and high peak output current applications. Reference The reference voltage of Si9122 is set at 3.3 V. The reference voltage is de-coupled externally with 0.1 µF capacitor. The VREF voltage is 0 V in shutdown mode and has 50 mA source capability. Voltage Mode PWM Operation Under normal load conditions, the IC operates in voltage mode and generates a fixed frequency pulse width modulated signal to the drivers. Duty cycle is controlled over a wide range to maintain output voltage under line and load variation. Voltage feed forward is also included to take account of variations in supply voltage VIN. In the half-bridge topology requiring isolation between output and input, the reference voltage and error amplifier must be supplied externally, usually on the secondary side. The error information is thus passed to the power controller through an opto-coupling device. This information is inverted, hence 0 V represents the maximum duty cycle, whilst 2 V represents minimum duty cycle. The error information enters the IC via pin EP, and is passed to the PWM generator via an inverting amplifier. The relationship between Duty cycle and VEP is shown in the Typical Characteristic Graph, Duty Cycle vs. VEP 25 °C , page 12. Voltage feedforward is implemented by taking the attenuated VIN signal at VINDET and directly modulating the duty cycle. The relationship between Duty cycle and VINDET is shown in the Typical Characteristic Graph, Duty Cycle vs. VINDET, page 16. At start-up, i.e., once VCC is greater than VUVLO, switching is initiated under soft-start control which increases primary switch on-times linearly from DMIN to DMAX over the soft-start period. Start-up from a VINDET power down is also initiated under soft-start control. www.vishay.com 10 Half-Bridge and Synchronous Rectification Timing Sequence The PWM signal generated within the Si9122 controls the low and high-side bridge drivers on alternative cycles. A period of inactivity always results after initiation of the softstart cycle until the soft-start voltage reaches approximately 1.2 V and PWM controlled switching begins. The first bridge driver to switch is always the low-side, DL as this allows charging of the high-side boost capacitor. The timing and coordination of the drives to the primary and secondary stages is very important and shown in Figure 3. It is essential to avoid the situation where both of the secondary MOSFETs are on when either the high or the lowside switch are active. In this situation the transformer would effectively be presented with a short across the output. To avoid this, a dedicated break-before-make circuit is included which will generate non overlapping waveforms for the primary and the secondary drive signals. This is achieved by a programmable timer which delays the switching on of the primary driver relative to the switching off of the related secondary and subsequently delays the switching on of the secondary relative to the switching off of the related primary. Typical variation in the tBBM3 and tBBM4 delay with LX voltage is shown in graphs tBBM3, tBBM4 and for RBBM = 33 kΩ. This is due to a reduction in propagation delay through the highside driver path as the LX voltage increases and must be considered in setting the delay for the system level design. Variation of BBM time with RBBM is shown in graph tBBM1 to tBBM4 vs. RBBM. Primary High- and Low-Side MOSFET Drivers The drive voltage for the low-side MOSFET switch is provided directly from VCC. The high-side MOSFET however requires the gate voltage to be enhanced above VIN. This is achieved by bootstraping the VCC voltage onto the LX voltage (the high-side MOSFET source). In order to provide the bootstrapping an external diode and capacitor are required as shown on the application schematic. The capacitor will charge up after the low-side driver has turned on. The switch gate drive signals DH and DL are shown in Figure 3. Secondary MOSFET Drivers The secondary side MOSFETs are driven from the Si9122 via a center tapped pulse transformer and inverter drivers. The waveforms from the IC SRH and SRL are shown in Figure 3. Of importance is the relative voltage between SRH and SRL, i.e. that which is presented across the primary of the pulse transformer. When both potentials of SRL and SRH are equal then by the action of the inverting driver both secondary MOSFETs are left on. Oscillator The oscillator is designed to operate at a nominal frequency of 500 kHz. The 500 kHz operating frequency allows the converter to minimize the inductor and capacitor size, improving the power density of the converter. The oscillator and therefore the switching frequency is programmable by attaching a resistor to the ROSC pin. Under overload Document Number: 71815 S-80038-Rev. J, 14-Jan-08 Si9122 Vishay Siliconix conditions the oscillator frequency is reduced by the current overload protection to enable a constant current to be maintained into a low impedance circuit. VIN Voltage Monitor - VINDET The chip provides a means of sensing the voltage of VIN, and withholding operation of the output drivers until a minimum voltage of VREF (3.3 V, 300 mV hysteresis), is achieved. This is achieved by choosing an appropriate resistive tap between the ground and VIN, and comparing this voltage with the reference voltage. When the applied voltage is greater than VREF, the output drivers are activated as normal. VINDET also provides the input to the voltage feed forward function. However, if the divided voltage applied to the VINDET pin is greater than VCC - 0.3 V, the high-side driver, DH, will stop switching until the voltage drops below VCC - 0.3 V. Thus, the resistive tap on the VIN divider must be set to accommodate the normal VCC operating voltage to avoid this condition. Alternatively, a zener clamp diode from VINDET to GND may also be used. Current Limit Current mode control providing constant current operation is achieved by monitoring the differential voltage VCS between the CS1 and CS2 pins, which are connected to a current sense resistor on the primary low-side MOSFET. In the absence of an overcurrent condition, VCS is less than lower current limit threshold VTLCL (typical 100 mV); CL_CONT is pulled up linearly via the 120 µA current source (IPU) and both DL and DH switch at half the oscillator set frequency. When a moderate overcurrent condition occurs (VTLCL < VCS < VTHCL), the CL_CONT capacitor will be discharged at a rate that is proportional to VCS - 100 mV by the IPD current source. Both driver outputs are in frequency fold-back mode and the switching frequency becomes roughly 20 % of normal switching frequency. When a severe overcurrent condition occurs (VTHCL < VCS), the NMOS discharges CL_CONT capacitor immediately at 2 mA rate and the CL_CONT voltage will be clamped to 1.2 V disabling both DL and DH outputs. Before VCS reaches severe overcurrent condition, a lowering of the CL_CONT voltage results in PWM control of the output drive being taken over by the current limit control loop through CL_CONT. Current control initially reduces the switching duty cycle toward the minimum the chip can reach (DMIN). If this duty cycle reduction still cannot lower the load current, then the switching frequency will start to fold back to minimum 1/5 of the nominal frequency. This prevents the on-time of the primary drivers from being reduced to below 100 ns and avoids current tails. If VCS > VTHCL, the switching will then stop. With constant current mode control and frequency foldback, protection of the MOSFET switches is increased. The converter reverts to voltage mode operation immediately when the primary current falls below the limit level, and CL_CONT capacitor is charged up and clamped to 6.5 V. The soft-start function does not apply during current limit period, as this would constitute hiccup mode operation. Shutdown Mode If VINDET is forced below the lower threshold, a minimum of 350 mV (VSD), the device will enter SHUTDOWN mode. This powers down all unnecessary functions of the controller, ensures that the primary switches are off and results in a low level current demand from the VIN or VCC supplies. VINEXT REXT VIN PNP Ext (Si9122) Auxillary VCC HVDMOS VCC REG_COMP CEXT 2 nF 14.5 V CVCC 0.5 µF VREF GND Figure 5. High-Voltage Pre-Regulator Circuit VCC AV + Peak Detect OSC IPU 120 µA (nom) GM VOFFSET - CL_CLAMP CL_CONT CS1 CS2 - AV + AV 150 mV REXT Blank + AV GM IPD 0 to 240 µA (nom) CEXT 100 mV Figure 6 . Current Limit Circuit Document Number: 71815 S-80038-Rev. J, 14-Jan-08 www.vishay.com 11 Si9122 Vishay Siliconix TYPICAL CHARACTERISTICS 600 3.300 3.295 500 V REF (V) FOSC (kHz) 3.290 400 3.285 3.280 300 3.275 200 20 30 40 50 60 70 3.270 - 50 80 - 25 0 25 75 Temperature (°C) FOSC vs. ROSC at VCC = 12 V VREF vs. Temperature, VCC = 12 V 100 100 10.0 90 3.6 V = VINDET 80 Duty Cycle (%) 9.5 V REG(V) 50 ROSC (kΩ) 9.0 VINDET > VREF TC = - 11 mV/C 8.5 4.8 V 70 60 7.2 V 50 40 VCC = 12 V 30 20 8.0 10 7.5 - 50 - 25 0 25 50 75 100 125 0 0.0 150 0.5 1.0 Temperature (°C) 2.0 SRL, SRH Duty Cycle vs. VEP VREG vs. Temperature, VIN = 48 V 8.20 25 VCC = 13 V 8.15 23 TC = + 1.25 mV/°C 8.10 VCC = 12 V 21 V SS (V) I SS1 (µA) 1.5 VEP (V) VINDET > VREF 8.05 19 8.00 VCC = 10 V 17 15 - 50 7.95 - 25 0 25 50 75 Temperature (°C) ISS vs. Temperature www.vishay.com 12 100 125 7.90 - 50 - 25 0 25 50 75 100 125 150 Temperature (°C) VSS vs. Temperature, VCC = 12 V Document Number: 71815 S-80038-Rev. J, 14-Jan-08 Si9122 Vishay Siliconix 11 13 10 12 9 11 ICC3 (mA) IREG2 (mA) TYPICAL CHARACTERISTICS 8 10 7 9 6 8 5 - 50 - 25 0 25 50 75 7 - 50 100 - 25 0 75 100 250 250 VCC = 12 V 200 VCC = 12 V 200 150 ISINK (mA) ISOURCE (mA) 50 ICC3 vs. Temperature IREG2 vs. Temperature 100 150 100 50 50 0 0 0 200 400 600 0 800 200 400 600 VOH (mV) VOL (mV) DH, DL ISOURCE vs. VOH DH, DL ISINK vs. VOL 35 800 35 30 30 VCC = 12 V VCC = 12 V 25 25 ISINK (mA) ISOURCE (mA) 25 Temperature (°C) Temperature (°C) 20 15 20 15 10 10 5 5 0 0 0 200 400 600 800 0 200 400 600 VOH (mV) VOL (mV) SRL, SRH ISOURCE vs. VOH SRL, SRH ISINK vs. VOL Document Number: 71815 S-80038-Rev. J, 14-Jan-08 800 www.vishay.com 13 Si9122 Vishay Siliconix TYPICAL CHARACTERISTICS 65 100 VCC = 12 V 90 tBBM4 VCC = 12 V tBBM1 tBBM1 55 80 tBBM4 tBBM2 60 tBBM3 tBBM2 50 45 tBBM (ns) tBBM (ns) 70 tBBM3 35 40 25 30 15 20 25 30 35 40 25 45 30 35 40 45 RBBM (kΩ) RBBM (kΩ) tBBM vs. RBBM, VEP = 0 V tBBM vs. RBBM, VEP = 1.65 V 60 80 tBBM1 = 13 V tBBM1 = 12 V 55 VCC = 12 V RBBM = 33 kΩ tBBM1 = 10 V tBBM1 = 12 70 tBBM1 = 13 50 tBBM1, 2 (ns) tBBM1, 2 (ns) tBBM1 = 10 V 60 VCC = 12 V RBBM = 33 kΩ 50 45 40 tBBM2 = 10 V tBBM2 = 12 V tBBM2 = 12 V 40 tBBM2 = 10 V 35 tBBM2 = 13 V tBBM2 = 13 V 30 - 50 - 25 0 25 50 75 100 30 - 50 125 0 25 50 75 100 125 Temperature (°C) Temperature (°C) tBBM1, 2 vs. Temperature, VEP = 1.65 V tBBM1, 2 vs. Temperature, VEP = 0 V 80 70 65 - 25 VEP = 1.65 V RBBM = 33 kΩ tBBM4 = 10 V VEP = 0 V RBBM = 33 kΩ tBBM4 = 13 V 70 60 60 tBBM13, 4 (ns) tBBM13, 4 (ns) tBBM4 = 12 V 55 tBBM4 = 13 V 50 45 tBBM3 = 13 V tBBM4 = 12 V tBBM4 = 10 V 50 40 tBBM3 = 12 V tBBM3 = 10 V tBBM3 = 12 V 40 30 35 30 - 50 tBBM3 = 10 V - 25 0 tBBM3 = 13 V 25 50 75 100 Temperature (°C) tBBM3, 4 vs. Temperature, VEP = 0 V www.vishay.com 14 125 20 - 50 - 25 0 25 50 75 100 125 Temperature (°C) tBBM3, 4 vs. Temperature, VEP = 1.65 V Document Number: 71815 S-80038-Rev. J, 14-Jan-08 Si9122 Vishay Siliconix TYPICAL CHARACTERISTICS 80 55 tBBM1 = 13 V tBBM1 = 12 V tBBM1 = 10 V 50 tBBM1, 2 (ns) tBBM1, 2 (ns) 70 tBBM1 = 13 V 60 VEP = 0 V 50 tBBM2 = 10 V tBBM1 = 10 V 45 VEP = 1.65 V tBBM2 = 12 V 40 40 tBBM2 = 13 V tBBM2 = 13 V tBBM2 = 12 V 30 3.5 tBBM1 = 12 V tBBM2 = 10 V 4.5 5.5 6.5 35 3.5 7.5 4.5 VINDER (V) 5.5 6.5 7.5 VINDER (V) tBBM1, 2 vs. VCC vs. VINDET tBBM1, 2 vs. VINDET vs. VCC 80 65 VEP = 0 V tBBM4 = 10 V 60 70 tBBM4 = 10 V tBBM4 = 12 V tBBM4 = 12 V 55 tBBM13, 4 (ns) tBBM13, 4 (ns) tBBM4 = 13 V 60 tBBM4 = 13 V 50 tBBM3 = 12 V tBBM3 = 10 V 50 45 VEP = 1.65 V 40 tBBM3 = 10 V 40 tBBM3 = 12 V tBBM3 = 13 V 35 tBBM3 = 13 V 30 3.5 4.5 5.5 6.5 30 3.5 7.5 4.5 5.5 6.5 VINDER (V) VINDER (V) tBBM3, 4 vs. VCC vs. VINDET tBBM3, 4 vs. VINDET vs. VCC 500 60 7.5 500 50 400 D% 300 30 200 20 IOUT 100 10 VOUT 0 0.0 0 0.2 0.4 0.6 0.8 RLOAD (Ω) IOUT vs. RLOAD (VIN = 7.2 V) Document Number: 71815 S-80038-Rev. J, 14-Jan-08 1.0 45 Frequency 400 40 D% 35 30 300 DDL 25 DSRL 200 20 Frequency (kHz) 40 Frequency (kHz) I OUT, Duty Cycle %. V OUT 50 V ROSC (V), SRL, SRH, Duty Cycle (%) Frequency 15 10 100 VROSC 5 0 0 1 2 3 4 5 VCLCONT (V) Current Sense Duty Cycle vs. VCLCONT VINDET = 7.2 V 25 °C www.vishay.com 15 Si9122 Vishay Siliconix TYPICAL WAVEFORMS SRL 10 V/div SRL 10 V/div IOUT 5 A /div IOUT 5 A /div DL 10 V/div DL 5 V/div CS2 5 V/div CS2 50 mV/div 2 µs/div 2 µs/div Figure 8. Normal Mode, RL = 0.1 Ω Figure 7. Foldback Mode, RL = 0.02 Ω VCL 2 V/div VIN 2 V/div VEP 2 V/div IOUT 10 A/div VOUT 2 V/div VCC 2 V/div 200 µs/div 2 ms/div Figure 9. VCC Ramp-Up Figure 10. Overload Recovery - Minimum Overshoot DH 5 V/div LX 20 V/div SRL 5 V/div DL 5 V/div SRH 2 V/div SRH 5 V/div SRL 2 V/div 500 ns/div Figure 11. Effective BBM - Measured On Secondary 500 ns/div Figure 12. Drive Waveforms Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?71815. www.vishay.com 16 Document Number: 71815 S-80038-Rev. J, 14-Jan-08 Package Information Vishay Siliconix TSSOP: 20-LEAD (POWER IC ONLY) B D 4X N 0.20 C A−B D 0.20 H A−B D 2X N/2 TIPS E1 E bbb 1.00 b M C A−B A2 E/2 D 9
0.05 C A 1 2 3 1.00 DIA. aaa H A1 e 1.00 C C SEATING PLANE A D (14_) SIDE VIEW MILLIMETERS 0.25 PARTING LINE + + H L (∝) 6 c 1.00 B B (14_) DETAIL ‘A’ (SCALE: 30/1) (VIEW ROTATED 90_ C.W.) C L e/2 X X = A and B LEAD SIDES TOP VIEW Document Number: 72818 28-Jan-04 SEE DETAIL ‘A’ Dim A A1 A2 aaa b b1 bbb c c1 D E E1 e L N P P1 ∝ Min Nom Max — — 1.10 0.05 — 0.15 0.85 0.90 0.95 0.076 0.19 − 0.30 0.19 0.22 0.25 0.10 0.09 0.09 − 0.20 0.127 0.16 6.50 BSC 6.40 BSC 4.30 4.40 4.50 0.65 BSC 0.50 0.60 0.70 20 4.2 3.0 0_ — 8_ ECN: S-40082—Rev. A, 02-Feb-04 DWG: 5923 END VIEW www.vishay.com 1 Package Information Vishay Siliconix -B- PowerPAKr MLP65-18/20 (POWER IC ONLY) D D/2 NXb Index Area D/2 E/2 -A- bbb M A B C NXb 2x E/2 E2/2 E2 2.00 aaa C E Index Area D/2 E/2 aaa NXL 2x C Detail D D2/2 D2 TOP VIEW BOTTOM VIEW A // ccc C 0.08 C A3 SEATING NX PLANE -C- SIDE VIEW A1 # IDENTIFIER TYPE A Chamber e/2 Terminal Tip e Terminal Tip e 5 EVEN TERMINAL SIDE 5 ODD TERMINAL SIDE DETAIL B Document Number: 73182 15-Oct-04 www.vishay.com 1 Package Information Vishay Siliconix PowerPAK MLP65-18/20 (POWER IC ONLY) N = 18/20 PITCH: 0.5 mm, BODY SIZE: 6.00 x 5.00 MILLIMETERS* Dim Min Nom A 0.80 0.90 A1 0.00 0.02 A2 0.00 0.65 A3 0.20 REF aaa − 0.15 b 0.18 0.25 bbb − 0.10 C’ − 0.225 ccc − 0.10 D 6.00 BSC D2 4.00 4.15 E 5.00 BSC E2 3.00 3.15 e − 0.50 L 0.45 0.55 N 18, 20 ND(18) 9 NE(18) 0 ND(20) 10 NE(20) 0 * Use millimeters as the primary measurement. INCHES Max Min Nom Max Notes 1.00 0.05 1.00 0.031 0.000 0.000 0.039 0.002 0.004 1, 2 1, 2 1, 2 − 0.30 − − − − 0.007 − − − 4.25 0.157 3.25 − 0.65 0.118 − 0.018 0.035 0.001 0.003 0.008 REF 0.006 0.010 0.004 0.009 0.004 0.236 BSC 1.63 0.197 BSC 0.124 0.020 0.022 18, 20 9 0 10 0 − 0.012 − − − 0.167 0.128 − 0.026 8 4, 10 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 ECN: S-41946—Rev. A, 18-Oct-04 DWG: 5939 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters. All angels are in degrees. 3. N is the total number of terminals. 4. The terminal #1 identifier and terminal numbering convention shall conform to JEDEC publication 95 SSP-022. Details of terminal #1 identifier are optional, but must be located within the zone indicated. A dot can be marked on the top side by pin 1 to indicate orientation. 5. ND and NE refer to the number of terminals on the D and E side respectively. 6. Depopulation is possible in a symmetrical fashion. 7. NJR refers to NON JEDEC REGISTERED. 8. Dimension “b” applies to metalized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has optional radius on the other end of the terminal, the dimension “b” should not be measured in that radius area. 9. Coplanarity applies to the exposed heat slug as well as the terminal. 10. The 45_ chamfer dimension C’ is located by pin 1 on the bottom side of the package. www.vishay.com 2 Document Number: 73182 15-Oct-04 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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ALL RIGHTS RESERVED Revision: 01-Jan-2022 1 Document Number: 91000