SiC402A, SiC402BCD
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Vishay Siliconix
10 A microBUCK® SiC402A/B
Integrated Buck Regulator with Programmable LDO
FEATURES
• High efficiency > 95 %
• 10 A continuous output current capability
• Integrated bootstrap switch
• Programmable 200 mA LDO with bypass logic
• Temperature compensated current limit
• All ceramic solution enabled
• Pseudo fixed-frequency adaptive on-time control
• Programmable input UVLO threshold
DESCRIPTION
• Independent enable pin for switcher and LDO
The Vishay Siliconix SiC402A/B an advanced stand-alone
synchronous buck regulator featuring integrated power
MOSFETs, bootstrap switch, and a programmable LDO in a
space-saving PowerPAK® MLP32-55G pin packages.
• Selectable ultra sonic power-save mode (SiC402A)
The SiC402A/B are capable of operating with all ceramic
solutions and switching frequencies up to 1 MHz. The
programmable frequency, synchronous operation and
selectable power-save allow operation at high efficiency
across the full range of load current. The internal LDO may
be used to supply 5 V for the gate drive circuits or it may be
bypassed with an external 5 V for optimum efficiency and
used to drive external n-channel MOSFETs or other loads.
Additional features include cycle-by-cycle current limit,
voltage soft-start, under voltage protection, programmable
over current protection, soft shutdown and selectable
power-save. The Vishay Siliconix SiC402A/B also provides
an enable input and a power good output.
• Selectable power-save mode (SiC402B)
• Programmable soft-start and soft-shutdown
• 1 % internal reference voltage
• Power good output
• Over voltage and under voltage protections
• PowerCAD simulation software available at
www.vishay.com/power-ics/powercad-list/
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
• Notebook, desktop, and server computers
• Digital HDTV and digital consumer applications
• Networking and telecommunication equipment
• Printers, DSL, and STB applications
PRIMARY CHARACTERISTICS
Input voltage range
• Embedded applications
3 V to 28 V
Output voltage range a
0.6 V to VIN x 0.75
Operating frequency
200 kHz to 1 MHz
Continuous output current
Peak efficiency
Package
10 A
95 %
• Point of load power supplies
TYPICAL APPLICATION CIRCUIT AND
PACKAGE OPTIONS
PowerPAK MLP32-55G
3.3 V
Note
a. See “High Output Voltage Operation” section
EN/PSV (Tri-State)
PGOOD
LX
ILIM
PGOOD
LX
AGND
TON
ENL
EN\PSV
LDO_EN
VOUT
32 31 30 29 28 27 26 25
FB
1
VOUT
VDD
AGND
FBL
VIN
VIN
24
PAD 1
2
23
AGND
3
22
PAD 3
4
5
PAD 2
6
SS 7
BST
21
LX
20
19
VIN
PGND
PGND
PGND
18
PGND
17
PGND
16
13
VOUT
NC 14
PGND
15
PGND
11
NC 12
LX
VIN
9
VIN
VIN
10
8
LX
LX
PGND
Typical Application Circuit for SiC402A/B (PowerPAK
MLP32-55G)
S20-0483-Rev. D, 29-Jun-2020
Document Number: 63729
1
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LX
ILIM
PGOOD
EN\PSV
LX
tON
AGND
ENL
PIN CONFIGURATION (Top View)
32 31 30 29 28 27 26 25
FBL
5
VIN
6
7
BST
8
PAD 3
LX
PAD 2
VIN
VIN
9
SS
AGND
24
LX
23
LX
22
PGND
21
PGND
20
PGND
19
PGND
18
PGND
17
PGND
PGND 16
4
NC 14
3
PGND 15
VDD
AGND
PAD 1
LX 13
2
NC 12
VOUT
VIN 11
1
VIN 10
FB
SiC402A/B Pin Configuration (Top View)
PIN DESCRIPTION
PIN NUMBER
SYMBOL
DESCRIPTION
1
FB
Feedback input for switching regulator used to program the output voltage - connect to an external
resistor divider from VOUT to AGND
2
VOUT
Switcher output voltage sense pin - also the input to the internal switch-over between VOUT and
VLDO. The voltage at this pin must be less than or equal to the voltage at the VDD pin
3
VDD
Bias supply for the IC - when using the internal LDO as a bias power supply, VDD is the LDO output.
When using an external power supply as the bias for the IC, the LDO output should be disabled
4, 30, PAD 1
AGND
Analog ground
5
FBL
Feedback input for the internal LDO - used to program the LDO output. Connect to an external
resistor divider from VDD to AGND
6, 9 to 11, PAD 2
VIN
Input supply voltage
7
SS
The soft start ramp will be programmed by an internal current source charging a capacitor on this
pin.
8
BST
Bootstrap pin - connect a capacitor of at least 100 nF from BST to LX to develop the floating supply
for the high side gate drive
12, 14
NC
No connection
13
LXBST
23 to 25, PAD 3
LX
15 to 22
PGND
Power ground
26
PGOOD
Open-drain power good indicator - high impedance indicates power is good. An external pull-up
resistor is required
27
IILIM
28
LXS
LX boost - connect to the BST capacitor
Switching (phase) node
Current limit sense pin - used to program the current limit by connecting a resistor from ILIM to LXS
LX sense - connects to RILIM
Enable/power-save input for the switching regulator - connect to AGND to disable the switching
regulator, connect to VDD to operate with power-save mode and float to operate in forced
continuous mode
29
EN/PSV
31
tON
On-time programming input - set the on-time by connecting through a resistor to AGND
32
ENL
Enable input for the LDO - connect ENL to AGND to disable the LDO. Drive with logic signal for logic
control, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND
ORDERING INFORMATION
PART NUMBER
PACKAGE
SiC402ACD-T1-GE3
PowerPAK
MLP32-55G
SiC402BCD-T1-GE3
SiC402DB
S20-0483-Rev. D, 29-Jun-2020
P/N
MARKING
(LINE 1: P/N)
II
SiC402A
SiC402B
Reference board
Format:
Fyww
Line 1: Dot
Line 2: P/N
Line 3: Siliconix Logo + LOT Code + ESD Symbol
Line 4: Factory Code + Year Code + Work Week Code
Document Number: 63729
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SiC402A, SiC402BCD
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FUNCTIONAL BLOCK DIAGRAM
NC
NC
SiC402A/B Functional Block Diagram
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
ELECTRICAL PARAMETER
VIN
CONDITIONS
LIMITS
To PGND
-0.3 to 30
VIN
To VDD
-0.4 max.
LX
To PGND
-0.3 to 30
LX (transient < 100 ns)
To PGND
-2 to 30
VDD
To PGND
-0.3 to 6
Reference to AGND
-0.3 to + (VDD + 0.3)
To PGND
-0.3 to + (VDD - 1.5)
EN/PSV, PGOOD, ILIM, SS, VOUT, FB, FBL
tON
BST
To LX
-0.3 to 6
To PGND
-0.3 to 35
ENL
-0.3 to VIN
AGND to PGND
-0.3 to 0.3
UNIT
V
Temperature
Maximum junction temperature
150
Storage temperature
-65 to +150
°C
Power Dissipation
Junction-to-ambient thermal impedance (RthJA) b
Maximum power dissipation
IC section
50
Ambient temperature = 25 °C
3.4
Ambient temperature = 100 °C
1.3
°C/W
W
ESD Protection
HBM
2
CDM
1
kV
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating/conditions for extended periods may affect device reliability.
S20-0483-Rev. D, 29-Jun-2020
Document Number: 63729
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RECOMMENDED OPERATING RANGE (all voltages referenced to GND = 0 V)
PARAMETER
VIN
VDD to PGND
VOUT
MIN.
TYP.
MAX.
3
-
28
3
-
5.5
0.6
-
VIN x 0.75
UNIT
V
Temperature
Operating junction temperature
-40 to +125
Recommended ambient temperature
-40 to +85
°C
ELECTRICAL SPECIFICATIONS
PARAMETER
SYMBOL
TEST CONDITIONS UNLESS SPECIFIED
VIN = 12 V, TA = +25 °C for typ.,
-40 °C to +85 °C for min. and max.,
TJ = < 125 °C, VDD = +5 V,
typical application circuit
LIMITS
UNIT
MIN.
TYP.
MAX.
3
-
28
Input Supplies
Input supply voltage
VIN
VDD
VDD
VIN UVLO threshold a
VUVLO
VIN UVLO hysteresis
VUVLO, HYS
VDD UVLO threshold
VUVLO
VDD UVLO hysteresis
VUVLO, HYS
VIN supply current
IIN
VDD supply current
IDD
FB on-time threshold
Frequency range
fsw
3
-
5.5
Sensed at ENL pin, rising
2.4
2.6
2.95
Sensed at ENL pin, falling
2.23
2.4
2.57
-
0.25
-
Measured at VDD pin, rising
2.5
-
3
Measured at VDD pin, falling
2.4
-
2.9
-
0.2
-
EN/PSV, ENL = 0 V, VIN = 28 V
-
10
20
Standby mode: ENL = VDD, EN/PSV = 0 V
-
160
-
EN/PSV, ENL = 0 V
-
190
300
SiC402A, EN/PSV = V5V, no load
(fSW = 25 kHz), VFB > 0.6 V b
-
0.3
-
SiC402B, EN/PSV = V5V, no load
VFB > 0.6 V b
-
0.7
-
VDD = 5 V, fSW = 250 kHz,
EN/PSV = floating, no load b
-
8
-
VDD = 3 V, fSW = 250 kHz,
EN/PSV = floating, no load b
-
5
-
0.600
0.606
V
μA
mA
Static VIN and load
0.594
Continuous mode operation
-
Minimum fSW, (SiC402A only)
-
25
-
-
10
-
Continuous mode operation VIN = 15 V,
VOUT = 5 V, fSW = 300 kHz, RtON = 133 k
999
1110
1220
-
80
-
VDD = 5 V
-
250
-
VDD = 3 V
-
370
-
-
3
-
μA
-
1.5
-
V
-
500
-
k
-3
-
+3
mV
Bootstrap switch resistance
1000
V
kHz
Timing
On-time
tON
Minimum on-time b
Minimum off-time
b
tON min.
tOFF min.
ns
Soft Start
Soft start current b
ISS
Soft start voltage b
VSS
When VOUT reaches regulation
Analog Inputs/Outputs
VOUT input resistance
Current Sense
Zero-crossing detector threshold voltage
S20-0483-Rev. D, 29-Jun-2020
LX-PGND
Document Number: 63729
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Vishay Siliconix
ELECTRICAL SPECIFICATIONS
PARAMETER
SYMBOL
TEST CONDITIONS UNLESS SPECIFIED
VIN = 12 V, TA = +25 °C for typ.,
-40 °C to +85 °C for min. and max.,
TJ = < 125 °C, VDD = +5 V,
typical application circuit
LIMITS
UNIT
MIN.
TYP.
MAX.
-
+20
-
-
-10
-
-
12
7
5
10
1
-
8.5
10
11.5
-10
8.5
10
0
+10
-
-25
-
-
+10
-
-
+20
-
10 °C hysteresis
-
5
150
-
VDD = 5 V
1
2.2
-
0.4
5
1
-
2
0
-10
-1
10
-
0.4
+10
18
+1
-
0.75
-
-
65
-
-
115
-
135
200
-
-130
-500
-
2
+130
+500
-
-
1.2
-
Power Good
PG_VTH_UPPER
Power good threshold voltage
PG_VTH_LOWER
Start-up delay time
(between PWM enable and PGOOD high)
Fault (noise-immunity) delay time b
Leakage current
Power good on-resistance
Fault Protection
Vally current Limit c
ILIM source current
ILIM comparator offset voltage
PG_Td
PG_ICC
PG_ILK
PG_RDS-ON
ILIM
VILM-LK
Output under voltage fault
VOUV_Fault
Smart power-save protection
threshold b
PSAVE_VTH
Over voltage protection threshold
Over voltage fault delay b
Over temperature shutdown b
Logic Inputs / Outputs
Logic input high voltage
Logic input low voltage
EN/PSV input for PSAVE operation b
EN/PSV input for forced continuous
operation b
EN/PSV input for disabling switcher
EN/PSV input bias current
ENL input bias current
FBL, FB input bias current
Linear Dropout Regulator
FBL b
LDO current limit
VLDO to VOUT switch-over threshold d
VLDO to VOUT non-switch-over threshold d
VLDO to VOUT switch-over resistance
LDO drop out voltage e
Upper limit, VFB > internal 600 mV
reference
Lower limit, VFB < internal 600 mV
reference
VDD = 5 V, Css = 10 nF
VDD = 3 V, Css = 10 nF
tOV-Delay
TShut
VDD = 5 V, RILIM = 4460,
TJ = 0 °C to +125 °C
VDD = 3 V, RILIM = 4460
With respect to AGND
VFB with respect to internal 600 mV
reference, 8 consecutive clocks
VFB with respect to internal 600 mV
reference
VFB with respect to internal 600 mV
reference
VIH
VIL
IEN
FBL_ILK
EN/PSV = VDD or AGND
ENL = VIN = 28 V
FBL, FB = VDD or AGND
VLDO ACC
LDO_ILIM
VLDO-BPS
VLDO-NBPS
RLDO
Short-circuit protection,
VIN =12 V, VDD < 0.75 V
Start-up and foldback, VIN = 12 V,
0.75 < VDD < 90 % of final VDD value
Operating current limit, VIN = 12 V,
VDD > 90 % of final VDD value
VOUT = 5 V
From VIN to VDD, VDD = +5 V,
IVLDO = 100 mA
%
ms
μs
μA
A
μA
mV
%
μs
°C
V
μA
V
mA
mV
V
Notes
a. VIN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference
b. Typical value measured on standard evaluation board
c. SiC402A/B has first order temperature compensation for over current. Results vary based upon the PCB thermal layout
d. The switch-over threshold is the maximum voltage differential between the VDD and VOUT pins which ensures that VLDO will internally
switch-over to VOUT. The non-switch-over threshold is the minimum voltage differential between the VLDO and VOUT pins which ensures that
VLDO will not switch-over to VOUT
e. The LDO drop out voltage is the voltage at which the LDO output drops 2 % below the nominal regulation point
S20-0483-Rev. D, 29-Jun-2020
Document Number: 63729
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100
100
95
95
90
90
85
85
80
Efficiency (%)
Efficiency (%)
ELECTRICAL CHARACTERISTICS
75
70
65
VIN = 5 V
60
VIN = 12 V
80
75
PSM
70
CCM
65
60
55
55
50
50
0
1
2
3
4
5
I OUT (A)
6
7
8
9
0
10
100
100
95
95
90
90
85
85
80
VIN = 5 V
VIN = 12 V
VIN = 18 V
75
70
65
3
4
5
I OU T ( A )
6
7
8
9
10
8
9
10
8
9
10
80
75
PSM
70
CCM
65
60
60
55
55
50
50
0
1
2
3
4
I OU T
5
(A)
6
7
8
9
0
10
1
2
3
4
5
6
7
I OU T ( A )
Fig. 2 - PSM Efficiency - VIN vs. Load
(VDD = 5 V, VOUT = 1.5 V)
Fig. 5 - Efficiency - PSM vs. CCM
(VDD = 5 V, VOUT = 1.5 V, VIN = 12 V)
100
100
95
95
90
90
85
85
80
75
VIN = 5 V
70
VIN = 12 V
65
VIN = 18 V
Efficiency (%)
Efficiency (%)
2
Fig. 4 - Efficiency - PSM vs. CCM
(VDD = 3.3 V, VOUT = 1.5 V, VIN = 12 V)
Efficiency (%)
Efficiency (%)
Fig. 1 - PSM Efficiency - VIN vs. Load
(VDD = 3.3 V, VOUT = 1.5 V)
1
80
75
70
60
60
55
55
50
VDD = 3.3 V
65
VDD = 5 V
50
0
1
2
3
4
5
I OUT (A)
6
7
8
Fig. 3 - PSM Efficiency - VIN vs. Load
(VDD = 5 V, VOUT = 1.5 V)
S20-0483-Rev. D, 29-Jun-2020
9
10
0
1
2
3
4
5
I OU T ( A )
6
7
Fig. 6 - PSM Efficiency - VDD 3.3 V vs. 5 V
(VOUT = 1.5 V, VIN = 12 V)
Document Number: 63729
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1.53
1.54
VIN = 18 V
1.52
VIN = 12 V
1.53
VIN = 12 V
VIN = 5 V
VIN = 5 V
1.52
VOUT (V)
VOUT (V)
1.51
1.50
1.49
1.51
1.50
1.49
1.48
1.48
1.47
1.47
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
9
10
IOUT (A)
IOUT (A)
Fig. 7 - Load Regulation - FCM
(VDD = 5 V, VOUT = 1.5 V)
Fig. 10 - Load Regulation - FCM
(VDD = 3.3 V, VOUT = 1.5 V)
1.54
1.53
VIN = 18 V
VIN = 12 V
1.53
VIN = 12 V
1.52
VIN = 5 V
VIN = 5 V
1.52
VOUT (V)
VOUT (V)
1.51
1.50
1.49
1.51
1.50
1.49
1.48
1.48
1.47
1.47
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
IOUT (A)
5
6
7
8
IOUT (A)
Fig. 8 - Load Regulation - PSM
(VDD = 5 V, VOUT = 1.5 V)
Fig. 11 - Load Regulation - PSM
(VDD = 3.3 V, VOUT = 1.5 V)
100
400
350
95
Efficiency (%)
Frequency (KHz)
300
250
200
150
90
VOUT = 5 V
85
VOUT =3.3 V
FCM
100
VOUT =2.5 V
80
PSM
VOUT =1.5 V
50
VOUT = 1 V
75
0
0
1
2
3
4
5
6
I OUT (A)
7
8
9
Fig. 9 - Switching Frequency - PSM vs. FCM
(VDD = 5 V, VOUT = 1.5 V, VIN = 12 V)
S20-0483-Rev. D, 29-Jun-2020
10
0
1
2
3
4
5
6
I OUT (A)
7
8
9
10
Fig. 12 - Switching Frequency - PSM vs. FCM
(VDD = 5 V, VIN = 12 V)
Document Number: 63729
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Fig. 13 - Start-Up - EN/PSV
(VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 0 A)
Fig. 16 - Shutdown - EN/PSV
(VDD = 5 V, VIN = 1.5 V, IOUT = 0 A)
Fig. 14 - Start-Up (Pre-Bias) - EN/PSV
(VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 0 A)
Fig. 17 - Ultra-sonic PSM - SiC402ACD
(VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 0 A)
Fig. 15 - Start-Up (Pre-Bias) - EN/PSV
(VDD = 5 V, VIN = 1.5 V, IOUT = 0 A)
Fig. 18 - Forced Continuous Mode - SiC402ACD
(VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 10 A)
S20-0483-Rev. D, 29-Jun-2020
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Fig. 19 - Transient Response - PSM Rising (VDD = 5 V,
VIN = 12 V, VOUT = 1.5 V, IOUT = 0.5 A to 8.5 A, dI/dt = 1 A/μs)
Fig. 21 - Transient Response - PSM Falling (VDD = 5 V,
VIN = 12 V, VOUT = 1.5 V, IOUT = 8.5 A to 0.5 A, dI/dt = 1 A/μs)
Fig. 20 - Transient Response - FCM (VDD = 5 V,
VIN = 12 V, VOUT = 1.5 V, IOUT = 2.5 A to 10 A, dI/dt = 1 A/μs)
Fig. 22 - Thermal Shutdown - 146 °C
(VIN = 12 V, VOUT = 2.5 A to 10 A, dI/dt = 1 A/μs)
S20-0483-Rev. D, 29-Jun-2020
Document Number: 63729
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OPERATIONAL DESCRIPTION
Device Overview
The SiC402A/B is a step down synchronous DC/DC buck
converter with integrated power MOSFETs and a 200 mA
capable programmable LDO. The device is capable of
10 A operation at very high efficiency. A space saving
5 x 5 (mm) 32-pin package is used. The programmable
operating frequency of up to 1 MHz enables optimizing
the configuration for PCB area and efficiency.
The buck controller uses a pseudo-fixed frequency adaptive
on-time control. This control method allows fast transient
response which permits the use of smaller output
capacitors.
tON
VIN
VLX
CIN
VFB
Q1
FB threshold
VLX
VOUT
L
Q2
ESR
FB
+
Input Voltage Requirements
The SiC402A/B requires two input supplies for normal
operation: VIN and VDD. VIN operates over a wide range from
3 V to 28 V. VDD requires a 3 V to 5.5 V supply input that can
be an external source or the internal LDO configured to
supply 3 V to 5.5 V from VIN.
Power Up Sequence
When the SiC402A/B uses an external power source at the
VDD pin, the switching regulator initiates the start up when
VIN, VDD and EN/PSV are above their respective thresholds.
When EN/PSV is at logic high, VDD needs to be applied after
VIN rises. It is also recommended to use a 10 resistor
between an external power source and the VDD pin. To start
up by using the EN/PSV pin when both VDD and VIN are
above their respective thresholds, apply EN/PSV to enable
the start-up process. For SiC402A/B in self-biased mode,
refer to the LDO section for a full description.
Shutdown
The SiC402A/B can be shut-down by pulling either VDD or
EN/PSV below its threshold. When using an external power
source, it is recommended that the VDD voltage ramps down
before the VIN voltage. When VDD is active and EN/PSV at
logic low, the output voltage discharges into the VOUT pin
through an internal FET.
Pseudo-Fixed Frequency Adaptive On-Time Control
The PWM control method used for the SiC402A/B is
pseudo-fixed frequency, adaptive on-time, as shown in
Fig. 23. The ripple voltage generated at the output capacitor
ESR is used as a PWM ramp signal. This ripple is used to
trigger the on-time of the controller.
S20-0483-Rev. D, 29-Jun-2020
COUT
Fig. 23 - PWM Control Method, VOUT Ripple
The adaptive on-time is determined by an internal one-shot
timer. When the one-shot is triggered by the output ripple,
the device sends a single on-time pulse to the highside
MOSFET. The pulse period is determined by VOUT and VIN;
the period is proportional to output voltage and inversely
proportional to input voltage. With this adaptive on-time
arrangement, the device automatically anticipates the
on-time needed to regulate VOUT for the present VIN
condition and at the selected frequency.
The advantages of adaptive on-time control are:
• Predictable operating frequency compared to other
variable frequency methods.
• Reduced component count by eliminating the error
amplifier and compensation components.
• Reduced component count by removing the need to
sense and control inductor current.
• Fast transient response - the response time is controlled
by a fast comparator instead of a typically slow error
amplifier.
• Reduced output capacitance due to fast transient
response.
One-Shot Timer and Operating Frequency
The one-shot timer operates as shown in Fig. 24. The FB
comparator output goes high when VFB is less than the
internal 600 mV reference. This feeds into the gate drive and
turns on the high side MOSFET, and also starts the one-shot
timer. The one-shot timer uses an internal comparator and a
capacitor. One comparator input is connected to VOUT, the
other input is connected to the capacitor. When the on-time
begins, the internal capacitor charges from zero volts
through a current which is proportional to VIN. When the
capacitor voltage reaches VOUT, the on-time is completed
and the high side MOSFET turns off.
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VOUT is shown by the following equation.
Gate
drives
FB comparator
FB
VREP
VOUT
VIN
Rton
VIN
+
DH
Q1
VLX
DL
Q2
VOUT = 0.6 x 1 +
VOUT
L
ESR
One-shot
timer
Fig. 24 - On-Time Generation
This method automatically produces an on-time that is
proportional to VOUT and inversely proportional to VIN. Under
steady-state conditions, the switching frequency can be
determined from the on-time by the following equation.
VOUT
tON x VIN
The SiC402A/B uses an external resistor to set the on-time
which indirectly sets the frequency. The on-time can be
programmed to provide an operating frequency up to 1 MHz
using a resistor between the tON pin and ground. The
resistor value is selected by the following equation.
Rton =
(VDD - 1.75) x 10
VIN
The maximum RtON value allowed is shown by the following
equation.
Rton_MAX. =
VRIPPLE
2
1 + (R1ωCTOP)2
x
1+
R2 x R1
ωCTOP
R2 + R1
2
Enable and Power-Save Inputs
The EN/PSV input is used to enable or disable the switching
regulator. When EN/PSV is low (grounded), the switching
regulator is off and in its lowest power state. When off, the
output of the switching regulator soft-discharges the output
into a 500 k internal resistor via the VOUT pin. When
EN/PSV is allowed to float, the pin voltage will float to 33 %
of the voltage at VDD. The switching regulator turns on with
power-save disabled and all switching is in forced
continuous mode.
When EN/PSV is high (above 44 % of the voltage at VDD), the
switching regulator turns on with power-save enabled. The
SiC402A/B PSAVE operation reduces the switching
frequency according to the load for increased efficiency at
light load conditions.
Forced Continuous Mode Operation
k
25 pF x fsw
The constant, k, equals 1, when VDD is greater than 3.6 V.
If VDD is less than 3.6 V and VIN is greater than
(VDD - 1.75) x 10, k is shown by the following equation.
k=
+
FB
+
COUT
On-time = K x Rton x (VOUT/VIN)
fSW =
R1
R2
VIN_MIN.
15 µA
The SiC402A/B operates the switcher in FCM (forced
continuous mode) by floating the EN/PSV pin (see Fig. 26).
In this mode one of the power MOSFETs is always on, with
no intentional dead time other than to avoid
cross-conduction. This feature results in uniform frequency
across the full load range with the trade-off being poor
efficiency at light loads due to the high frequency switching
of the MOSFETs. DH is gate signal to drive upper MOSFET.
DL is lower gate signal to drive lower MOSFET.
VOUT Voltage Selection
The switcher output voltage is regulated by comparing VOUT
as seen through a resistor divider at the FB pin to the internal
600 mV reference voltage, see Fig. 25.
VOUT
to FB pin
FB ripple
voltage (VFB)
FB threshold
DC load current
Inductor
current
R1
R2
On-time
(tON)
Fig. 25 - Output Voltage Selection
Note that this control method regulates the valley of the
output ripple voltage, not the DC value. The DC output
voltage VOUT is offset by the output ripple according to the
following equation.
VOUT = 0.6 x
1+
R1
R2
+
VRIPPLE
2
DH on-time is triggered when
VFB reaches the FB threshold
DH
DL
DL drives high when on-time is completed.
DL remains high until VFB falls to the FB threshold.
Fig. 26 - Forced Continuous Mode Operation
When a large capacitor is placed in parallel with R1 (CTOP) .
S20-0483-Rev. D, 29-Jun-2020
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Ultrasonic Power-Save Operation (SiC402A)
The SiC402A provides ultrasonic power-save operation at
light loads, with the minimum operating frequency fixed at
slightly under 25 kHz. This is accomplished by using an
internal timer that monitors the time between consecutive
high side gate pulses. If the time exceeds 40 μs, DL drives
high to turn the low side MOSFET on. This draws current
from VOUT through the inductor, forcing both VOUT and VFB
to fall. When VFB drops to the 600 mV threshold, the next DH
(the drive signal for the high side FET) on-time is triggered.
After the on-time is completed the high side MOSFET is
turned off and the low side MOSFET turns on. The low side
MOSFET remains on until the inductor current ramps down
to zero, at which point the low side MOSFET is turned off.
Because the on-times are forced to occur at intervals no
greater than 40 μs, the frequency will not fall far below
25 kHz. Fig.27 shows ultrasonic power-save operation.
Fig. 28 - Power-Save Mode
minimum fSW ~ 25 kHz
Smart Power-Save Protection
FB ripple
voltage (VFB)
FB threshold
(600 mV)
(0 A)
Inductor
current
On-time
(tON)
DH on-time is triggered when
VFB reaches the FB threshold
DH
40 μs time-out
DL
After the 40 µs time-out, DL drives high if VFB
has not reached the FB threshold.
Fig. 27 - Ultrasonic Power-Save Operation
Power-Save Operation (SiC402B)
The SIC402B provides power-save operation at light loads
with no minimum operating frequency. With power-save
enabled, the internal zero crossing comparator monitors the
inductor current via the voltage across the low side MOSFET
during the off-time. If the inductor current falls to zero for 8
consecutive switching cycles, the controller enters MOSFET
on each subsequent cycle provided that the power-save
operation. It will turn off the low side MOSFET on each
subsequent cycle provided that the current crosses zero. At
this time both MOSFETs remain off until VFB drops to the
600 mV threshold. Because the MOSFETs are off, the load
is supplied by the output capacitor.
Active loads may leak current from a higher voltage into the
switcher output. Under light load conditions with
power-save enabled, this can force VOUT to slowly rise and
reach the over voltage threshold, resulting in a hard
shut-down. Smart power-save prevents this condition.
When the FB voltage exceeds 10 % above nominal, the
device immediately disables power-save, and DL drives
high to turn on the low side MOSFET. This draws current
from VOUT through the inductor and causes VOUT to fall.
When VFB drops back to the 600 mV trip point, a normal tON
switching cycle begins. This method prevents a hard OVP
shut-down and also cycles energy from VOUT back to VIN. It
also minimizes operating power by avoiding forced
conduction mode operation. Fig. 29 shows typical
waveforms for the smart power-save feature.
VOUT drifts up to due to leakage
current flowing into COUT
Smart power save
threshold
FB
threshold
VOUT discharges via inductor
and low-side MOSFET
Normal VOUT ripple
DH and DL off
High-side
drive (DH)
Single DH on-time pulse
after DL turn-off
Low-side
drive (DL)
DL turns on when smart
PSAVE threshold is reached
DL turns off FB
threshold is reached
Normal DL pulse after DH
on-time pulse
Fig. 29 - Smart Power-Save
If the inductor current does not reach zero on any switching
cycle, the controller immediately exits power-save and
returns to forced continuous mode.
Fig. 28 shows power-save operation at light loads.
S20-0483-Rev. D, 29-Jun-2020
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SmartDriveTM
Soft-Start of PWM Regulator
For each DH pulse the DH driver initially turns on the high
side MOSFET at a lower speed, allowing a softer, smooth
turn-off of the low side diode. Once the diode is off and the
LX voltage has risen 0.5 V above PGND, the SmartDrive
circuit automatically drives the high side MOSFET on at a
rapid rate. This technique reduces switching losses while
maintaining high efficiency and also avoids the need for
snubbers for the power MOSFETs.
SiC402A/B has a programmable soft-start time that is
controlled by an external capacitor at the SS pin. After the
controller meets both UVLO and EN/PSV thresholds, the
controller has an internal current source of 3 μA flowing
through the SS pin to charge the capacitor. During the start
up process (Fig. 31), 50 % of the voltage at the SS pin is
used as the reference for the FB comparator. The PWM
comparator issues an on-time pulse when the voltage at the
FB pin is less than 40 % of the SS pin. As a result, the output
voltage follows the SS voltage. The output voltage reaches
and maintains regulation when the soft start voltage is
1.5 V. The time between the first LX pulse and VOUT
reaching regulation is the soft-start time (tSS). The
calculation for the soft-start time is shown by the following
equation.
Current Limit Protection
The device features programmable current limiting, which is
accomplished by using the RDS(on) of the lower MOSFET for
current sensing. The current limit is set by RILIM resistor. The
RILIM resistor connects from the ILIM pin to the LXS pin which
is also the drain of the low side MOSFET. When the low side
MOSFET is on, an internal ~10 μA current flows from the ILIM
pin and through the RILIM resistor, creating a voltage drop
across the resistor. While the low side MOSFET is on, the
inductor current flows through it and creates a voltage
across the RDS(on). The voltage across the MOSFET is
negative with respect to ground. If this MOSFET voltage
drop exceeds the voltage across RILIM, the voltage at the ILIM
pin will be negative and current limit will activate. The
current limit then keeps the low side MOSFET on and will not
allow another high side on-time, until the current in the low
side MOSFET reduces enough to bring the ILIM voltage back
up to zero. This method regulates the inductor valley current
at the level shown by ILIM in Fig. 30.
tSS = CSS x
1.5 V
3 μA
The voltage at the SS pin continues to ramp up and
eventually equals 64 % of VDD. After the soft start
completes, the FB pin voltage is compared to an internal
reference of 0.6 V. The delay time between the VOUT
regulation point and PGOOD going high is shown by the
following equation.
tPGOOD-DELAY =
CSS x (0.64 x VDD - 1.5 V)
3 μA
Inductor Current
IPEAK
ILOAD
ILIM
Fig. 30 - Valley Current Limit
Setting the valley current limit to 10 A results in a peak
inductor current of 10 A plus peak ripple current. In this
situation, the average (load) current through the inductor is
10 A plus one-half the peak-to-peak ripple current.
The internal 10 μA current source is temperature
compensated at 4100 ppm in order to provide tracking with
the RDS(on).
The RILIM value is calculated by the following equation.
RILIM = 446 x ILIM x [0.099 x (5 V - VDD) + 1]
When selecting a value for RILIM be sure not to exceed the
absolute maximum voltage value for the ILIM pin. Note that
because the low side MOSFET with low RDS(on) is used for
current sensing, the PCB layout, solder connections, and
PCB connection to the LX node must be done carefully to
obtain good results. RILIM should be connected directly to
LXS (pin 28).
S20-0483-Rev. D, 29-Jun-2020
Fig. 31 - Soft-Start Timing Diagram
Pre-Bias Startup
The SiC402A/B can start up normally even when there is an
existing output voltage present. The soft start time is still the
same as normal start up (when the output voltage starts
from zero). The output voltage starts to ramp up when 40 %
of the voltage at SS pin meets the existing FB voltage level.
Pre-bias startup is achieved by turning off the lower gate
when the inductor current falls below zero. This method
prevents the output voltage from discharging.
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Power Good Output
The PGOOD (power good) output is an open-drain output
which requires a pull-up resistor. When the voltage at the FB
pin is 10 % below the nominal voltage, PGOOD is pulled low.
It is held low until the output voltage returns above -8 % of
nominal.
PGOOD will transition low if the VFB pin exceeds +20 % of
nominal, which is also the over voltage shutdown threshold.
PGOOD also pulls low if the EN/PSV pin is low when VDD is
present.
Note that if the LDO voltage is set lower than 4.5 V, the
minimum output capacitance for the LDO is 10 μF.
LDO ENL Functions
The ENL input is used to enable/disable the internal LDO.
When ENL is a logic low, the LDO is off. When ENL is above
the VIN UVLO threshold, the LDO is enabled and the
switcher is also enabled if the EN/PSV and VDD are above
their threshold. The table below summarizes the function of
ENL and EN/PSV pins.
Output Over Voltage Protection
Over voltage protection becomes active as soon as the
device is enabled. The threshold is set at 600 mV +20 %
(720 mV). When VFB exceeds the OVP threshold, DL latches
high and the low side MOSFET is turned on. DL remains high
and the controller remains off, until the EN/PSV input is
toggled or VDD is cycled. There is a 5 μs delay built into the
OVP detector to prevent false transitions. PGOOD is also low
after an OVP event.
Output Under Voltage Protection
When VFB falls 25 % below its nominal voltage (falls to
450 mV) for eight consecutive clock cycles, the switcher is
shut off and the DH and DL drives are pulled low to tri-state
the MOSFETs. The controller stays off until EN/PSV is
toggled or VDD is cycled.
VDD UVLO, and POR
UVLO (Under Voltage Lock-Out) circuitry inhibits switching
and tri-states the DH/DL drivers until VDD rises above 3 V. An
internal POR (Power-On Reset) occurs when VDD exceeds
3 V, which resets the fault latch and a soft-start counter
cycle begins which prepares for soft-start. The SiC402A/B
then begins a soft-start cycle. The PWM will shut off if VDD
falls below 2.4 V.
LDO Regulator
SiC402A/B has an option to bias the switcher by using an
internal LDO from VIN. The LDO output is connected to VDD
internally. The output of the LDO is programmable by using
external resistors from the VDD pin to AGND (see Fig. 32). The
feedback pin (FBL) for the LDO is regulated to 750 mV.
EN/PSV
ENL
LDO
SWITCHER
Disabled
Low, < 0.4 V
Off
Off
Enabled
Low, < 0.4 V
Off
On
Disabled
1 V < High < 2.6 V
On
Off
Enabled
1 V < High < 2.6 V
On
Off
Disabled
High, > 2.6 V
On
Off
Enabled
High, > 2.6 V
On
On
The ENL pin also acts as the switcher under voltage lockout
for the VIN supply. When SiC402A/B is self-biased from the
LDO and runs from the VIN power source only, the VIN UVLO
feature can be used to prevent false UV faults for the PWM
output by programming with a resistor divider at the VIN,
ENL and AGND pins. When SiC402A/B has an external bias
voltage at VDD and the ENL pin is used to program the
VIN UVLO feature, the voltage at FBL needs to be higher
than 750 mV to force the LDO off.
Timing is important when driving ENL with logic and not
implementing VIN UVLO. The ENL pin must transition from
high to low within 2 switching cycles to avoid the PWM
output turning off. If ENL goes below the VIN UVLO threshold
and stays above 1 V, then the switcher will turn off but the
LDO will remain on.
Timing is important when driving ENL with logic and not
implementing VIN UVLO. The ENL pin must transition from
high to low within 2 switching cycles to avoid the PWM
output turning off. If ENL goes below the VIN UVLO threshold
and stays above 1 V, then the switcher will turn off but the
LDO will remain on.
LDO Start-Up
VDD
to FBL pin
RLDO1
Before start-up, the LDO checks the status of the following
signals to ensure proper operation can be maintained.
1. ENL pin
RLDO2
2. VIN input voltage
Fig. 32 - LDO Output Voltage Selection
The LDO output voltage is set by the following equation.
VLDO = 750 mV x
1+
RLDO1
RLDO2
A minimum capacitance of 1 μF referenced to AGND is
normally required at the output of the LDO for stability.
S20-0483-Rev. D, 29-Jun-2020
When the ENL pin is high and VIN is above the UVLO point,
the LDO will begin start-up. During the initial phase, when
the VDD voltage (which is the LDO output voltage) is less
than 0.75 V, the LDO initiates a current-limited start-up
(typically 65 mA) to charge the output capacitors while
protecting from a short circuit event. When VDD is greater
than 0.75 V but still less than 90 % of its final value (as
sensed at the FBL pin), the LDO current limit is increased to
~115 mA. When VDD has reached 90 % of the final value (as
sensed at the FBL pin), the LDO current limit is increased to
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~200 mA and the LDO output is quickly driven to the
nominal value by the internal LDO regulator. It is
recommended that during LDO start-up to hold the PWM
switching off until the LDO has reached 90 % of the final
value. This prevents overloading the current-limited LDO
output during the LDO start-up.
Vishay Siliconix
Switchover
control
Switchover
MOSFET
VOUT
LDO
Due to the initial current limitations on the LDO during power
up (Fig. 33), any external load attached to the VDD pin must
be limited to less than the start up current before the LDO
has reached 90 % of its final regulation value.
Parastic diode
VDD
Fig. 34 - Switch-over MOSFET Parasitic Diodes
Design Procedure
When designing a switch mode supply the input voltage
range, load current, switching frequency, and inductor ripple
current must be specified.
Fig. 33 - LDO Start-Up
LDO Switch-Over Operation
The SiC402A/B includes a switch-over function for the LDO.
The switch-over function is designed to increase efficiency
by using the more efficient DC/DC converter to power the
LDO output, avoiding the less efficient LDO regulator when
possible. The switch-over function connects the VDD pin
directly to the VOUT pin using an internal switch. When the
switch-over is complete the LDO is turned off, which results
in a power savings and maximizes efficiency. If the LDO
output is used to bias the SiC402A/B, then after switch-over
the device is self-powered from the switching regulator with
the LDO turned off.
The switch-over starts 32 switching cycles after PGOOD
output goes high. The voltages at the VDD and VOUT pins are
then compared; if the two voltages are within ± 300 mV of
each other, the VDD pin connects to the VOUT pin using an
internal switch, and the LDO is turned off. To avoid
unwanted switch-over, the minimum difference between the
voltages for VOUT and VDD should be ± 500 mV.
It is not recommended to use the switch-over feature for an
output voltage less than VDD UVLO threshold since the
SiC402A/B is not operational below that threshold.
Switch-over MOSFET Parasitic Diodes
The switch-over MOSFET contains parasitic diodes that are
inherent to its construction, as shown in Fig. 34. If the
voltage at the VOUT pin is higher than VDD, then the
respective diode will turn on and the current will flow
through this diode. This has the potential of damaging the
device. Therefore, VOUT must be less than VDD to prevent
damaging the device.
The maximum input voltage (VIN max.) is the highest specified
input voltage. The minimum input voltage (VINmin.) is
determined by the lowest input voltage after evaluating the
voltage drops due to connectors, fuses, switches, and PCB
traces.
The following parameters define the design.
• Nominal output voltage (VOUT)
• Static or DC output tolerance
• Transient response
• Maximum load current (IOUT)
There are two values of load current to evaluate - continuous
load current and peak load current. Continuous load current
relates to thermal stresses which drive the selection
of the inductor and input capacitors. Peak load current
determines instantaneous component stresses and
filtering requirements such as inductor saturation, output
capacitors, and design of the current limit circuit.
The following values are used in this design.
VIN = 12 V ± 10 %
VOUT = 1.5 V ± 4 %
fSW = 300 kHz
Load = 10 A maximum
Frequency Selection
Selection of the switching frequency requires making a
trade-off between the size and cost of the external filter
components (inductor and output capacitor) and the power
conversion efficiency.
The desired switching frequency is 300 kHz which results
from using components selected for optimum size and cost.
A resistor (RtON) is used to program the on-time (indirectly
setting the frequency) using the following equation.
Rton =
S20-0483-Rev. D, 29-Jun-2020
k
25 pF x fsw
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To select RtON, use the maximum value for VIN, and for tON
use the value associated with maximum VIN.
tON =
VOUT
VINMAX. x fSW
Substituting for RtON results in the following solution.
RtON = 133.3 k, use RtON = 130 k
Inductor Selection
In order to determine the inductance, the ripple current must
first be defined. Low inductor values result in smaller size
but create higher ripple current which can reduce efficiency.
Higher inductor values will reduce the ripple current/voltage
and for a given DC resistance are more efficient. However,
larger inductance translates directly into larger packages
and higher cost. Cost, size, output ripple, and efficiency are
all used in the selection process.
The ripple current will also set the boundary for PSAVE
operation. The switching will typically enter PSAVE mode
when the load current decreases to 1/2 of the ripple current.
For example, if ripple current is 4 A then PSAVE operation will
typically start for loads less than 2 A. If ripple current is set
at 40 % of maximum load current, then PSAVE will start for
loads less than 20 % of maximum current.
The inductor value is typically selected to provide a ripple
current that is between 25 % to 50 % of the maximum load
current. This provides an optimal trade-off between cost,
efficiency, and transient performance.
During the on-time, voltage across the inductor is
(VIN - VOUT). The equation for determining inductance is
shown next.
L=
Capacitor Selection
The output capacitors are chosen based upon required
ESR and capacitance. The maximum ESR requirement is
controlled by the output ripple requirement and the DC
tolerance. The output voltage has a DC value that is equal to
the valley of the output ripple plus 1/2 of the peak-to-peak
ripple. A change in the output ripple voltage will lead to a
change in DC voltage at the output.
The design goal for output voltage ripple is 3 % of 1.5 V or
45 mV. The maximum ESR value allowed is shown by the
following equations.
ESRMAX =
VRIPPLE
IRIPPLEMAX
=
45 mV
4.43 A
ESRMAX = 10.2 mΩ
The output capacitance is usually chosen to meet transient
requirements. A worst-case load release, from maximum
load to no load at the exact moment when inductor current
is at the peak, determines the required capacitance. If the
load release is instantaneous (load changes from maximum
to zero in < 1 μs), the output capacitor must absorb all the
inductor's stored energy. This will cause a peak voltage on
the capacitor according to the following equation.
1
xI
)2
2 RIPPLEMAX
(VPEAK)2 - (VOUT)2
L (IOUT +
COUT_MIN =
Assuming a peak voltage VPEAK of 1.65 V (150 mV rise
upon load release), and a 10 A load release, the required
capacitance is shown by the next equation.
1
x 4.43)2
2
2
(1.65) - (1.5)2
1 µH (10 +
(VIN - VOUT) x tON
IRIPPLE
COUT_MIN =
COUT_MIN = 316 µF
Example
In this example, the inductor ripple current is set equal
to 45 % of the maximum load current. Therefore ripple
current will be 45 % x 10 A or 4.5 A. To find the minimum
inductance needed, use the VIN and tON values that
correspond to VIN max..
L=
(13.2 - 1.5) x 379 ns
= 0.99 µH
4.5 A
A slightly larger value of 1 μH is selected. This will decrease
the maximum IRIPPLE to 4.43 A.
Note that the inductor must be rated for the maximum DC
load current plus 1/2 of the ripple current.
The ripple current under minimum VIN conditions is also
checked using the following equations.
25 pF x RTON x VOUT
= 451 ns
TON_VINMIN =
VINMIN
IRIPPLE =
(VIN - VOUT) x tON
L
(10.8 - 1.5) x 451 ns
IRIPPLE_VINMIN =
1 µH
S20-0483-Rev. D, 29-Jun-2020
= 4.19 A
During the load release time, the voltage cross the inductor
is approximately - VOUT. This causes a down-slope or falling
dI/dt in the inductor. If the load dI/dt is not much faster than
the dI/dt of the inductor, then the inductor current will tend
to track the falling load current. This will reduce the excess
inductive energy that must be absorbed by the output
capacitor; therefore a smaller capacitance can be used.
The following can be used to calculate the needed
capacitance for a given dILOAD/dt.
Peak inductor current is shown by the next equation.
ILPK = Imax. + 1/2 x IRIPPLE max.
ILPK = 10 + 1/2 x 4.43 = 12.215 A
Rate of change of Load Current =
dILOAD
dt
Imax. = maximum load release = 10 A
COUT = ILPK x
I
I
L x LPK - MAX x dt
VOUT dlLOAD
2 (VPK - VOUT)
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Example
dlLOAD 2.5 A
=
1 µs
dt
This would cause the output current to move from 10 A
to 0 A in 4 μs, giving the minimum output capacitance
requirement shown in the following equation.
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking
stability is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and ringing.
Ringing for more than one cycle after the initial step is an
indication that the ESR should be increased.
ESR Requirements
12.215 10
x 1 µs
2.5
1.5
2 (1.65 - 1.5)
1 µH x
COUT = 12.215 x
COUT = 169 µF
Note that COUT is much smaller in this example, 169 μF
compared to 316 μF based on a worst-case load release. To
meet the two design criteria of minimum 316 μF and
maximum 10.2 m ESR, select one capacitor of 330 μF and
9 m ESR.
Stability Considerations
Unstable operation is possible with adaptive on-time
controllers, and usually takes the form of double-pulsing or
ESR loop instability.
Double-pulsing occurs due to switching noise seen at the
FB input or because the FB ripple voltage is too low. This
causes the FB comparator to trigger prematurely after the
250 ns minimum off-time has expired. In extreme cases the
noise can cause three or more successive on-times.
Double-pulsing will result in higher ripple voltage at the
output, but in most applications it will not affect operation.
This form of instability can usually be avoided by providing
the FB pin with a smooth, clean ripple signal that is at least
10 mVp-p, which may dictate the need to increase the ESR
of the output capacitors. It is also imperative to provide a
proper PCB layout as discussed in the Layout Guidelines
section.
Another way to eliminate doubling-pulsing is to add a small
(~10 pF) capacitor across the upper feedback resistor, as
shown in Fig. 35. This capacitor should be left unpopulated
until it can be confirmed that double-pulsing exists. Adding
the CTOP capacitor will couple more ripple into FB to help
eliminate the problem. An optional connection on the PCB
should be available for this capacitor.
A minimum ESR is required for two reasons. One reason
is to generate enough output ripple voltage to provide
10 mVp-p at the FB pin (after the resistor divider) to avoid
double-pulsing.
The second reason is to prevent instability due to insufficient
ESR. The on-time control regulates the valley of the output
ripple voltage. This ripple voltage is the sum of the two
voltages. One is the ripple generated by the ESR, the other
is the ripple due to capacitive charging and discharging
during the switching cycle. For most applications the
minimum ESR ripple voltage is dominated by the output
capacitors, typically SP or POSCAP devices. For stability
the ESR zero of the output capacitor should be lower than
approximately one-third the switching frequency. The
formula for minimum ESR is shown by the following
equation.
ESRMIN =
3
2 x π x COUT x fSW
Using Ceramic Output Capacitors
When the system is using high ESR value capacitors, the
feedback voltage ripple lags the phase node voltage by 90°.
Therefore, the converter is easily stabilized. When the
system is using ceramic output capacitors, the ESR value is
normally too small to meet the above ESR criteria. As a
result, the feedback voltage ripple is 180° from the phase
node and behaves in an unstable manner. In this application
it is necessary to add a small virtual ESR network that is
composed of two capacitors and one resistor, as shown in
Fig. 36.
CTOP
VOUT
To FB pin
R1
R2
Fig. 36 - Virtual ESR Ramp Circuit
The ripple voltage at FB is a superposition of two voltage
sources: the voltage across CL and output ripple voltage.
Fig. 35 - Capacitor Coupling to FB Pin
ESR loop instability is caused by insufficient ESR. The
S20-0483-Rev. D, 29-Jun-2020
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They are defined in the following equations.
VCL =
IL x DCR (s x L/DCR + 1)
S x RLCL + 1
ΔVOUT =
ΔIL
8C x fSW
Fig. 37 shows the magnitude of the ripple contribution due
to CL at the FB pin.
Fig. 39 - FB Voltage in Phasor Diagram
Fig. 37 - FB Voltage by CL Voltage
It is shown by the following equation.
VFBCL = VCL x
(R1//R2) x S x CC
(R1//R2) x S x CC + 1
Fig. 38 shows the magnitude of the ripple contribution due
to the output voltage ripple at the FB pin.
The magnitude of the feedback ripple voltage, which
is dominated by the contribution from CL, is controlled
by the value of R1, R2 and CC. If the corner frequency of
(R1//R2) x CC is too high, the ripple magnitude at the FB pin
will be smaller, which can lead to double-pulsing.
Conversely, if the corner frequency of (R1//R2) x CC is too
low, the ripple magnitude at FB pin will be higher. Since
the SiC402A/B regulates to the valley of the ripple voltage
at the FB pin, a high ripple magnitude is undesirable as
it significantly impacts the output voltage regulation.
As a result, it is desirable to select a corner frequency for
(R1//R2) x CC to achieve enough, but not excessive, ripple
magnitude and phase margin. The component values for
R1, R2, and CC should be calculated using the following
procedure.
Select CL (typical 10 nF) and RL to match with L and DCR
time constant using the following equation.
RL =
L
DCR x CL
Select CC by using the following equation.
CC ≈
1
3
x
R1//R2 2 x π x fsw
The resistor values (R1 and R2) in the voltage divider circuit
set the VOUT for the switcher. The typical value for CC is from
10 pF to 1 nF.
Dropout Performance
Fig. 38 - FB Voltage by Output Voltage
It is shown by the following equation.
VFBΔVOUT = ΔVOUT x
R2
R1//
1
+ R2
S x CC
It is recommended that R2 be set to 1k.
The purpose of this network is to couple the inductor current
ripple information into the feedback voltage such that the
feedback voltage has 90° phase lag to the switching node
similar to the case of using standard high ESR capacitors.
This is illustrated in Fig. 39.
S20-0483-Rev. D, 29-Jun-2020
The output voltage adjustment range for continuous
conduction operation is limited by the fixed 250 ns (typical)
minimum off-time of the one-shot. When working with low
input voltages, the duty-factor limit must be calculated using
worst-case values for on- and off-times.
The duty-factor limitation is shown by the next equation.
DUTY =
TON(MIN)
TON(MIN) x TOFF(MAX)
The inductor resistance and MOSFET on-state voltage
drops must be included when performing worst-case
dropout duty-factor calculations.
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System DC Accuracy (VOUT Controller)
HIGH OUTPUT VOLTAGE OPERATION
Three factors affect VOUT accuracy: the trip point of the FB
error comparator, the ripple voltage variation with line and
load, and the external resistor tolerance. The error
comparator offset is trimmed so that under static conditions
it trips when the feedback pin is 600 mV, 1 %.
For the SiC40X family the recommended maximum output
voltage of no more than 75 % of VIN.
The on-time pulse from the SiC402A/B in the design
example is calculated to give a pseudo-fixed frequency of
300 kHz. Some frequency variation with line and load is
expected. This variation changes the output ripple voltage.
Because adaptive on-time converters regulate to the valley
of the output ripple, ½ of the output ripple appears as a DC
regulation error. For example, if the output ripple is 50 mV
with VIN = 6 V, then the measured DC output will be 25 mV
above the comparator trip point. If the ripple increases to
80 mV with VIN = 25 V, then the measured DC output will be
40 mV above the comparator trip. The best way to minimize
this effect is to minimize the output ripple.
For applications where an output voltage greater than 5 V is
required a resistive network should be used to step down the
output voltage in order to provide the VOUT_PIN with 4.5 V.
R1 =
The switching frequency will also need recalculating using a
VOUT_PIN magnitude of 4.5 V.
fsw =
The output inductor value may change with current. This will
change the output ripple and therefore will have a minor
effect on the DC output voltage. The output ESR also affects
the output ripple and thus has a minor effect on the DC
output voltage.
The switching frequency varies with load current as a result
of the power losses in the MOSFETs and DCR of the
inductor. For a conventional PWM constant-frequency
converter, as load increases the duty cycle also increases
slightly to compensate for IR and switching losses in the
MOSFETs and inductor. An adaptive on-time converter
must also compensate for the same losses by increasing the
effective duty cycle (more time is spent drawing energy from
VIN as losses increase). The on-time is essentially constant
for a given VOUT/VIN combination, to offset the losses the
off-time will tend to reduce slightly as load increases. The
net effect is that switching frequency increases slightly with
increasing load.
S20-0483-Rev. D, 29-Jun-2020
VOUT_PIN
For example, if an output voltage of VOUT = 8.5 V is required,
setting R2 = 10 k and VOUT_PIN = 4.5 V results in R1 = 8870
The use of 1 % feedback resistors may result in up to
1 % error. If tighter DC accuracy is required, 0.1 % resistors
should be used.
Switching Frequency Variation
R2 (VOUT - VOUT_PIN)
VOUT_PIN
tON x VIN
LX
SiC40X
Vout
R1
VOUT_PIN
Cout
R2
Fig. 40 - Resistor Divider Network allows 4.5 V at the VOUT Pin
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LAYOUT CONSIDERATIONS
The SiC40x family of footprint compatible 15 A, 10 A, and
6 A products offers the designer a scalable buck regulator
solution. If the below layout recommendations are followed,
the same layout can be used to cover a wide range of output
currents and voltages without any changes to the board
design and only minor changes to the component values in
the schematic.
The reference design has a majority of the components
placed on the top layer. This allows for easy assembly and
straightforward layout.
Fig. 41 outlines the pointers for the layout considerations
and the explanations follow.
2
7
SiC40X
8. PGND can be used on internal layers if the resistance of
the PCB is to be small; this will also help remove heat.
Use extra vias if needed but be mindful to allow a path
between the vias.
6
LX
VOUT
3
10
4
11
5
8
Fig. 41 - Reference Design Pointers
1. Place input ceramic capacitors close to the voltage input
pins with a small 10 nF/100 nF placed as close as the
design rules will allow. This will help reduce the size of
the input high frequency current loop and consequently
reduce the high frequency ripple noise seen at the input
and the LX node.
2. Place the setup and control passive devices logically
around the IC with the intention of placing a quiet ground
plane beneath them on a secondary layer.
S20-0483-Rev. D, 29-Jun-2020
5. The output impedance should be small when high
current is required; use high current traces, multiple
layers can be used with many vias.
7. If a voltage injection network is needed then place it near
to the inductor LX node.
1
0V
4. The loop between LX, VOUT and the IC GND should be as
compact as possible. This will lower series resistance
and also make the current loop smaller enabling the high
frequency response of the output capacitors to take
effect.
6. Use many vias when multiple layers are involved. This
will have the effect of lowering the resistance between
layers and reducing the via inductance of the PCB nets.
9
VIN
3. It is advisable to use ceramic capacitors at the output to
reduce impedance. Place these as close to the IC PGND
and output voltage node as design will allow. Place a
small 10 nF/100 nF ceramic capacitor closest to the IC
and inductor loop.
9. A quiet plane should be employed for the AGND, this is
placed under the small signal passives. This can be
placed on multiple layers if needed for heat removal. This
should be connected to the PGND plane near to the input
GND at one connection only of at least 1 mm width.
10. The LX copper can also be used on multiple layers, use
a number of vias.
11. The copper area beneath the inductor has been removed
(on all layers) in this design to reduce the inductive
coupling that occurs between the inductor and the GND
trace. No other voltage planes should be placed under
this area.
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PCB LAYOUT
Fig. 42 - Top Layer
Fig. 44 - Inner Layer 2
Fig. 43 - Inner Layer 1
Fig. 45 - Bottom Layer
S20-0483-Rev. D, 29-Jun-2020
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SCHEMATIC
Note
• If OUT voltage setting 5 VDC, please change R10 and R11 value based on “High Output Voltage Operation” formula calculation
S20-0483-Rev. D, 29-Jun-2020
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BILL OF MATERIALS (VIN = 12 V, VOUT = 1.5 V, fsw = 500 kHz)
ITEM
QTY
REFERENCE
PCB
FOOTPRINT
VALUE
VOLTAGE
PART NUMBER
MANUFACTURER
1
2
C1, C2
1206
Omit
35 V
C3216X5R1V226M160AC
TDK
2
2
C3, C4
1206
22 μF
35 V
C3216X5R1V226M160AC
TDK
3
3
C5, C9, C12
0402
10 nF
50 V
GRM155R71H103KA88D
Murata
4
1
C6
0402
2.2 μF
10 V
C0402C225M8PACTU
Kemet
5
2
C7, C10
0402
2.2 nF
50 V
GRM155R71H222KA01D
Murata
6
1
C8
0402
100 nF
35 V
CGA2B3X7R1V104K050BB
Vishay
7
3
C13, C14, C15
1206
47 μF
10 V
GRM31CR61A476ME15L
Murata
8
5
C16, C17, C18, C19, C20
1206
Omit
10 V
GRM31CR61A476ME15L
Murata
9
2
C21, C22
7343
Omit
-
-
-
10
4
P1, P3, P9, P10
Banana Jack
-
-
575-4K-ND
Keystone
11
5
P2, P4, P5, P7, P8
Header-2
-
-
826926-2
AMP (TE)
12
1
P6
Header-3
-
-
HTSW-103-08-T-S
Samtec
13
1
L1
IHLP4040
1 μH
-
IHLP4040DZER1R0
Vishay
14
1
R1
0402
249K
-
CRCW0402249KFKED
Vishay
15
1
R2
0402
100K
-
CRCW0402100KFKED
Vishay
16
1
R3
0402
169K
-
CRCW0402169KFKED
Vishay
17
1
R4
0402
30K
-
CRCW040230K0FKED
Vishay
18
1
R5
0402
5K11
-
CRCW04025K11FKED
Vishay
19
1
R6
0402
76K8
-
CRCW040276K8FKED
Vishay
20
1
R7
0402
10R
-
CRCW040210R0FKEA
Vishay
21
1
R8
0402
10K
-
CRCW040210K0FKED
Vishay
22
1
R9
0805
Omit
-
-
Vishay
23
1
R10
0402
0R
-
CRCW04020000Z0ED
Vishay
24
1
R11
0402
Omit
-
-
Vishay
25
1
R12
0402
1K54
-
CRCW04021K54FKED
Vishay
26
1
R13
0402
1K
-
CRCW0402249KFKED
Vishay
27
1
R14
0402
10R
-
CRCW040210R0FKEA
Vishay
28
1
R15
0402
10K
-
CRCW040210K0FKED
Vishay
29
1
U1
MLP55-33
SIC402
-
-
-
S20-0483-Rev. D, 29-Jun-2020
Document Number: 63729
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PRODUCT SUMMARY
Part number
SiC402A
SiC402B
Description
10 A, 3 V to 28 V input, scalable synchronous
buck regulator, ultrasonic mode
10 A, 3 V to 28 V input, scalable synchronous
buck regulator, powersave mode
Input voltage min. (V)
3
3
Input voltage max. (V)
28
28
Output voltage min. (V)
0.6
0.6
Output voltage max. (V)
5.5
5.5
Continuous current (A)
10
10
Switch frequency min. (kHz)
200
200
Switch frequency max. (kHz)
1000
1000
Pre-bias operation (yes / no)
Yes
Yes
Internal bias reg. (yes / no)
Yes
Yes
Not required
Not required
Compensation
Enable (yes / no)
Yes
Yes
PGOOD (yes / no)
Yes
Yes
Overcurrent protection
Protection
Light load mode
Peak efficiency (%)
Package type
Package size (W, L, H) (mm)
Programmable
Programmable
OVP, OCP, UVP/SCP, OTP, UVLO
OVP, OCP, UVP/SCP, OTP, UVLO
Ultrasonic
Powersave
95
95
PowerPAK MLP32-55G
PowerPAK MLP32-55G
5.0 x 5.0 x 0.85
5.0 x 5.0 x 0.85
Status code
2
2
Product type
microBUCK (step down regulator)
microBUCK (step down regulator)
Applications
Computing, consumer, networking, industrial, Computing, consumer, networking, industrial,
healthcare
healthcare
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?63729.
S20-0483-Rev. D, 29-Jun-2020
Document Number: 63729
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Package Information
Vishay Siliconix
PowerPAK® MLP55-32L CASE OUTLINE
0.08 C
A
A1
D
A2
25
1
4
(5 mm x 5 mm)
Pin #1 identification
R0.200
E2 - 3
0.10
E
32L T/SLP
D2 - 2
32
24
E2 - 1
CAB
e
0.10 CB
D2 - 1
0.360
8
17
B
b
16
L
C
0.36
Top View
(Nd-1) Xe
Ref.
0.10 CA
A
E2 - 2
2x
0.45
5 6
Pin 1 dot
by marking
2x
Side View
D2 - 3
D2 - 4
(Nd-1) Xe
Ref.
D4
9
Bottom View
MILLIMETERS
INCHES
DIM
MIN.
NOM.
MAX.
MIN.
NOM.
A
0.80
0.85
0.90
0.031
0.033
0.035
A1(8)
0.00
-
0.05
0.000
-
0.002
0.30
0.078
A2
b(4)
0.20 REF.
0.20
0.25
0.008 REF.
0.098
D
5.00 BSC
0.196 BSC
e
0.50 BSC
0.019 BSC
E
5.00 BSC
L
0.35
0.40
MAX.
0.011
0.196 BSC
0.45
0.013
0.015
N(3)
32
32
Nd(3)
8
8
Ne(3)
8
0.017
8
D2 - 1
3.43
3.48
3.53
0.135
0.137
0.139
D2 - 2
1.00
1.05
1.10
0.039
0.041
0.043
D2 - 3
1.00
1.05
1.10
0.039
0.041
0.043
D2 - 4
1.92
1.97
2.02
0.075
0.077
0.079
E2 - 1
3.43
3.48
3.53
0.135
0.137
0.139
E2 - 2
1.61
1.66
1.71
0.063
0.065
0.067
E2 - 3
1.43
1.48
1.53
0.056
0.058
0.060
ECN: T-08957-Rev. A, 29-Dec-08
DWG: 5983
Notes
1. Use millimeters as the primary measurement.
2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994.
3. N is the number of terminals.
Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction.
4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip.
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body.
6. Exact shape and size of this feature is optional.
7. Package warpage max. 0.08 mm.
8. Applied only for terminals.
Document Number: 64714
Revision: 29-Dec-08
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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
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Statements regarding the suitability of products for certain types of applications are based on Vishay's knowledge of typical
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements
about the suitability of products for a particular application. It is the customer's responsibility to validate that a particular product
with the properties described in the product specification is suitable for use in a particular application. Parameters provided in
datasheets and / or specifications may vary in different applications and performance may vary over time. All operating
parameters, including typical parameters, must be validated for each customer application by the customer's technical experts.
Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited
to the warranty expressed therein.
Hyperlinks included in this datasheet may direct users to third-party websites. These links are provided as a convenience and
for informational purposes only. Inclusion of these hyperlinks does not constitute an endorsement or an approval by Vishay of
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Vishay disclaims any and all liability and bears no responsibility for the accuracy, legality or content of the third-party website
or for that of subsequent links.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please
contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.
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© 2022 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 01-Jan-2022
1
Document Number: 91000
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