SiC403
Vishay Siliconix
microBUCK® SiC403
6 A, 28 V Integrated Buck Regulator with Programmable LDO
DESCRIPTION
FEATURES
The Vishay Siliconix SiC403 is an advanced stand-alone
synchronous buck regulator featuring integrated power
MOSFETs, bootstrap switch, and a programmable LDO in a
space-saving MLPQ 5 x 5 - 32 pin package.
The SiC403 is capable of operating with all ceramic solutions
and switching frequencies up to 1 MHz. The programmable
frequency, synchronous operation and selectable
power-save allow operation at high efficiency across the full
range of load current. The internal LDO may be used to
supply 5 V for the gate drive circuits or it may be bypassed
with an external 5 V for optimum efficiency and used to drive
external n-channel MOSFETs or other loads. Additional
features include cycle-by-cycle current limit, voltage
soft-start,
under-voltage
protection,
programmable
over-current protection, soft shutdown and selectable
power-save. The Vishay Siliconix SiC403 also provides an
enable input and a power good output.
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High efficiency > 95 %
6 A continuous output current capability
Integrated bootstrap switch
Programmable 200 mA LDO with bypass logic
Temperature compensated current limit
Pseudo fixed-frequency adaptive on-time control
All ceramic solution enabled
Programmable input UVLO threshold
Independent enable pin for switcher and LDO
Selectable ultra-sonic power-save mode
Programmable soft-start
Soft-shutdown
1 % internal reference voltage
Power good output
Under and over voltage protection
Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
PRODUCT SUMMARY
Input Voltage Range
3 V to 28 V
APPLICATIONS
Output Voltage Range
0.75 V to 5.5 V
Operating Frequency
200 kHz to 1 MHz
Continuous Output Current
•
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6A
Peak Efficiency
95 % at 300 kHz
Package
MLPQ 5 mm x 5 mm
Notebook, desktop, and server computers
Digital HDTV and digital consumer applications
Networking and telecommunication equipment
Printers, DSL, and STB applications
Embedded applications
Point of load power supplies
TYPICAL APPLICATION CIRCUIT
3.3 V
EN/PSV (Tri-State)
PGOOD
LX
ILIM
PGOOD
LX
AGND
TON
ENL
EN\PSV
LDO_EN
VOUT
32 31 30 29 28 27 26 25
FB
VOUT
VDD
AGND
FBL
VIN
VIN
24
1
PAD 1
2
23
AGND
3
22
PAD 3
4
5
LX
PAD 2
6
SS 7
BST
21
20
19
VIN
VOUT
LX
PGND
PGND
PGND
PGND
18
PGND
17
PGND
16
NC 14
PGND
15
PGND
13
NC 12
LX
10
11
VIN
VIN
VIN
9
8
LX
SiC403 (MLP 5 x 5-32L)
Document Number: 66550
S12-0628-Rev. C, 19-Mar-12
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SiC403
Vishay Siliconix
LX
ILIM
PGOOD
EN\PSV
LX
TON
AGND
ENL
PIN CONFIGURATION (TOP VIEW)
32 31 30 29 28 27 26 25
FBL
5
VIN
6
7
BST
8
PAD 3
LX
PAD 2
LX
LX
22
PGND
21
PGND
20
PGND
19 PGND
VIN
18 PGND
17 PGND
VIN
9
SS
AGND
24
23
PGND 16
4
NC 14
3
PGND 15
VDD
AGND
PAD 1
LX 13
2
NC 12
VOUT
VIN 11
1
VIN 10
FB
PIN DESCRIPTION
Pin Number
Symbol
1
FB
2
VOUT
3
VDD
4, 30, PAD 1
AGND
5
FBL
6, 9-11, PAD 2
VIN
Description
Feedback input for switching regulator. Connect to an external resistor divider from output to program
output voltage.
Output voltage input to the controller. Additionally may be used to by pass LDO to supply VDD directly.
Bias for internal logic circuitry and gate drivers. Connect to external 5V power supply or configure
the internal LDO for 5 V.
Analog ground
Feedback input for internal LDO. Connect to an external resistor divider from VDD to AGND to program
LDO output.
Power stage input (HS FET Drain)
Connect to an external capacitor to AGND to program softstart ramp
7
SS
8
BST
Bootstrap pin. A capacitor is connected between BST and LX to provide HS driver voltage.
Not internally connected
12
NC
13, 23-25, 28, PAD 3
LX
Switching node (HS FET Source and LS FET Drain)
14
NC
Not internally connected
15-22
PGND
26
PGOOD
27
ILIM
29
EN/PSV
Power ground (LS FET Source)
Open-drain power good indicator. Externally pull-up resistor is required.
31
TON
Connect to an external resistor between ILIM and LX to program over current limit
Tri-state pin. Pull low to AGND to disable the regulator. Float to enable forced continuous current
mode. Pull high to VDD to enable power save mode.
Connect to an external resistor to AGND program on-time
32
ENL
Enable input for internal LDO. Pull down to AGND to disable internal LDO.
ORDERING INFORMATION
Part Number
SiC403CD-T1-GE3
SiC403DB
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Package
MLPQ55-32
Evaluation board
For technical support, please contact: analogswitchtechsupport@vishay.com
Document Number: 66550
S12-0628-Rev. C, 19-Mar-12
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SiC403
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM
AGND
VDD
6, 9-11, PAD 2
29
26
PGOOD
EN/PSV
VIN
4, 30,
PAD 1
VIN
VDD
Reference
BST
8
Control and Status
DL
SS
7
Soft Start
+
FB
On-Time
Generator
-
1
LX
13, 23 to 25,
28, PAD 3
Gate Drive
Control
VDD
FB Comparator
TON
PGND
31
15 to 22
Zero Cross
Detector
VOUT
2
VDD
VDD
3
Y
ILIM
Valley1-Limit
Bypass Comparator
27
VIN
A
B
MUX
LDO
5
FBL
32
ENL
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Symbol
Min.
Max.
LX to PGND Voltage
VLX
- 0.3
+ 30
LX to PGND Voltage (transient - 100 ns)
VLX
-2
+ 30
VIN to PGND Voltage
VIN
- 0.3
+ 30
EN/PSV, PGOOD, ILIM, to AGND
- 0.3
VDD + 0.3
BST Bootstrap to LX; VDD to PGND
- 0.3
+6
- 0.3
+ 0.3
EN/PSV, PGOOD, ILIM, VOUT, VLDO, FB, FBL to GND
- 0.3
+ (VDD + 0.3)
tON to PGND
- 0.3
+ (VDD - 1.5)
BST to PGND
- 0.3
+ 35
AGND to PGND
VAG-PG
Unit
V
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min.
VIN
3
Input Voltage
Typ.
Max.
Unit
28
VDD to PGND
VDD
3
5.5
VOUT to PGND
VOUT
0.75
5.5
V
Note:
For proper operation, the device should be used within the recommended conditions.
THERMAL RESISTANCE RATINGS
Parameter
Storage Temperature
Symbol
Min.
TSTG
- 40
Typ.
Max.
Unit
+ 150
Maximum Junction Temperature
TJ
-
150
Operation Junction Temperature
TJ
- 25
+ 125
°C
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SiC403
Vishay Siliconix
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Min.
Thermal Resistance, Junction-to-Ambientb
High-Side MOSFET
Low-Side MOSFET
PWM Controller and LDO Thermal Resistance
Typ.
Max.
Unit
25
20
50
°C/W
Peak IR Reflow Temperature
TReflow
260
°C
Notes:
a. This device is ESD sensitive. Use of standard ESD handling precautions is required.
b. Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters
specififed in the Electrical Characteristics section is not recommended.
ELECTRICAL SPECIFICATIONS
Parameter
Symbol
Test Conditions Unless Specified
VIN = 12 V, VDD = 5 V, TA = + 25 °C for typ.,
- 40 °C to + 85 °C for min. and max.,
TJ = < 125 °C
Min.
Typ.
Max.
Unit
Input Supplies
VIN UVLO Threshold Voltagea
VIN UVLO Hysteresis
VDD UVLO Threshold Voltage
VDD UVLO Hysteresis
VIN_UV+
Sensed at ENL pin, rising edge
2.4
2.6
2.95
VIN_UV-
Sensed at ENL pin, falling edge
2.235
2.4
2.565
VIN_UV_HY
EN/PSV = High
VDD_UV+
Measured at VDD pin, rising edge
2.5
0.2
VDD_UV-
Measured at VDD pin, falling edge
2.4
VDD_UV_HY
VIN Supply Current
IIN
VDD Supply Current
IVDD
2.8
3
2.6
2.9
V
0.2
EN/PSV, ENL = 0 V, VIN = 28 V
8.5
Standby mode:
ENL = VDD, EN/PSV = 0 V
130
EN/PSV, ENL = 0 V
3
EN/PSV = VDD, no load (fSW = 25 kHz),
VFB > 750 mV
2
fSW = 250 kHz, EN/PSV = floating, no loadb
25°C bench testing
10
20
µA
7
mA
Controller
FB On-Time Threshold
VFB-TH
Static VIN and load, - 40 °C to + 85 °C
0.7425
Frequency Rangeb
FPWM
continuous mode, 25°C bench testing
200
Bootstrap Switch Resistance
0.750
0.7599
V
1000
kHz
10
Timing
On-Time
tON
Continuous mode operation VIN = 15 V,
VOUT = 5 V, Rton = 300 k
Minimum On-Timeb
tON
25°C bench testing
80
Minimum Off-Timeb
tOFF
25°C bench testing
320
ISS
IOUT = ILIM/2, 25°C bench testing
2.75
µA
500
k
2386
2650
2915
ns
Soft Start
Soft Start Currentb
Analog Inputs/Outputs
VOUT Input Resistance
RO-IN
Current Sense
VSense-th
LX-PGND
Power Good Threshold Voltage
PG_VTH_UPPER
VFB > internal reference 750 mV
+ 20
Power Good Threshold Voltage
PG_VTH_LOWER
VFB < internal reference 750 mV
- 10
Zero-Crossing Detector Threshold Voltage
- 3.5
0.5
+ 3.5
mV
Power Good
Start-Up Delay Time
PG_Td
Css = 10 nF
12
Fault (noise-immunity) Delay Timeb
PG_ICC
VEN = 0 V, 25°C bench testing
5
Power Good Leakage Current
PG_ILK
VEN = 0 V
PG_RDS-ON
VEN = 0 V
Power Good On-Resistance
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%
ms
µs
1
10
µA
Document Number: 66550
S12-0628-Rev. C, 19-Mar-12
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SiC403
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
Parameter
Symbol
Test Conditions Unless Specified
VIN = 12 V, VDD = 5 V, TA = + 25 °C for typ.,
- 40 °C to + 85 °C for min. and max.,
TJ = < 125 °C
Min.
Typ.
Max.
Unit
Fault Protection
ILIM Source Current
ILIM
8
RILIM = 6 kVDD = 5 V,
25°C bench testing
Valley Current Limit
4.5
6
Output Under-Voltage Fault
VOUV_Fault
VFB with respect to Internal 500 mV
reference, 8 consecutive clocks
- 25
Smart Power-Save Protection
Threshold Voltageb
PSAVE_VTH
VFB with respect to internal 500 mV
reference, 25°C bench testing
+ 10
VFB with respect to internal 500 mV
reference
+ 20
Over-Voltage Protection Threshold
Over-Voltage Fault Delayb
Over Temperature Shutdownb
µA
7.2
A
%
%
tOV-Delay
25°C bench testing
5
µs
TShut
10 °C hysteresis, 25°C bench testing
150
°C
Logic Inputs/Outputs
Logic Input High Voltage
VIH
Logic Input Low Voltage
VIL
EN, ENL, PSV
1
0.4
EN/PSV Input Bias Current
IEN
EN/PSV = VDD or AGND
ENL Input Bias Current
IENL
VIN = 28 V
FBL_ILK
FBL, FB = VDD or AGND
-1
VLDO load = 10 mA
0.735
FBL, FB Input Bias Current
- 10
V
+ 10
11
18
µA
+1
Linear Dropout Regulator
FBL Accuracy
LDO Current Limit
FBLACC
LDO_ILIM
Start-up and foldback, VIN = 12 V
Operating current limit, VIN = 12 V
0.750
0.765
115
134
mA
200
VLDO to VOUT Switch-Over Thresholdc
VLDO-BPS
- 130
+ 130
VLDO to VOUT Non-Switch-Over Thresholdc
VLDO-NBPS
- 500
+ 500
VLDO to VOUT Switch-Over Resistance
LDO Drop Out Voltaged
RLDO
V
mV
VOUT = 5 V
2
From VIN to VVLDO, VVLDO = + 5 V,
IVLDO = 100 mA
1.2
V
Notes:
a. VIN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference.
b. Guaranteed by design.
c. The switch-over threshold is the maximum voltage diff erential between the VLDO and VOUT pins which ensures that VLDO will internally
switch-over to VOUT. The non-switch-over threshold is the minimum voltage diff erential between the VLDO and VOUT pins which ensures that
VLDO will not switch-over to VOUT.
d. The LDO drop out voltage is the voltage at which the LDO output drops 2 % below the nominal regulation point.
Document Number: 66550 For technical support, please contact: analogswitchtechsupport@vishay.com
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S12-0628-Rev. C, 19-Mar-12
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SiC403
Vishay Siliconix
90
90
80
80
70
70
60
60
Efficiency (%)
Efficiency (%)
ELECTRICAL CHARACTERISTICS
50
40
50
40
30
30
20
20
VIN = 12 V, VOUT = 1 V, FSW = 500 kHz
VIN = 12 V, VOUT = 1 V, FSW = 500 kHz
10
10
0
0
0.01
0.1
1
0.01
10
0.1
1
Efficiency vs. IOUT
(in Continuous Conduction Mode)
Efficiency vs. IOUT
(in Power-Save-Mode)
1.006
1.008
1.004
1.006
1.004
1.002
VIN = 12 V, VOUT = 1 V, FSW = 500 kHz
1.002
1
VIN = 12 V, VOUT = 1 V, FSW = 500 kHz
VOUT (V)
VOUT (V)
10
IOUT (A)
IOUT (A)
0.998
1
0.998
0.996
0.996
0.994
0.994
0.992
0.992
0
1
2
3
4
IOUT (A)
5
6
7
0
1
2
VOUT vs. IOUT
(in Continuous Conduction Mode)
3
4
IOUT (A)
5
6
7
VOUT vs. IOUT
(in Power-Save-Mode)
1.05
1.012
1.04
1.010
1.03
1.02
1.006
VOUT (V)
VOUT (V)
1.008
1.004
VOUT = 1 V, FSW = 500 kHz,
Continuous Conduction Mode
1.002
1.01
1
0.99
VOUT = 1 V, FSW = 500 kHz,
Continuous Conduction Mode
0.98
0.97
1
0.96
0.95
0.998
5
7
9
11
13
15
17
19
21
23
VIN (V)
VOUT vs. VIN at IOUT = 0 A
(in Continuous Conduction Mode, FSW = 500 kHz)
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5
7
9
11
13
15
VIN (V)
17
19
21
23
VOUT vs. VIN at IOUT = 6 A
(in Continuous Conduction Mode, FSW = 500 kHz)
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Document Number: 66550
S12-0628-Rev. C, 19-Mar-12
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SiC403
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
40
1.1
35
30
VOUT Ripple (mV)
VOUT (V)
1.05
1
VOUT = 1 V, FSW = 500 kHz, Power Saving Mode
VOUT = 1 V, IOUT = 6 A, FSW = 500 kHz
25
20
15
10
0.95
5
0
0.9
6
8
10
12
14
16
18
20
22
0
24
5
10
15
VOUT vs. VIN
(IOUT = 0 A in Power-Save-Mode)
25
VOUT Ripple vs. VIN
(IOUT = 6 A in Continuous Conduction Mode)
35
40
30
35
30
20
VOUT Ripple (mV)
25
VOUT Ripple (mV)
20
VIN (V)
VIN (V)
VOUT =1 V, IOUT = 0 A, FSW = 500 kHz
15
VOUT = 1 V, IOUT = 0 A, FSW = 500 kHz
25
20
15
10
10
5
5
0
0
0
5
10
15
20
25
6
8
10
12
VIN (V)
14
16
18
20
VIN (V)
VOUT Ripple vs. VIN
(IOUT = 0 A in Continuous Conduction Mode)
VOUT Ripple vs. VIN
(IOUT = 0 A in Power-Save-Mode)
600
550
530
500
510
400
470
FSW (kHz)
FSW (kHz)
490
450
430
300
200
410
VIN = 12 V, VOUT = 1 V
390
100
VIN = 12 V, VOUT = 1 V
370
0
350
0
1
2
3
4
5
6
7
0
1
2
IOUT (A)
FSW vs. IOUT
(in Continuous Conduction Mode)
Document Number: 66550
S12-0628-Rev. C, 19-Mar-12
3
4
IOUT (A)
5
6
7
FSW vs. IOUT
(in Power-Save-Mode)
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SiC403
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
Ch2: Output ripple Voltage (20mV/div)
Ch1: LX Switching Node (5V/div)
Ch2: Output ripple Voltage (20mV/div)
Ch1: LX Switching Node (5V/div)
Time: 2 μs/div
Time: 20 μs/div
VOUT Ripple in Power Save Mode (No Load)
(VIN = 12 V, VOUT = 1 V)
Ch3: Output Current (2A/div)
Ch2: Output Voltage (50mV/div)
VOUT Ripple in Continuous Conduction Mode (No Load)
(VIN = 12 V, VOUT = 1 V, FSW = 500 kHz)
Ch3: Output Current (2A/div)
Ch2: Output Voltage (50mV/div)
Time: 5 μs/div
Time: 5 μs/div
Transient Response in Continuous Conduction Mode
(6 A to 0.2 A)
(VIN = 12 V, VOUT = 1 V, FSW = 500 kHz)
Ch3: Output Current (2A/div)
Ch2: Output Voltage (50mV/div)
Transient Response in Continuous Conduction Mode
(0.2 A to 6 A)
(VIN = 12 V, VOUT = 1 V, FSW = 500 kHz)
Ch3: Output Current (2A/div)
Ch2: Output Voltage (50mV/div)
Time: 10 μs/div
Transient Response in Power Save Mode
(6 A to 0.2 A)
(VIN = 12 V, VOUT = 1 V, FSW = 500 kHz at 6 A)
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Time: 10 μs/div
Transient Response in Power Save Mode
(0.2 A to 6 A)
(VIN = 12 V, VOUT = 1 V, FSW = 500 kHz at 6 A)
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Document Number: 66550
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SiC403
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
Ch4: Vin (5V/div)
Ch2: Vout (500mV/div)
Ch3: Power Good (5V/div)
Ch1: Switching Node (5V/div)
Ch4: Iout (10A/div)
Ch2: Vout (1V/div)
Ch3: Power good (5V/div)
Ch1: Switching Node (10V/div)
Time: 10 ms/div
Time: 10 ms/div
Start-up with VIN Ramping up
(VIN = 12 V, VOUT = 1 V, FSW = 500 kHz)
Over-Current Protection
(VIN = 12 V, VOUT = 1 V, FSW = 500 kHz )
100
Efficiency (%)
95
90
VIN = 12 V, VOUT = 5 V, FSW = 300 kHz
85
80
75
70
0
1
2
3
4
5
6
7
IOUT (A)
Efficiency with 12 VIN, 5 VOUT, 300 kHz
Document Number: 66550
S12-0628-Rev. C, 19-Mar-12
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SiC403
Vishay Siliconix
APPLICATIONS INFORMATION
SiC403 Synchronous Buck Converter
The SiC403 is a step down synchronous buck DC/DC
converter with integrated power FETs and programmable
LDO. The SiC403 is capable of 6 A operation at very high
efficiency in a tiny 5 mm x 5 mm - 32 pin package. The
programmable operating frequency range of 200 kHz to
1 MHz, enables the user to optimize the solution for minimum
board space and optimum efficiency.
The buck controller employs pseudo-fixed frequency
adaptive on-time control. This control scheme allows fast
transient response thereby lowering the size of the power
components used in the system.
tON
VIN
VLX
CIN
VFB
Q1
VLX
FB threshold
VOUT
L
ESR
Q2
FB
+
COUT
Input Voltage Range
The SiC403 requires two input supplies for normal operation:
VIN and VDD. VIN operates over the wide range from 3 V to
28 V. VDD requires a supply voltage between 3 V to 5 V that
can be an external source or the internal LDO configured
from VIN.
Power Up Sequence
The SIC403 initiates a start up when VIN, VDD, and EN/PSV
pins are above the applicable thresholds. When using an
external bias supply for the VDD voltage, it is recommended
that the VDD is applied to the device only after the VIN voltage
is present because VDD cannot exceed VIN at any time. A 10
resistor must be placed between the external VDD supply and
the VDD pin to avoid damage to the device during power-up
and or shutdown situations where VDD could exceed VIN
unexpectedly.
Shut-Down
The SIC403 can be shut-down by pulling either VDD or
EN/PSV pin below its threshold. When using an external
supply voltage for VDD, the VDD pin must be deactivated
while the VIN voltage is still present. A 10 resistor must be
placed between the external VDD supply and the VDD pin to
avoid damage to the device.
When the VDD pin is active and EN/PSV is at low logic level,
the output voltage discharges through an internal FET.
Pseudo-Fixed Frequency Adaptive On-Time Control
The PWM control method used for the SiC403 is
pseudo-fixed frequency, adaptive on-time, as shown in
figure 1. The ripple voltage generated at the output capacitor
ESR is used as a PWM ramp signal. This ripple is used to
trigger the on-time of the controller.
The adaptive on-time is determined by an internal oneshot
timer. When the one-shot is triggered by the output ripple, the
device sends a single on-time pulse to the highside
MOSFET. The pulse period is determined by VOUT and VIN;
the period is proportional to output voltage and inversely
proportional to input voltage. With this adaptive on-time
arrangement, the device automatically anticipates the
on-time needed to regulate VOUT for the present VIN
condition and at the selected frequency.
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Figure 1 - Output Ripple and PWM Control Method
The adaptive on-time control has significant advantages over
traditional control methods used in the controllers today.
• Reduced component count by eliminating DCR sense or
current sense resistor as no need of a sensing inductor
current.
• Reduced saves external components used for
compensation by eliminating the no error amplifier and
other components.
• Ultra fast transient response because of fast loop,
absence of error amplifier speeds up the transient
response.
• Predictable frequency spread because of constant on-time
architecture.
• Fast transient response enables operation with minimum
output capacitance
Overall, superior performance compared to fixed frequency
architectures.
On-Time One-Shot Generator (tON) and Operating
Frequency
The SiC403 have an internal on-time one-shot generator
which is a comparator that has two inputs. The FB
Comparator output goes high when VFB is less than the
internal 750 mV reference. This feeds into the gate drive and
turns on the high-side MOSFET, and also starts the one-shot
timer. The one-shot timer uses an internal comparator and a
capacitor. One comparator input is connected to VOUT, the
other input is connected to the capacitor. When the on-time
begins, the internal capacitor charges from zero volts
through a current which is proportional to VIN. When the
capacitor voltage reaches VOUT, the on-time is completed
and the high-side MOSFET turns off. The figure 2 shows the
on-chip implementation of on-time generation.
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SiC403
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Gate
drives
FB comparator
FB
750 mV
+
DH
Q1
VLX
One-shot
timer
DL
Q2
COUT
FB
+
On-time = K x Rton x (VOUT/VIN)
Figure 2 - On-Time Generation
This method automatically produces an on-time that is
proportional to VOUT and inversely proportional to VIN.
Under steady-state conditions, the switching frequency can
be determined from the on-time by the following equation.
fsw =
VOUT
tON x VIN
The SiC403 uses an external resistor to set the ontime
which indirectly sets the frequency. The on-time can be programmed to provide operating frequency from 200 kHz to 1
MHz using a resistor between the tON pin and ground. The
resistor value is selected by the following equation.
Rton =
(tON - 10 ns) x VIN
25 pF x VOUT
The maximum RtON value allowed is shown by the following
equation.
Rton_MAX =
VIN_MIN
15 µA
VOUT Voltage Selection
The switcher output voltage is regulated by comparing VOUT
as seen through a resistor divider at the FB pin to the internal
750 mV reference voltage, see figure 3.
VOUT
R1
R2
+
VOUT
L
ESR
VOUT
VIN
Rton
VOUT = 0.75 x 1 +
VRIPPLE
2
1 + (R1ωCTOP)2
x
1+
R 2 x R1
ωCTOP
R2 + R1
2
Enable and Power-Save Inputs
The EN/PSV and ENL inputs are used to enable or disable the switching regulator and the LDO.
When EN/PSV is low (grounded), the switching regulator is
off and in its lowest power state. When off, the output of the
switching regulator soft-discharges the output into a 15
internal resistor via the VOUT pin.
When EN/PSV is allowed to float, the pin voltage will float to
1.5 V. The switching regulator turns on with power-save
disabled and all switching is in forced continuous mode.
When EN/PSV is high (above 2 V), the switching regulator
turns on with ultra-sonic power-save enabled. The SiC403
ultra-sonic power-save operation maintains a minimum
switching frequency of 25 kHz, for applications with stringent
audio requirements.
The ENL input is used to control the internal LDO. This input
serves a second function by acting as a VIN UVLO sensor for
the switching regulator.
The LDO is off when ENL is low (grounded). When ENL is a
logic high but below the VIN UVLO threshold (2.6 V typical),
then the LDO is on and the switcher is off. When ENL is
above the VIN UVLO threshold, the LDO is enabled and the
switcher is also enabled if the EN/PSV pin is not grounded.
Forced Continuous Mode Operation
The SiC403 operates the switcher in Forced Continuous
Mode (FCM) by floating the EN/PSV pin (see figure 4). In this
mode one of the power MOSFETs is always on, with no
intentional dead time other than to avoid cross-conduction.
This feature results in uniform frequency across the full load
range with the trade-off being poor efficiency at light loads
due to the high-frequency switching of the MOSFETs.
FB ripple
voltage (VFB)
FB threshold
(750 mV)
to FB pin
R1
DC load current
Inductor
current
R2
On-time
(tON)
Figure 3 - Output Voltage Selection
As the control method regulates the valley of the output ripple
voltage, the DC output voltage VOUT is off set by the output
ripple according to the following equation.
DH on-time is triggered when
VFB reaches the FB threshold
DH
DL
VOUT = 0.75 x 1 +
R1
R2
+
VRIPPLE
2
When a large capacitor is placed in parallel with R1 (CTOP)
VOUT is shown by the following equation.
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DL drives high when on-time is completed.
DL remains high until VFB falls to the FB threshold.
Figure 4 - Forced Continuous Mode Operation
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SiC403
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Ultrasonic Power-Save Operation
The SiC403 provides ultra-sonic power-save operation at
light loads, with the minimum operating frequency fixed at
25 kHz. This is accomplished using an internal timer that
monitors the time between consecutive high-side gate
pulses.
If the time exceeds 40 µs, DL drives high to turn the low-side
MOSFET on. This draws current from VOUT through the
inductor, forcing both VOUT and VFB to fall. When VFB drops
to the 750 mV threshold, the next DH on-time is triggered.
After the on-time is completed the high-side MOSFET is
turned off and the low-side MOSFET turns on, the low-side
MOSFET remains on until the inductor current ramps down
to zero, at which point the low-side MOSFET is turned off.
minimum fSW ~ 25 kHz
FB ripple
voltage (VFB)
Figure 6 - Ultrasonic Power-Save Operation Mode
FB threshold
(750 mV)
(0A)
Inductor
current
On-time
(tON)
DH on-time is triggered when
VFB reaches the FB threshold
DH
DL
After the 40 µs time-out, DL drives high if VFB
has not reached the FB threshold.
Figure 5 - Ultrasonic power-save Operation
Because the on-times are forced to occur at intervals no
greater than 40 µs, the frequency will not fall below ~ 25 kHz.
Figure 5 shows ultra-sonic power-save operation.
Benefits of Ultrasonic Power-Save
Having a fixed minimum frequency in power-save has some
significant advantages as below:
• The minimum frequency of 25 kHz is outside the audible
range of human ear. This makes the operation of the
SiC403 very quiet.
• The output voltage ripple seen in power-save mode is
significant lower than conventional power-save, which
improves efficiency at light loads.
• Lower ripple in power-save also makes the power
component selection easier.
Figure 6 shows the behavior under power-save and
continuous conduction mode at light loads.
Smart Power-Save Protection
Active loads may leak current from a higher voltage into the
switcher output. Under light load conditions with
power-save-power-save enabled, this can force VOUT to
slowly rise and reach the over-voltage threshold, resulting in
a hard shutdown. Smart power-save prevents this condition.
When the FB voltage exceeds 10 % above nominal (exceeds
825 mV), the device immediately disables power-save, and
DL drives high to turn on the low-side MOSFET. This draws
current from VOUT through the inductor and causes VOUT to
fall. When VFB drops back to the 750 mV trip point, a normal
tON switching cycle begins.
This method prevents a hard OVP shutdown and also cycles
energy from VOUT back to VIN. It also minimizes operating
power by avoiding forced conduction mode operation.
Figure 7 shows typical waveforms for the smart power-save
feature.
VOUT drifts up to due to leakage
current flowing into COUT
Smart power save
threshold (825 mV)
FB
threshold
VOUT discharges via inductor
and low-side MOSFET
Normal VOUT ripple
DH and DL off
High-side
drive (DH)
Single DH on-time pulse
after DL turn-off
Low-side
drive (DL)
DL turns on when smart
PSAVE threshold is reached
DL turns off FB
threshold is reached
Normal DL pulse after DH
on-time pulse
Figure 7 - Smart Power-Save
Current Limit Protection
The SiC403 features programmable current limit capability,
which is accomplished by using the RDS(ON) of the lower
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SiC403
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MOSFET for current sensing. The current limit is set by RILIM
resistor. The RILIM resistor connects from the ILIM pin to the
LX pin which is also the drain of the low-side MOSFET.
When the low-side MOSFET is on, an internal ~ 10 µA
current flows from the ILIM pin and the RILIM resistor, creating
a voltage drop across the resistor. While the low-side
MOSFET is on, the inductor current flows through it and
creates a voltage across the RDS(ON). The voltage across the
MOSFET is negative with respect to ground.
If this MOSFET voltage drop exceeds the voltage across
RILIM, the voltage at the ILIM pin will be negative and current
limit will activate. The current limit then keeps the low-side
MOSFET on and will not allow another high-side on-time,
until the current in the low-side MOSFET reduces enough to
bring the ILIM voltage back up to zero. This method regulates
the inductor valley current at the level shown by ILIM in
figure 8.
Inductor Current
IPEAK
ILOAD
ILIM
Time
Figure 8 - Valley Current Limit
Setting the valley current limit to 6 A results in a 6 A peak
inductor current plus peak ripple current. In this situation, the
average (load) current through the inductor is 6 A plus
one-half the peak-to-peak ripple current.
The internal 10 µA current source is temperature
compensated at 4100 ppm in order to provide tracking with
the RDS(ON). The RILIM value is calculated by the following
equation.
RILIM = 1176 x ILIM x [0.088 x (5V - VDD) + 1] ()
where ILIM is in A.
When selecting a value for RILIM do not exceed the absolute
maximum voltage value for the ILIM pin.
Note that because the low-side MOSFET with low RDS(ON) is
used for current sensing, the PCB layout, solder
connections, and PCB connection to the LX node must be
done carefully to obtain good results. Refer to the layout
guidelines for information.
Soft-Start of PWM Regulator
SiC403 has a programmable soft-start time that is controlled
by an external capacitor at the SS pin. After the controller
meets both UVLO and EN/PSV thresholds, the controller has
an internal current source of 2.75 µA flowing through the
SS pin to charge the capacitor. During the start up process,
50 % of the voltage at the SS pin is used as the reference for
the FB comparator. The PWM comparator issues an on-time
Document Number: 66550
S12-0628-Rev. C, 19-Mar-12
pulse when the voltage at the FB pin is less than 50 % of the
SS pin. As result, the output voltage follows the SS start voltage. The output voltage reaches and maintains regulation
when the soft start voltage is > 1.5 V. The time between the
first LX pulse and when VOUT meets regulation is the soft
start time (tSS). The calculation for the soft-start time is
shown by the following equation:
tSS = CSS x
1.5 V
2.75 μA
Power Good Output
The power good (PGOOD) output is an open-drain output
which requires a pull-up resistor. When the output voltage is
10 % below the nominal voltage, PGOOD is pulled low. It is
held low until the output voltage returns above - 8 % of nominal. PGOOD is held low during start-up and will not be allowed
to transition high until soft-start is completed (when VFB
reaches 750 mV) and typically 2 ms has passed.
PGOOD will transition low if the VFB pin exceeds + 20 % of
nominal, which is also the over-voltage shutdown threshold
(900 mV). PGOOD also pulls low if the EN/PSV pin is low
when VDD is present.
Output Over-Voltage Protection
Over-voltage protection becomes active as soon as the
device is enabled. The threshold is set at 750 mV + 20 %
(900 mV). When VFB exceeds the OVP threshold, DL latches
high and the low-side MOSFET is turned on. DL remains
high and the controller remains off , until the EN/PSV input is
toggled or VDD is cycled. There is a 5 µs delay built into the
OVP detector to prevent false transitions. PGOOD is also low
after an OVP event.
Output Under-Voltage Protection
When VFB falls 25 % below its nominal voltage (falls to
562.5 mV) for eight consecutive clock cycles, the switcher is
shut off and the DH and DL drives are pulled low to tristate
the MOSFETs. The controller stays off until EN/PSV is
toggled or VDD is cycled.
VDD UVLO, and POR
Under-voltage lock-out (UVLO) circuitry inhibits switching
and tri-states the DH/DL drivers until VDD rises above 3 V.
An internal Power-On Reset (POR) occurs when VDD
exceeds 3 V, which resets the fault latch and soft-start
counter to prepare for soft-start. The SiC403 then begins a
soft-start cycle. The PWM will shut off if VDD falls below
2.4 V.
LDO Regulator
SIC403 has an option to bias the switcher by using an
internal LDO from VIN. The LDO output is connected to VDD
internally. The output of the LDO is programmable by using
external resistors from the VDD pin to AGND. The feedback
pin (FBL) for the LDO is regulated to 750 mV (see figure 9).
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SiC403
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VDD
to FBL pin
RLDO1
RLDO2
Figure 9 - LDO Voltage Divider
The LDO output voltage is set by the following equation.
(
VLDO = 750 mV x 1 +
RLDO1
RLDO2
)
Figure 10 - ENL Threshold
A minimum 0.1 µF capacitor referenced to AGND is equired
along with a minimum 1 µF capacitor referenced to PGND to
filter the gate drive pulses. Refer to the layout guidelines
section for component placement suggestions.
.
LDO ENL Functions
The ENL input is used to control the internal LDO. When ENL
is low (grounded), the LDO is off. When ENL is above the VIN
UVLO threshold, the LDO is enabled and the switcher is also
enabled if EN/PSV and VDD meet the thresholds.
The ENL pin also acts as the switcher UVLO (undervoltage
lockout) for the VIN supply. The VIN UVLO voltage is
programmable via a resistor divider at the VIN, ENL and
AGND pins.
If the ENL pin transitions from high to low within 2 switching
cycles and is less than 1 V, then the LDO will turn off but the
switcher remains on. If the ENL goes below the VIN UVLO
threshold and stays above 1 V, then the switcher will turn off
but the LDO remains on. The VIN UVLO function has a typical
threshold of 2.6 V on the VIN rising edge. The falling edge
threshold is 2.4 V.
Note that it is possible to operate the switcher with the LDO
disabled, but the ENL pin must be below the logic low
threshold (0.4 V max.). In this case, the UVLO function for
the input voltage cannot be used. The table below
summarizes the function of the ENL and EN pins, with
respect to the rising edge of ENL.
EN
ENL
LDO
Status
Switcher
Status
Low
Low, < 0.4 V
Off
Off
High
Low, < 0.4 V
Off
On
Low
High, < 2.6 V
On
Off
High
High, < 2.6 V
On
Off
Low
High, > 2.6 V
On
Off
High
High, > 2.6 V
On
On
Figure 10 shows the ENL voltage thresholds and their effect
on LDO and switcher operation.
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Before start-up, the LDO checks the status of the following
signals to ensure proper operation can be maintained.
• ENL pin
• VIN input voltage
When the ENL pin is high and VIN is above the UVLO point,
the LDO will begin start-up. During the initial phase, when the
VDD voltage (which is the LDO output voltage) is less than
0.75 V, the LDO initiates a current-limited start-up (typically
65 mA) to charge the output capacitors while protecting from
a short circuit event. When VDD is greater than 0.75 V but still
less than 90 % of its final value (as sensed at the FBL pin),
the LDO current limit is increased to ~ 115mA. When VDD
has reached 90 % of the final value (as sensed at the FBL
pin), the LDO current limit is increased to ~ 200 mA and the
LDO output is quickly driven to the nominal value by the
internal LDO regulator. It is recommended that during LDO
start-up to hold the PWM switching off until the LDO has
reached 90 % of the final value. This prevents overloading
the current-limited LDO output during the LDO start-up.
Due to the initial current limitations on the LDO during power
up (figure 11), any external load attached to the VDD pin must
be limited to 20 mA before the LDO has reached 90 % of it
final regulation value.
Figure 11 - LDO Start-Up
LDO Switchover Function
The SiC403 includes a switch-over function for the LDO. The
switch-over function is designed to increase efficiency by
using the more efficient DC/DC converter to power the LDO
output, avoiding the less efficient LDO regulator when
possible. The switch-over function connects the VLDO pin
directly to the VOUT pin using an internal switch. When the
switch-over is complete the LDO is turned off, which results
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in a power savings and maximizes efficiency. If the LDO
output is used to bias the SiC403, then after switch-over the
device is self-powered from the switching regulator with the
LDO turned off.
The switch-over logic waits for 32 switching cycles before it
starts the switch-over. There are two methods that determine
the switch-over of VLDO to VOUT.
In the first method, the LDO is already in regulation and the
DC/DC converter is later enabled. As soon as the PGOOD
output goes high, the 32 cycles are started. The voltages at
the VLDO and VOUT pins are then compared; if the two
voltages are within ± 300 mV of each other, the VLDO pin
connects to the VOUT pin using an internal switch, and the
LDO is turned off.
In the second method, the DC/DC converter is already
running and the LDO is enabled. In this case the 32 cycles
are started as soon as the LDO reaches 90 % of its final
value. At this time, the VLDO and VOUT pins are compared,
and if within ± 300 mV the switch-over occurs and the LDO
is turned off.
It is not recommended to use the switch-over feature for an
output voltage less than 3 V since this does not provide
sufficient voltage for the gate-source drive to the internal
p-channel switch-over MOSFET.
Benefits of having a switchover circuit
The switchover function is designed to get maximum
efficiency out of the DC/DC converter. The efficiency for an
LDO is very low especially for high input voltages. Using the
switchover function we tie any rails connected to VLDO
through a switch directly to VOUT. Once switchover is
complete LDO is turned off which saves power. This gives us
the maximum efficiency out of the SiC403.
If the LDO output is used to bias the SiC403, then after
switchover the VOUT self biases the SiC403 and operates in
self-powered mode.
Steps to follow when using the on chip LDO to bias the
SiC403:
• Always tie the VDD to VLDO before enabling the LDO
• Enable the LDO before enabling the switcher
• LDO has a current limit of 40 mA at start-up, so do not
connect any load between VLDO and ground
• The current limit for the LDO goes up to 200 mA once the
VLDO reaches 90 % of its final values and can easily supply
the required bias current to the IC.
There are some important design rules that must be followed
to prevent forward bias of these diodes. The following two
conditions need to be satisfied in order for the parasitic
diodes to stay off.
• VDD VLDO
• VDD VOUT
If either VLDO or VOUT is higher than VDD, then the respective
diode will turn on and the SiC403 operating current will flow
through this diode. This has the potential of damaging the
device.
Switch-over Limitations on VOUT and VLDO
Because the internal switch-over circuit always compares
the VOUT and VLDO pins at start-up, there are limitations on
permissible combinations of VOUT and VLDO. Consider the
case where VOUT is programmed to 1.5 V and VLDO is
programmed to 1.8 V. After start-up, the device would
connect VOUT to VLDO and disable the LDO, since the two
voltages are within the ± 300 mV switch-over window.
To avoid unwanted switch-over, the minimum difference
between the voltages for VOUT and VLDO should be
± 500 mV.
Document Number: 66550
S12-0628-Rev. C, 19-Mar-12
Switch-Over MOSFET Parasitic Diodes
The switch-over MOSFET contains parasitic diodes that are
inherent to its construction, as shown in figure 12.
Switchover
control
Switchover
MOSFET
VOUT
VLDO
Parastic diode
Parastic diode
V5V
Figure 12- Switch-over MOSFET Parasitic Diodes
ENL Pin and VIN UVLO
The ENL pin also acts as the switcher under-voltage lockout
for the VIN supply. The VIN UVLO voltage is programmable
via a resistor divider at the VIN, ENL and AGND pins.
ENL is the enable/disable signal for the LDO. In order to
implement the VIN UVLO there is also a timing requirement
that needs to be satisfied.
If the ENL pin transitions low within 2 switching cycles and is
< 0.4 V, then the LDO will turn off but the switcher remains
on. If ENL goes below the VIN UVLO threshold and stays
above 1 V, then the switcher will turn off but the LDO remains
on.
The VIN UVLO function has a typical threshold of 2.6 V on the
VIN rising edge. The falling edge threshold is 2.4 V.
Note that it is possible to operate the switcher with the LDO
disabled, but the ENL pin must be below the logic low
threshold (0.4 V maximum).
ENL Logic Control of PWM Operation
When the ENL input is driven above 2.6 V, it is impossible to
determine if the LDO output is going to be used to power the
device or not. In self-powered operation where the LDO will
power the device, it is necessary during the LDO start-up to
hold the PWM switching off until the LDO has reached 90 %
of the final value. This is to prevent overloading the
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SiC403
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current-limited LDO output during the LDO start-up.
However, if the switcher was previously operating (with EN/
PSV high but ENL at ground, and VDD supplied externally),
then it is undesirable to shut down the switcher.
To prevent this, when the ENL input is taken above 2.6 V
(above the VIN UVLO threshold), the internal logic checks the
PGOOD signal. If PGOOD is high, then the switcher is already
running and the LDO will run through the start-up cycle
without affecting the switcher. If PGOOD is low, then the LDO
will not allow any PWM switching until the LDO output has
reached 90 % of it's final value.
On-Chip LDO Bias the SiC403
The following steps must be followed when using the onchip
LDO to bias the device.
• Connect VDD to VLDO before enabling the LDO.
• The LDO has an initial current limit of 40 mA at start-up,
therefore, do not connect any external load to VLDO during
start-up.
• When VLDO reaches 90 % of its final value, the LDO
current limit increases to 200 mA. At this time the LDO may
be used to supply the required bias current to the device.
Attempting to operate in self-powered mode in any other
configuration can cause unpredictable results and may
damage the device.
Design Procedure
When designing a switch mode power supply, the input
voltage range, load current, switching frequency, and
inductor ripple current must be specified.
The maximum input voltage (VINMAX) is the highest specified
input voltage. The minimum input voltage (VINMIN) is
determined by the lowest input voltage after evaluating the
voltage drops due to connectors, fuses, switches, and PCB
traces.
The following parameters define the design:
• Nominal output voltage (VOUT)
• Static or DC output tolerance
• Transient response
• Maximum load current (IOUT)
There are two values of load current to evaluate - continuous
load current and peak load current. Continuous load current
relates to thermal stresses which drive the selection of the
inductor and input capacitors. Peak load current determines
instantaneous
component
stresses
and
filtering
requirements such as inductor saturation, output capacitors,
and design of the current limit circuit.
The following values are used in this design:
• VIN = 12 V ± 10 %
• VOUT = 1.05 V ± 4 %
• fSW = 250 kHz
• Load = 6 A maximum
Frequency Selection
Selection of the switching frequency requires making a
trade-off between the size and cost of the external filter
components (inductor and output capacitor) and the power
conversion efficiency.
The desired switching frequency is 250 kHz which results
from using component selected for optimum size and cost.
A resistor (RTON) is used to program the on-time (indirectly
setting the frequency) using the following equation.
Rton =
25 pF x VOUT
To select RTON, use the maximum value for VIN, and for tON
use the value associated with maximum VIN.
tON =
VOUT
VINMAX. x fSW
tON = 318 ns at 13.2 VIN, 1.05 VOUT, 250 kHz
Substituting for RTON results in the following solution
RTON = 154.9 k, use RTON = 154 k.
Inductor Selection
In order to determine the inductance, the ripple current must
first be defined. Low inductor values result in smaller size but
create higher ripple current which can reduce efficiency.
Higher inductor values will reduce the ripple current and
voltage and for a given DC resistance are more efficient.
However, larger inductance translates directly into larger
packages and higher cost. Cost, size, output ripple, and
efficiency are all used in the selection process.
The ripple current will also set the boundary for power-save
operation. The switching will typically enter power-save
mode when the load current decreases to 1/2 of the ripple
current. For example, if ripple current is 4 A then power-save
operation will typically start for loads less than 2 A. If ripple
current is set at 40 % of maximum load current, then
power-save will start for loads less than 20 % of maximum
current.
The inductor value is typically selected to provide a ripple
current that is between 25 % to 50 % of the maximum load
current. This provides an optimal trade-off between cost,
efficiency, and transient performance.
During the DH on-time, voltage across the inductor is
(VIN - VOUT). The equation for determining inductance is
shown next.
L=
(VIN - VOUT) x tON
IRIPPLE
Example
In this example, the inductor ripple current is set equal to
50 % of the maximum load current. Thus ripple current will be
50 % x 6 A or 3 A. To find the minimum inductance needed,
use the VIN and TON values that correspond to VINMAX.
L=
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16
(tON - 10 ns) x VIN
(13.2 - 1.05) x 318 ns
= 1.28 µH
3A
For technical support, please contact: analogswitchtechsupport@vishay.com
Document Number: 66550
S12-0628-Rev. C, 19-Mar-12
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403
Vishay Siliconix
A slightly larger value of 1.3 µH is selected. This will
decrease the maximum IRIPPLE to 2.9 A.
Note that the inductor must be rated for the maximum DC
load current plus 1/2 of the ripple current. The ripple current
under minimum VIN conditions is also checked using the
following equations.
TON_VINMIN =
IRIPPLE =
25 pF x RTON x VOUT
VINMIN
(VIN - VOUT) x TON
L
IRIPPLE_VIN =
(10.8 - 1.05) x 384 ns
= 2.88 A
1.3 µH
Capacitor Selection
The output capacitors are chosen based on required ESR
and capacitance. The maximum ESR requirement is
controlled by the output ripple requirement and the DC
tolerance. The output voltage has a DC value that is equal to
the valley of the output ripple plus 1/2 of the peak-to-peak
ripple. Change in the output ripple voltage will lead to a
change in DC voltage at the output.
The design goal is that the output voltage regulation be
± 4 % under static conditions. The internal 500 mV reference
tolerance is 1 %. Allowing 1 % tolerance from the FB resistor
divider, this allows 2 % tolerance due to VOUT ripple.
Since this 2 % error comes from 1/2 of the ripple voltage, the
allowable ripple is 4 %, or 42 mV for a 1.05 V output.
The maximum ripple current of 4.4 A creates a ripple voltage
across the ESR. The maximum ESR value allowed is shown
by the following equations.
ESRMAX =
VRIPPLE
IRIPPLEMAX
=
42 mV
2.9 A
ESRMAX = 9.5 mΩ
The output capacitance is usually chosen to meet transient
requirements. A worst-case load release, from maximum
load to no load at the exact moment when inductor current is
at the peak, determines the required capacitance. If the load
release is instantaneous (load changes from maximum to
zero in < 1 µs), the output capacitor must absorb all the
inductor's stored energy. This will cause a peak voltage on
the capacitor according to the following equation.
1
xI
)2
2 RIPPLEMAX
(VPEAK)2 - (VOUT)2
L (IOUT +
COUT_MIN =
Assuming a peak voltage VPEAK of 1.150 (100 mV rise upon
load release), and a 10 A load release, the required
capacitance is shown by the next equation.
1
x 2.9)2
2
2
(1.15) - (1.05)2
1.3 µH (6 +
COUT_MIN =
If the load release is relatively slow, the output capacitance
can be reduced. At heavy loads during normal switching,
when the FB pin is above the 750 mV reference, the DL
output is high and the low-side MOSFET is on. During this
time, the voltage across the inductor is approximately - VOUT.
This causes a down-slope or falling di/dt in the inductor. If the
load dI/dt is not much faster than the - dI/dt in the inductor,
then the inductor current will tend to track the falling load
current. This will reduce the excess inductive energy that
must be absorbed by the output capacitor, therefore a
smaller capacitance can be used.
The following can be used to calculate the needed
capacitance for a given dILOAD/dt:
Peak inductor current is shown by the next equation.
ILPK = IMAX + 1/2 x IRIPPLEMAX
ILPK = 6 + 1/2 x 2.9 = 7.45 A
Rate of change of load current = dILOAD/dt
IMAX = maximum load release = 6 A
COUT = ILPK x
I
I
L x LPK - MAX x dt
VOUT dlLOAD
2 (VPK - VOUT)
Example
Load
dlLOAD 2.5 A
=
µs
dt
This would cause the output current to move from 10 A to
zero in 4 µs as shown by the following equation.
7.45
6
x 1 µs
1.05
2.5
2 (1.15 - 1.05)
1.3 µH x
COUT = 7.45 x
COUT = 254 µF
Note that COUT is much smaller in this example, 254 µF
compared to 328 µF based on a worst-case load release. To
meet the two design criteria of minimum 254 µF and
maximum 9 m ESR, select two capacitors rated at 150 µF
and 18 m ESR.
It is recommended that an additional small capacitor be
placed in parallel with COUT in order to filter high frequency
switching noise.
Stability Considerations
Unstable operation is possible with adaptive on-time
controllers, and usually takes the form of double-pulsing or
ESR loop instability.
Double-pulsing occurs due to switching noise seen at the FB
input or because the FB ripple voltage is too low. This causes
the FB comparator to trigger prematurely after the 250 ns
minimum off-time has expired. In extreme cases the noise
can cause three or more successive on-times.
Double-pulsing will result in higher ripple voltage at the
output, but in most applications it will not affect operation.
COUT_MIN = 328 µF
Document Number: 66550
S12-0628-Rev. C, 19-Mar-12
For technical support, please contact: analogswitchtechsupport@vi-
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17
This document is subject to change without notice.
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SiC403
Vishay Siliconix
This form of instability can usually be avoided by providing
the FB pin with a smooth, clean ripple signal that is at least
10 mVp-p, which may dictate the need to increase the ESR of
the output capacitors. It is also imperative to provide a proper
PCB layout as discussed in the Layout Guidelines section.
CTOP
For applications using ceramic output capacitors, the ESR is
normally too small to meet the above ESR criteria. In these
applications it is necessary to add a small virtual ESR
network composed of two capacitors and one resistor, as
shown in figure 14. This network creates a ramp voltage
across CL, analogous to the ramp voltage generated across
the ESR of a standard capacitor. This ramp is then
capacitive-coupled into the FB pin via capacitor CC.
L
VOUT
To FB pin
R1
Highside
R2
CL
RL
R1
Figure 13 - Capacitor Coupling to FB Pin
Another way to eliminate doubling-pulsing is to add a small
(~ 10 pF) capacitor across the upper feedback resistor, as
shown in figure 13. This capacitor should be left unpopulated
until it can be confirmed that double-pulsing exists. Adding
the CTOP capacitor will couple more ripple into FB to help
eliminate the problem. An optional connection on the PCB
should be available for this capacitor.
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking
stability is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and ringing.
Ringing for more than one cycle after the initial step is an
indication that the ESR should be increased.
One simple way to solve this problem is to add trace
resistance in the high current output path. A side effect of
adding trace resistance is output decreased load regulation.
ESR Requirements
A minimum ESR is required for two reasons. One reason is
to generate enough output ripple voltage to provide10 mVp-p
at the FB pin (after the resistor divider) to avoid
double-pulsing.
The second reason is to prevent instability due to insufficient
ESR. The on-time control regulates the valley of the output
ripple voltage. This ripple voltage is the sum of the two
voltages. One is the ripple generated by the ESR, the other
is the ripple due to capacitive charging and discharging
during the switching cycle. For most applications the
minimum ESR ripple voltage is dominated by the output
capacitors, typically SP or POSCAP devices. For stability the
ESR zero of the output capacitor should be lower than
approximately one-third the switching frequency. The
formula for minimum ESR is shown by the following
equation.
ESRMIN =
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18
Lowside
CC
COUT
R2
FB
pin
Figure 14 - Virtual ESR Ramp Current
Dropout Performance
The output voltage adjusts range for continuous-conduction
operation is limited by the fixed 250 ns (typical) minimum
off-time of the one-shot. When working with low input
voltages, the duty-factor limit must be calculated using
worst-case values for on and off times. The duty-factor
limitation is shown by the next equation.
DUTY =
TON(MIN)
TON(MIN) x TOFF(MAX)
The inductor resistance and MOSFET on-state voltage drops
must be included when performing worst-case dropout
duty-factor calculations.
3
2 x π x COUT x fSW
For technical support, please contact: analogswitchtechsupport@vishay.com
Document Number: 66550
S12-0628-Rev. C, 19-Mar-12
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403
Vishay Siliconix
System DC Accuracy (VOUT Controller)
Three factors affect VOUT accuracy: the trip point of the FB
error comparator, the ripple voltage variation with line and
load, and the external resistor tolerance. The error
comparator off set is trimmed so that under static conditions
it trips when the feedback pin is 750 mV, 1 %.
The on-time pulse from the SiC403 in the design example is
calculated to give a pseudo-fixed frequency of 250 kHz.
Some frequency variation with line and load is expected.
This variation changes the output ripple voltage. Because
constant on-time converters regulate to the valley of the
output ripple, ½ of the output ripple appears as a DC
regulation error. For example, if the output ripple is 50 mV
with VIN = 6 V, then the measured DC output will be 25 mV
above the comparator trip point. If the ripple increases to
80 mV with VIN = 25 V, then the measured DC output will be
40 mV above the comparator trip. The best way to minimize
this effect is to minimize the output ripple.
To compensate for valley regulation, it may be desirable to
use passive droop. Take the feedback directly from the
output side of the inductor and place a small amount of trace
resistance between the inductor and output capacitor.
This trace resistance should be optimized so that at full load
the output droops to near the lower regulation limit. Passive
droop minimizes the required output capacitance because
the voltage excursions due to load steps are reduced as
seen at the load.
The use of 1 % feedback resistors contributes up to 1 %
error. If tighter DC accuracy is required, 0.1 % resistors
should be used.
The output inductor value may change with current. This will
change the output ripple and therefore will have a minor
effect on the DC output voltage. The output ESR also affects
the output ripple and thus has a minor effect on the DC
output voltage.
Document Number: 66550
S12-0628-Rev. C, 19-Mar-12
Switching Frequency Variations
The switching frequency will vary depending on line and load
conditions. The line variations are a result of fixed
propagation delays in the on-time one-shot, as well as
unavoidable delays in the external MOSFET switching. As
VIN increases, these factors make the actual DH on-time
slightly longer than the ideal on-time. The net effect is that
frequency tends to falls slightly with increasing input voltage.
The switching frequency also varies with load current as a
result of the power losses in the MOSFETs and the inductor.
For a conventional PWM constant-frequency converter, as
load increases the duty cycle also increases slightly to
compensate for IR and switching losses in the MOSFETs
and inductor.
A constant on-time converter must also compensate for the
same losses by increasing the effective duty cycle (more
time is spent drawing energy from VIN as losses increase).
The on-time is essentially constant for a given VOUT/VIN
combination, to off set the losses the off-time will tend to
reduce slightly as load increases. The net effect is that
switching frequency increases slightly with increasing load.
For technical support, please contact: analogswitchtechsupport@vi-
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19
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
P1
VDD
B2
VIN_GND
1
M1
1
1
1
1
1
M2
C26
4.7uF
C12
150uF
+
1
1
1
C27
4.7uF
1
M3
C28
0.1uF
C10
C20
C22
220uF 220uF 220uF
+
B1
VIN
+
P8 P9
VIN VIN_GND
P2
EN_PSV
1
+
1
R12
57.6K
1
M4
R29
10K
C11
0.1uF
R2
300K
1
6
9
10
11
34
C29
22nF
FBL5
SOFT 7
VDD 3
C13
0.01uF
VIN
R6 100K
ENL
P6
ENL
R52 31K6
C37
10nF
FBL
SOFT
VDD
VIN
VIN
VIN
VIN
VIN
C5
0.1uF
U1
Vo
SiC401/2/3
R39 0R
PGD
TON
ILIM
FB
LXS
LX
LX
LX
LX
LXBST
C6
0.1uF
R30
154K
P7
PGOOD
VDD
26 PGD C30
31
100pF
27 ILIM
1 FB
33 LX
25
24
23
R8 10K
28
13
R7 0R
R14 100
R15
1.5K
5
C36
1nF
R51
1R
3
4
2
1
0.78uH
R13 10K
C24
10n *
R9 *
L1
J5
Probe Test Pin
C19 1u *
0.1uF
C14
10uF
C15
VOUT
1
10uF
C21
220uF
C16
LDTRG
P4
R4 1R01
Step_I_Sense
1
C18
220uF
C17
220uF
Q1
Si4812BDY
C7
0.1uF
R5
100K
C25
68pF
C1
22uF
C2
22uF
R23
7k15
R10
10K
C3
22uF
C4
22uF
P11
VO_GND
VCTL
P5
P10
VOUT
1
1
P3
1
R1
300K
1
32
ENL
14
NC
29 EN_PSV
EN/PSV
12
NC
BST
8
BST
2
VOUT
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
AGND
AGND
AGND
15
16
17
18
19
20
21
22
4
30
35
lxbst
TON
+
1
+
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20
+
VDD
B4
1
1
B3
VO_GND
Vo
SiC403
Vishay Siliconix
SIC403 EVALUATION BOARD SCHEMATIC
Figure 15. Evaluation Board Schematic
For technical support, please contact: analogswitchtechsupport@vishay.com
Document Number: 66550
S12-0628-Rev. C, 19-Mar-12
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SiC403
Vishay Siliconix
BILL OF MATERIALS
Item
Qty.
Reference
Value
Voltage
PCB Footprint
Part Number
Manufacturer
1
1
B1
VIN
SOLDER-BANANA
575-4
Keystone
2
1
B2
VIN_GND
SOLDER-BANANA
575-4
Keystone
3
1
B3
Vo
SOLDER-BANANA
575-4
Keystone
4
1
B4
VO_GND
SOLDER-BANANA
575-4
Keystone
5
4
C1, C2, C3, C4
22 µF
SM/C_1210
GRM32ER71C226ME18L
Murata
6
1
C5
0.1 µF
16 V
SM/C_0402
EMK105BJ104KV-F
Taiyo Yuden
7
1
C6
0.1 µF
50 V
SM/C_0603
VJ0603Y104KXACW1BC
Murata
8
3
C7, C11, C14
0.1 µF
50 V
SM/C_0603
VJ0603Y104KXACW1BC
Vishay
9
3
C10, C20, C22
220 µF
25 V
595D-D
593D227X0010E2TE3
Vishay
10
1
C12
150 µF
35 V
D8X11.5-D0.6X3.5
EEU-FM1V151
Panasonic
16 V
11
1
C13
0.01 µF
50 V
SM/C_0402
VJ0402Y103KXACW1BC
Vishay
12
2
C15, C21
10 µF
16 V
SM/C_1206
C3216X7R1C106M
TDK
13
3
C16, C17, C18
220 µF
10 V
595D-D
593D227X0010E2TE3
Vishay
14
1
C19
1 µ
SM/C_0603
15
1
C24
10 n
SM/C_0603
16
1
C25
68 pF
50 V
SM/C_0402
0402YA680JAT2A
AVX
17
2
C26, C27
4.7 µF
10 V
SM/C_0805
LMK212B7475KG-T
TAIYO
YUDEN
18
1
C28
0.1 µF
10 V
SM/C_0603
GRM155R61A105KE19D
Murata
19
1
C29
22 nF
16 V
SM/C_0603
20
1
C30
100 pF
50 V
SM/C_0402
VJ0402Y101KXACW1BC
Vishay
21
1
C36
1 nF
50 V
SM/C_0402
C0402C102K3RA
Vishay
22
1
C37
10 nF
50 V
Vishay
23
1
J5
Probe Test Pin
24
1
L1
25
4
M1, M2, M3, M4
26
1
P1
Murata
SM/C_0402
VJ0402A103KXACW1BC
LECROY PROBE PIN
PK007-015
0.78 µH
IHLP4040
IHLP4040DZERR78M11
Vishay
M HOLE2
STACKING SPACER
8834
Keystone
VDD
Probe Hook - d76
1573-3
Keystone
27
1
P2
EN_PSV
Probe Hook - d76
1573-3
Keystone
28
1
P3
Step_I_Sense
Probe Hook - d76
1573-3
Keystone
29
1
P4
LDTRG
Probe Hook - d76
1573-3
Keystone
30
1
P5
VCTL
Probe Hook - d76
1573-3
Keystone
31
1
P6
ENL
Probe Hook - d76
1573-3
Keystone
32
1
P7
PGOOD
Probe Hook - d76
1573-3
Keystone
33
1
P8
VIN
Probe Hook - d76
1573-3
Keystone
34
1
P9
VIN_GND
Probe Hook - d76
1573-3
Keystone
Probe Hook - d76
1573-3
Keystone
Probe Hook - d76
1573-3
Keystone
SO-8
Si4812BDY
Vishay
35
1
P10
VOUT
36
1
P11
VO_GND
37
1
Q1
Si4812BDY
30 V
38
1
R1
300K
50 V
SM/C_0603
CRCW060310K0FKEA
Vishay
39
1
R2
300K
50 V
SM/C_0603
CRCW06030000FKEA
Vishay
40
1
R4
1R01
200 V
C_2512
CRCW25121R00FKTA
Vishay
41
2
R5, R6
100K
50 V
SM/C_0603
CRCW0603100KFKEA
Vishay
42
1
R7
0R
50 V
SM/C_0603
CRCW06030000Z0EA
Vishay
Document Number: 66550
S12-0628-Rev. C, 19-Mar-12
For technical support, please contact: analogswitchtechsupport@vi-
www.vishay.com
21
This document is subject to change without notice.
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SiC403
New Product
Vishay Semiconductors
BILL OF MATERIALS
43
3
R8, R10, R29
10K
44
1
R9
50 V
SM/C_0603
CRCW060310K0FKEA
Vishay
SM/C_0603
45
1
R12
57.6K
50 V
SM/C_0603
CRCW060357K6FKEA
Vishay
46
1
R13
10K
50 V
SM/C_0402
CRCW040210K0FKED
Vishay
47
1
R14
100
50 V
SM/C_0402
CRCW040210K0FKED
Vishay
48
1
R15
1.5K
SM/C_0603
CRCW06031K50FKEA
Vishay
49
1
R23
7k15
SM/C_0603
CRCW06037K15FKEA
Vishay
50
1
R30
154K
SM/C_0603
CRCW0603154KFKEA
Vishay
51
1
R39
0R
SM/C_0402
CRCW04020000Z0ED
Vishay
52
1
R51
1R
SM/C_0805
CRCW08051R00FNEA
Vishay
53
1
R52
31K6
SM/C_0603
CRCW060331K6FKEA
Vishay
54
1
U1
SiC401/2/3
www.vishay.com
22
50 V
MLPQ5x5-32L
Vishay
Document Number: 66550
S12-0628-Rev. C, 19-Mar-12
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403
Vishay Siliconix
PCB LAYOUT OF THE EVALUATION BOARD
Figure 14. Top Layer
Figure 15. Middle Layer 1
Figure 16. Middle Layer 2
Figure 17. Bottom Layer
Figure 15. Top Component
Figure 17. Bottom Component
Document Number: 66550
S12-0628-Rev. C, 19-Mar-12
For technical support, please contact: analogswitchtechsupport@vi-
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23
This document is subject to change without notice.
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SiC403
New Product
Vishay Semiconductors
PACKAGE DIMENSIONS AND MARKING INFO
0.900 ± 0.100
0.050
0.000
3.480 ± 0.100
17
24
0.400 ± 0.100
25
16
1.970 ± 0.100
5.000 ± 0.075
R Full
CL
1.050 ± 0.100
0.10 C
B
A
5.000 ± 0.075
C
0.460
32
+
9
Pin # 1 (Laser Marked)
Top View
0.08 C
Bare
Copper
8
R0.200
Pin 1 I.D.
CL
1.660 ± 0.100
1.485 ± 0.100
0.250 ± 0.050
0.10
C AB
0.200 ref.
0.500
0.460
Bottom View
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?66550.
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24
Document Number: 66550
S12-0628-Rev. C, 19-Mar-12
This document is subject to change without notice.
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Package Information
Vishay Siliconix
PowerPAK® MLP55-32L CASE OUTLINE
0.08 C
A
A1
D
A2
25
1
4
(5 mm x 5 mm)
Pin #1 identification
R0.200
E2 - 3
0.10
E
32L T/SLP
D2 - 2
32
24
E2 - 1
CAB
e
0.10 CB
D2 - 1
0.360
8
17
B
b
16
L
C
0.36
Top View
(Nd-1) Xe
Ref.
0.10 CA
A
E2 - 2
2x
0.45
5 6
Pin 1 dot
by marking
2x
Side View
D2 - 3
D2 - 4
(Nd-1) Xe
Ref.
D4
9
Bottom View
MILLIMETERS
INCHES
DIM
MIN.
NOM.
MAX.
MIN.
NOM.
A
0.80
0.85
0.90
0.031
0.033
0.035
A1(8)
0.00
-
0.05
0.000
-
0.002
0.30
0.078
A2
b(4)
0.20 REF.
0.20
0.25
0.008 REF.
0.098
D
5.00 BSC
0.196 BSC
e
0.50 BSC
0.019 BSC
E
5.00 BSC
L
0.35
0.40
MAX.
0.011
0.196 BSC
0.45
0.013
0.015
N(3)
32
32
Nd(3)
8
8
Ne(3)
8
0.017
8
D2 - 1
3.43
3.48
3.53
0.135
0.137
0.139
D2 - 2
1.00
1.05
1.10
0.039
0.041
0.043
D2 - 3
1.00
1.05
1.10
0.039
0.041
0.043
D2 - 4
1.92
1.97
2.02
0.075
0.077
0.079
E2 - 1
3.43
3.48
3.53
0.135
0.137
0.139
E2 - 2
1.61
1.66
1.71
0.063
0.065
0.067
E2 - 3
1.43
1.48
1.53
0.056
0.058
0.060
ECN: T-08957-Rev. A, 29-Dec-08
DWG: 5983
Notes
1. Use millimeters as the primary measurement.
2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994.
3. N is the number of terminals.
Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction.
4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip.
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body.
6. Exact shape and size of this feature is optional.
7. Package warpage max. 0.08 mm.
8. Applied only for terminals.
Document Number: 64714
Revision: 29-Dec-08
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