SiC431
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Vishay Siliconix
3 V to 24 V Input, 24 A
microBUCK® DC/DC Converter
FEATURES
DESCRIPTION
The SiC431 is a synchronous buck regulator with integrated
high side and low side power MOSFETs. Its power stage
is capable of supplying 24 A continuous current at up to
1 MHz switching frequency. This regulator produces an
adjustable output voltage down to 0.6 V from 3 V to 24 V
input rail
to accommodate a variety of applications,
including computing, consumer electronics, telecom, and
industrial.
SiC431’s architecture supports ultrafast transient response
with minimum output capacitance and tight ripple regulation
at very light load. The device is internally compensated and
no external ESR network is required for loop stability
purposes. The device also incorporates a power saving
scheme that significantly increases light load efficiency.
The regulator integrates a full protection feature set,
including output over voltage protection (OVP), cycle by
cycle over current protection (OCP) short circuit protection
(SCP) and thermal shutdown (OTP). It also has UVLO and a
user programmable soft start.
The SiC431 is available in lead (Pb)-free power enhanced
MLP44-24L package in 4 mm x 4 mm dimension.
APPLICATIONS
•
•
•
•
5 V, 12 V, and 24 V input rail POLs
Desktop, notebooks, server, and industrial computing
Industrial and automation
consumer electronics
• Versatile
- Operation from 3 V to 24 V input voltage
- Adjustable output voltage down to 0.6 V
- Scalable solution 8 A (SiC438), 12 A (SiC437),
and 24 A (SiC431)
- Output voltage tracking and sequencing with
pre-bias start up
- ± 1 % output voltage accuracy from -40 °C to +125 °C
• Highly efficient
- 97 % peak efficiency
- 1 μA supply current at shutdown
- 50 μA operating current, not switching
• Highly configurable
- Four programmable switching frequencies available:
300 kHz, 500 kHz, 750 kHz, and 1 MHz
- Adjustable soft start and adjustable current limit
- Three modes of operation: forced continuous
conduction, power save (SiC431B, SiC431D), or
ultrasonic (SiC431A, SiC431C)
• Robust and reliable
- Cycle-by-cycle current limit
- Output overvoltage protection
- Output undervoltage / short circuit protection with auto
retry
- Power good flag and over temperature protection
• Design tools
- Supported by Vishay PowerCAD Online Design
Simulation (www.vishay.com/power-ics/powercad-list/)
- Design Support Kit (www.vishay.com/ppg?74589)
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
TYPICAL APPLICATION CIRCUIT AND PACKAGE OPTIONS
100
VOUT = 5 V, L = 1 μH
VOUT = 3.3 V, L = 1 μH
97
VDD
CIN
BOOT
94
CBOOT
Phase
VOUT
SiC431 SW
GL
VDRV
MODE1
VOUT
MODE2
VFB
Efficiency (%)
VIN
PGOOD
EN
INPUT
3.0 VDC to 24 VDC
91
88
VOUT = 1.2 V, L = 0.36 μH
85
82
PGND
AGND
RUP
RDOWN
Complete converter efficiency
PIN = VIN x IIN
POUT = VOUT x IOUT, measured at output capacitor
79
COUT
76
0
2
4
6
8
10
12
14
16
18
20
Output Current, IOUT (A)
Fig. 1 - Typical Application Circuit for SiC431
S18-0866-Rev. D, 27-Aug-2018
Fig. 2 - Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, Full Load)
Document Number: 74589
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SiC431
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Vishay Siliconix
17 FB
16 AGND
AGND 16
VIN 2
15 VDD
VDD 15
14 PGOOD
PGOOD 14
PGND 3
13 PGND
PGND 13
PGND 4
12 VDRV
VDRV 12
23 BOOT
24 PHASE
22 VIN
21 MODE1
25
AGND
26
VIN
1 VIN
2 VIN
27
PGND
3 PGND
4 PGND
SW 5
SW 6
SW 7
SW 8
GL 10
28
GL
SW 9
GL 11
GL 10
SW 9
SW 8
SW 7
11 GL
SW 6
20 MODE2
FB 17
VIN 1
SW 5
19 EN
18 VOUT
18 VOUT
19 EN
20 MODE2
21 MODE1
22 VIN
23 BOOT
Pin 1 indicator
24 PHASE
PIN CONFIGURATION
Fig. 3 - SiC431 Pin Configuration
PIN DESCRIPTION
PIN NUMBER
SYMBOL
1, 2, 22, 26
3, 4, 13, 27
5 to 9
10, 11, 28
12
14
15
16, 25
17
18
19
20
VIN
PGND
SW
GL
VDRV
PGOOD
VDD
AGND
FB
VOUT
EN
MODE2
Input voltage
Power signal return ground
Switching node signal; output inductor connection point
Low side power MOSFET gate signal
Supply voltage for internal gate driver. Connect a 2.2 μF decoupling capacitor to PGND
Power good signal output; open drain
Supply voltage for internal logic. Connect a 1 μF decoupling capacitor to AGND
Analog signal return ground
Output voltage feedback pin; connect to VOUT through a resistor divider network.
Output voltage sense pin
Enable pin
Soft start and current limit selection; connect a resistor to VDD or AGND per Table 2
DESCRIPTION
21
23
24
MODE1
BOOT
PHASE
Operating mode and switching frequency selection; connect a resistor to VDD or AGND per Table 1
Bootstrap pin; connect a capacitor to PHASE pin for HS power MOSFET gate voltage supply
Switching node signal for bootstrap return path
ORDERING INFORMATION
PART NUMBER
PART
MARKING
SiC431AED-T1-GE3
SiC431A
SiC431BED-T1-GE3
SiC431B
SiC431CED-T1-GE3
SiC431C
SiC431DED-T1-GE3
SiC431D
S18-0866-Rev. D, 27-Aug-2018
MAXIMUM
CURRENT
VDD, VDRV
Internal
24 A
External
LIGHT LOAD
MODE
OPERATING
JUNCTION
TEMPERATURE
PACKAGE
-40 °C to +125 °C
PowerPAK® MLP44-24L
Ultrasonic
Power saving
Ultrasonic
Power saving
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SiC431
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ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
ELECTRICAL PARAMETER
CONDITIONS
LIMITS
VIN
Reference to PGND
-0.3 to +25
UNIT
-0.3 to +22
VOUT
Reference to PGND
VDD / VDRV
Reference to PGND
-0.3 to +6
SW / PHASE
Reference to PGND
-0.3 to +25
SW / PHASE (AC)
BOOT
100 ns; reference to PGND
-8 to +30
Reference to PGND
-0.3 to +31
BOOT to SW
-0.3 to +6
AGND to PGND
-0.3 to +0.3
EN
Reference to AGND
-0.3 to +25
All other pins
Reference to AGND
-0.3 to +6
Junction temperature
TJ
-40 to +150
Storage temperature
TSTG
-65 to +150
V
Temperature
°C
Power Dissipation
Junction-to-ambient thermal impedance (RJA)
16
Junction-to-case thermal impedance (RJC)
2
Maximum power dissipation
Ambient temperature = 25 °C
°C/W
7.75
W
ESD Protection
Electrostatic discharge protection
Human body model
4000
Charged device model
1000
V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating/conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (all voltages referenced to AGND, PGND = 0 V)
PARAMETER
MIN.
TYP.
MAX.
Input voltage (VIN) (SiC431A, SiC431B)
4.5
-
24
Input voltage (VIN) (SiC431C, SiC431D)
3
-
24
4.5
5
5.5
0
-
24
0.6
-
0.9 x VIN
and < 20 V
Logic supply voltage, gate driver supply voltage (VDD, VDRV)
(SiC431C, SiC431D)
Enable (EN)
Output voltage (VOUT)
UNIT
V
Temperature
Recommended ambient temperature
-40 to +105
Operating junction temperature
-40 to +125
S18-0866-Rev. D, 27-Aug-2018
°C
Document Number: 74589
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SiC431
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Vishay Siliconix
ELECTRICAL SPECIFICATIONS (VIN = 12 V, VEN = 5 V, TJ = -40 °C to +125 °C, unless otherwise stated)
PARAMETER
Power Supplies
VDD supply
VDD UVLO threshold, rising
VDD UVLO hysteresis
Maximum VDD current
VDRV supply
Maximum VDRV current
Input current
Shutdown current
Controller and Timing
Feedback voltage
VFB input bias current
Minimum on-time
tON accuracy
On-time range
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
VDD
VDD_UVLO
VIN = 6 V to 24 V (SiC431A, SiC431B)
4.75
3.3
3
4.75
50
-
5
3.6
300
5
50
0.5
5.25
3.9
5.25
120
3
597
594
-10
65
20
0
205
600
600
2
50
250
603
606
65
10
2250
30
305
VDD_UVLO_HYST
IDD
VDRV
IDRV
IIN
IIN_SHDN
VFB
TJ = 25 °C
TJ = -40 °C to +125 °C (1)
IFB
tON_MIN.
tON_ACCURACY
tON_RANGE
Minimum frequency, skip mode
fSW_MIN.
Minimum off-time
Power MOSFETs
High side on resistance
Low side on resistance
Fault Protections
Over current protection (inductor valley
current)
Output OVP threshold
Output UVP threshold
tOFF_MIN.
Over temperature protection
VIN = 6 V to 24 V
VIN = 6 V to 24 V (SiC431A, SiC431B)
VIN = 6 V to 24 V
Non-switching, VFB > 0.6 V
VEN = 0 V
Ultrasonic version (SiC431A, SiC431C)
Power save version (SiC431B, SiC431D)
RON_HS
RON_LS
VDRV = 5 V, TA = 25 °C
-
6
2
-
IOCP
TJ = -10 °C to +125 °C
-20
-
20
VOVP
VUVP
VFB with respect to 0.6 V reference
TOTP_RISING
TOTP_HYST
Rising temperature
Hysteresis
-
20
-80
150
25
-
VFB_RISING_VTH_OV
VFB_FALLING_VTH_UV
VFB_HYST
RON_PGOOD
tDLY_PGOOD
VFB rising above 0.6 V reference
VFB falling below 0.6 V reference
15
20
-10
40
7.5
25
15
35
1.6
-
5
0.4
-
90
180
450
51
100
200
499
55
110
220
-
1.8
3
4.2
3.6
6
8.4
450
180
90
-
499
200
100
51
220
110
55
UNIT
V
mV
mA
V
mA
μA
m/V
nA
ns
%
ns
kHz
ns
m
%
°C
Power Good
Power good output threshold
Power good hysteresis
Power good on resistance
Power good delay time
EN / MODE / Ultrasonic Threshold
EN logic high level
EN logic low level
EN pull down resistance
Switching Frequency
MODE1 (switching frequency)
VEN_H
VEN_L
REN
RMODE1
fSW = 300 kHz
fSW = 500 kHz
fSW = 750 kHz
fSW = 1000 kHz
tss
Connect RMODE2 between
MODE2 and AGND
Connect RMODE2 between
MODE2 and VDD
%
mV
μs
V
M
k
Soft Start
Soft start time
ms
Over Current Protection
MODE2 (over current protection)
RMODE2
IOCP = 32 A
IOCP = 24.8 A
IOCP = 17.3 A
IOCP = 9.6 A
k
Note
(1) Guaranteed by design
S18-0866-Rev. D, 27-Aug-2018
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SiC431
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Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM
VIN
VDRV
VOUT
Sync.
rectifier
Regulator
Rr
VDD
BOOT
UVLO
EN
Enable
MODE1
PH
Control
logic
Over voltage
under voltage
SW
VOUT
FB
SW
VDRV
Ramp
On time
generator
EA
Reference
RC
GL
Zero
crossing
PGOOD
CC
Soft start
Over
current
MODE2
Over
temperature
Power good
AGND
PGND
Fig. 4 - SiC431 Functional Block Diagram
S18-0866-Rev. D, 27-Aug-2018
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SiC431
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Vishay Siliconix
OPERATIONAL DESCRIPTION
Device Overview
VOUT
L
SiC431 is a high efficiency synchronous buck regulator
capable of delivering up to 24 A continuous current. The
device has user programmable switching frequency of 300
kHz, 500 kHz, 750 kHz, and 1 MHz. The control scheme
delivers fast transient response and minimizes the number
of external components. Thanks to the internal ramp
information, no high ESR output bulk or virtual ESR network
is required for the loop stability. This device also
incorporates a power saving feature that enables diode
emulation mode and frequency fold back as the load
decreases.
SiC431 has a full set of protection and monitoring features:
• Over current protection in pulse-by-pulse mode
• Output over voltage protection
• Output under voltage protection with device latch
• Over temperature protection with hysteresis
• Dedicated enable pin for easy power sequencing
• Power good open drain output
This device is available in MLP44-24L package to deliver
high power density and minimize PCB area.
Power Stage
SiC431 integrates a high performance power stage with a
2 m n-channel low side MOSFET and a 6 m n-channel
high side MOSFET. The MOSFETs are optimized to achieve
up to 97 % efficiency.
The input voltage (VIN) can go up to 24 V and down to as low
as 3 V for power conversion. For input voltages (VIN) below
4.5 V an external VDD and VDRV supply is required (SiC431C,
SiC431D). For input voltages (VIN) above 4.5 V only a single
input supply is required (SiC431A, SiC431B).
Control Mechanism
SiC431 employs an advanced voltage - mode COT control
mechanism. During steady-state operation, feedback
voltage (VFB) is compared with internal reference (0.6 V typ.)
and the amplified error signal (VCOMP) is generated at the
internal comp node. An internally generated ramp signal and
VCOMP feed into a comparator. Once VRAMP crosses VCOMP,
an on-time pulse is generated for a fixed time. During the
on-time pulse, the high side MOSFET will be turned on.
Once the on-time pulse expires, the low side MOSFET will
be turned on after a dead time period. The low side MOSFET
will stay on for a minimum duration equal to the minimum
off-time (tOFF_MIN.) and remains on until VRAMP crosses
VCOMP. The cycle is then repeated.
Fig. 5 illustrates the basic block diagram for VM-COT
architecture. In this architecture the following is achieved:
• The reference of a basic ripple control regulator is
replaced with a high again error amplifier loop
• This establishes two parallel voltage regulating feedback
paths, a fast and slow path
• Fast path is the ripple injection which ensures rapid
correction of the transient perturbation
• Slow path is the error amplifier loop which ensures the DC
component of the output voltage follows the internal
accurate reference voltage
S18-0866-Rev. D, 27-Aug-2018
VIN
VOUT
SW
Ramp
CX RX
FB
CY
RUP
COUT
Load
INPUT
PWM comp
Ripple based
controller
RDOWN
Error amp
Ref
RCOMP
CCOMP
SiC431
AGND
Fig. 5 - VM-COT Block Diagram
All components for RAMP signal generation and error
amplifier compensation required for the control loop are
internal to the IC, see Fig. 5. In order for the device to cover
a wide range of VOUT operation, the internal RAMP signal
components (RX, CX, CY) are automatically selected
depending on the VOUT voltage and switching frequency.
This method allows the RAMP amplitude to remain constant
throughout the VOUT voltage range, achieving low jitter and
fast transient Response. The error amplifier internal
compensation consists of a resistor in series with a
capacitor (RCOMP, CCOMP).
Fig. 6 demonstrates the basic operational waveforms:
VRAMP
VCOMP
PWM
Fixed on-time
Fig. 6 - VM-COT Operational Principle
Light Load Condition
To improve efficiency at light-load condition, SiC431
provides a set of innovative implementations to eliminate LS
recirculating current and switching losses. The internal zero
crossing detector monitors SW node voltage to determine
when inductor current starts to flow negatively. In power
saving mode, as soon as inductor valley current crosses
zero, the device deploys diode emulation mode by turning
off low side MOSFET. If load further decreases, switching
frequency is reduced proportional to load condition to save
switching losses while keeping output ripple within
tolerance. The switching frequency is set by the controller to
maintain regulation. In the standard power save mode, there
is no minimum switching frequency (SiC431B, SiC431D).
For SiC431A, SiC431C, the minimum switching frequency
that the regulator will reduce to is < 20 kHz as the part
avoids switching frequencies in the audible range. This light
load mode implementation is called ultrasonic mode.
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Mode Setting, Over Current Protection, Switching
Frequency, and Soft Start Selection
The SiC431 has a low pin count, minimal external
components, and offers the user flexibility to choose soft
start times, current limit settings, switching frequencies and
to enable or disable the light load mode. Two MODE pins,
MODE1 and MODE2, are user programmable by connecting
a resistor from MODEx to VDD or AGND, allowing the user to
choose various operating modes. This is best explained in
the tables below.
TABLE 1 - MODE1 CONFIGURATION SETTINGS
OPERATION
CONNECTION
Skip
fSWITCH (kHZ)
To AGND
Forced CCM
To VDD
RMODE1 (k)
300
51
500
100
750
200
1000
499
300
51
500
100
750
200
1000
499
ILIMIT (%)
RMODE2 (k)
TABLE 2 - MODE2 CONFIGURATION SETTINGS
SOFT-START TIME
CONNECTION
3 ms
6 ms
30
51
54
100
78
200
100 (32 A)
499
To AGND
30
51
54
100
78
200
100 (32 A)
499
To VDD
OUTPUT MONITORING AND PROTECTION FEATURES
Output Over Current Protection (OCP)
SiC431 has pulse-by-pulse over current limit control. The
inductor current is monitored during low side MOSFET
conduction time through RDS(on) sensing. After a pre-defined
blanking time, the inductor current is compared with an
internal OCP threshold. If inductor current is higher than
OCP threshold, high side MOSFET is kept off until the
inductor current falls below OCP threshold.
OCP is enabled immediately after VDD passes UVLO rising
threshold.
S18-0866-Rev. D, 27-Aug-2018
OCPthreshold
Iload
Iinductor
GH
Fig. 7 - Over-Current Protection Illustration
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Output Undervoltage Protection (UVP)
UVP is implemented by monitoring the FB pin. If the voltage
level at FB drops below 0.12 V for more than 25 μs, a UVP
event is recognized and both high side and low side
MOSFETs are turned off. After a duration equivalent to 20
soft start periods, the IC attempts to re-start. If the fault
condition still exists, the above cycle will be repeated.
VOUT, 2 V/div
VEN, 2 V/div
UVP is active after the completion of soft start sequence.
Output Overvoltage Protection (OVP)
VSW, 20 V/div
OVP is implemented by monitoring the FB pin. If the voltage
level at FB rising above 0.72 V, a OVP event is recognized
and both high side and low side MOSFETs are turned off.
Normal operation is resumed once FB voltage drop below
0.68 V.
Fig. 8 - Pre-Bias Start-Up
OVP is active after VDD passes UVLO rising threshold.
Over-Temperature Protection (OTP)
OTP is implemented by monitoring the junction
temperature. If the junction temperature rises above 150 °C,
a OTP event is recognized and both high side and low
MOSFETs are turned off. After the junction temperature falls
below 115 °C (35 °C hysteresis), the device restarts by
initiating a soft start sequence.
Sequencing of Input / Output Supplies
Power Good
SiC431’s power good is an open-drain output. Pull PGOOD
pin high through a > 10K resistor to use this signal. Power
good window is shown in the below diagram. If voltage on
FB pin is out of this window, PGOOD signal is de-asserted by
pulling down to AGND. To prevent false triggering during
transient events, PGOOD has a 25 μs blanking time.
VFB_Rising_Vth_OV
(typ. = 0.72 V)
SiC431 has no sequencing requirements on its supplies or
enables (VIN, VDD, VDRV, EN).
Vref (0.6 V)
The SiC431 has an enable pin to turn the part on and off.
Driving the pin high enables the device, while driving the pin
low disables the device.
Pull-high
PG
The EN pin is internally pulled to AGND by a 5 M resistor to
prevent unwanted turn on due to a floating GPIO.
Pull-low
Fig. 9 - PGOOD Window Diagram
Pre-Bias Start-Up
S18-0866-Rev. D, 27-Aug-2018
VFB_Falling_Vth_UV
VFB_Rising_Vth_UV
(typ. = 0.54 V)
(typ. = 0.58 V)
VFB
Enable
In case of pre-bias startup, output is monitored through FB
pin. If the sensed voltage on FB is higher than the internal
reference ramp value, control logic prevents high side and
low side MOSFETs from switching to avoid negative output
voltage spike and excessive current sinking through low
side MOSFET.
VFB_Falling_Vth_OV
(typ. = 0.68 V)
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ELECTRICAL CHARACTERISTICS
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 13, CIN = 10 μF x 6, unless otherwise noted)
100
VOUT = 5 V, L = 1 μH
VOUT = 3.3 V, L = 1 μH
97
92
94
84
Efficiency (%)
Efficiency (%)
100
91
88
VOUT = 1.2 V, L = 0.36 μH
85
Complete converter efficiency
PIN = VIN x IIN
POUT = VOUT x IOUT, measured at output capacitor
79
76
0
VOUT = 1.2 V, L = 0.36 μH
68
60
2
4
6
8
10 12 14
Output Current, IOUT (A)
16
44
18
0.01
0.1
Output Current, IOUT (A)
1
Fig. 13 - Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, Light Load)
100
100
VOUT = 3.3 V, L = 0.36 μH
92
94
84
Efficiency (%)
97 VOUT = 5 V, L = 0.47 μH
91
88
85
Complete converter efficiency
PIN = VIN x IIN
POUT = VOUT x IOUT, measured at output capacitor
36
0.001
20
Fig. 10 - Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, Full Load)
Efficiency (%)
VOUT = 3.3 V, L = 1 μH
76
52
82
VOUT = 1.2 V, L = 0.19 μH
VOUT = 5 V, L = 0.47 μH
VOUT = 3.3 V, L = 0.36 μH
76
68
VOUT = 1.2 V, L = 0.19 μH
60
52
82
Complete converter efficiency
PIN = VIN x IIN
POUT = VOUT x IOUT, measured at output capacitor
79
Complete converter efficiency
44 PIN = VIN x IIN
POUT = VOUT x IOUT, measured at output capacitor
36
0.001
0.01
0.1
1
Output Current, IOUT (A)
76
0
2
4
6
8
10 12 14
Output Current, IOUT (A)
16
18
20
Fig. 11 - Efficiency vs. Output Current
(VIN = 12 V, fsw = 1000 kHz, Full Load)
Fig. 14 - Efficiency vs. Output Current
(VIN = 12 V, fsw = 1000 kHz, Light Load)
608
1.4
606
1.3
604
1.2
VEN = 5.0 V
EN Current, IEN (μA)
Voltage Reference, VFB (mv)
VOUT = 5 V, L = 1 μH
602
600
598
1.1
1.0
0.9
596
0.8
594
0.7
0.6
592
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
Fig. 12 - Voltage Reference vs. Junction Temperature
S18-0866-Rev. D, 27-Aug-2018
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (°C)
Fig. 15 - EN Current vs. Junction Temperature
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1.2
2.0
1.1
1.8
Shutdown Current, IVIN_SHDN (μA)
EN Logic Threshold, VEN (V)
ELECTRICAL CHARACTERISTICS
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 13, CIN = 10 μF x 6, unless otherwise noted)
1.0
0.9
VIH_EN
0.8
0.7
0.6
VIL_EN
0.5
0.4
1.5
1.3
1.0
0.8
0.5
0.3
0.0
-60 -40 -20
0
20
40
60
80 100 120 140
0
3
6
Temperature (°C)
1.2
90
1.1
Shutdown Current, IVIN_SHDN (μA)
Input Current, IVIN (μA)
100
70
60
50
40
30
20
27
30
0.9
0.8
0.6
0.5
0.3
0.2
0.0
0
3
6
9
12 15 18 21
Input Voltage, VIN (V)
24
27
30
Fig. 17 - Input Current vs. Input Voltage
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
Fig. 20 - Shutdown Current vs. Junction Temperature
100
1.00
90
0.75
80
0.50
Line Regulation (%)
Input Current, IVIN (μA)
24
Fig. 19 - Shutdown Current vs. Input Voltage
Fig. 16 - EN Logic Threshold vs. Junction Temperature
80
9
12 15 18 21
Input Voltage, VIN (V)
70
60
50
0.25
0.00
-0.25
40
-0.50
30
-0.75
-1.00
20
-60 -40 -20
0
20 40 60 80
Temperature (°C)
100 120 140
Fig. 18 - Input Current vs. Junction Temperature
S18-0866-Rev. D, 27-Aug-2018
5
7
9
11
13 15 17 19
Input Voltage (V)
21
23
25
Fig. 21 - Line Regulation vs. Input Voltage
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ELECTRICAL CHARACTERISTICS
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 13, CIN = 10 μF x 6, unless otherwise noted)
1.00
Load Regulation (%)
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
0.0 2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Output Current (A)
Fig. 22 - Load Regulation vs. Output Current
On-State Resistance, RDSON (mΩ)
12.8
11.2
9.6
High side
8.0
6.4
4.8
Low side
3.2
1.6
0
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (°C)
Fig. 23 - On Resistance vs. Junction Temperature
S18-0866-Rev. D, 27-Aug-2018
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ELECTRICAL CHARACTERISTICS
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 13, CIN = 10 μF x 6, unless otherwise noted)
VEN, 5 V/div
VDD, 5 V/div
VDD, 5 V/div
VPGOOD, 5 V/div
VPGOOD, 5 V/div
VIN, 5 V/div
VOUT, 500 mV/div
VOUT, 500 mV/div
Fig. 24 - Startup with VIN, t = 2 ms/div
VDD, 5 V/div
Fig. 27 - Startup with EN, t = 1 ms/div
VEN, 5 V/div
VDD, 5 V/div
VPGOOD, 5 V/div
VIN, 5 V/div
VPGOOD, 5 V/div
VOUT, 500 mV/div
VOUT, 500 mV/div
Fig. 25 - Shut down with VIN, t = 100 ms/div
Fig. 28 - Shut down with EN, t = 200 ms/div
IOUT, 10 A/div
VOUT, 500 mV/div
VOUT, 500 mV/div
VSW, 10 V/div
Fig. 26 - Overcurrent Protection Behavior, t = 5 μs/div
S18-0866-Rev. D, 27-Aug-2018
VSW, 10 V/div
Fig. 29 - Output Undervoltage Protection Behavior, t = 50 ms/div
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ELECTRICAL CHARACTERISTICS
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 13, CIN = 10 μF x 6, unless otherwise noted)
VOUT, 50 mV/div
VOUT, 50 mV/div
IOUT, 10 A/div
IOUT, 10 A/div
SW, 10 V/div
Fig. 30 - Load Step, 12 A to 24 A, 1 A/μs, t = 10 μs/div
SW, 10 V/div
Fig. 33 - Load Release, 24 A to 12 A, 1 A/μs, t = 10 μs/div
VOUT, 50 mV/div
VOUT, 50 mV/div
IOUT, 10 A/div
SW, 10 V/div
Fig. 31 - Load Step, 0.1 A to 12 A, 1 A/μs, t = 10 μs/div
Skip Mode Enabled
VOUT, 50 mV/div
IOUT, 10 A/div
SW, 10 V/div
Fig. 32 - Load Step, 0.1 A to 12 A, 1 A/μs, t = 10 μs/div
Forced Continuous Conduction Mode
S18-0866-Rev. D, 27-Aug-2018
IOUT, 10 A/div
SW, 10 V/div
Fig. 34 - Load Release, 12 A to 0.1 A, 1 A/μs, t = 50 μs/div
Skip Mode Enabled
VOUT, 50 mV/div
IOUT, 10 A/div
SW, 10 V/div
Fig. 35 - Load Release, 12 A to 0.1 A, 1 A/μs, t = 20 μs/div
Forced Continuous Conduction Mode
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ELECTRICAL CHARACTERISTICS
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 13, CIN = 10 μF x 6, unless otherwise noted)
VOUT, 20 mV/div
VOUT, 20 mV/div
VSW, 10 V/div
VSW, 10 V/div
Fig. 36 - Output Ripple, 0.1 A, t = 2 μs/div
Forced Continuous Conduction Mode
Fig. 38 - Output Ripple, 12 A, t = 1 μs/div
Forced Continuous Conduction Mode
VOUT, 20 mV/div
VSW, 10 V/div
Fig. 37 - Output Ripple, 0.1 A, t = 20 μs/div
Skip Mode Enabled
S18-0866-Rev. D, 27-Aug-2018
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EXAMPLE SCHEMATIC FOR SiC431
EN
RBOOT
1R Ω
PGOOD
CBOOT
0.1 μF
RPGOOD
BOOT
PHASE
EN
VIN 1
PGOOD
10 kΩ
MODE2
VIN-PAD
VIN = 4.5 V to 24 V
RMODE2
499 kΩ
VIN 2
CIN_D
100 nF
VDD
VIN 3
RMODE1
100 kΩ
MODE1
AGND-PAD
SiC431
PGND-PAD
AGND
PGND 1
PGND 2
R_FB_L
VFB
PGND
VOUT
SW 5
SW 4
SW 3
SW 2
SW 1
VDRV
10 kΩ
GL 2
GL 1
CIN
22 μF
x2
CVDD
1 μF
R_FB_H
9.53 kΩ
LO
CVDRV
4.7 μF
300 nH
0.7 mΩ
* * Analog ground (AGND), and power ground (PGND) are tied internally
AGND
VOUT = 1.2 V at 24 A
COUT_D
100 μF
COUT_C COUT_B
100 μF 100 μF
COUT_A
100 μF
PGND
Fig. 39 - Schematic
S18-0866-Rev. D, 27-Aug-2018
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EXTERNAL COMPONENT SELECTION FOR THE SiC43X
This section explains external component selection for
the SiC43x family of regulators. Component reference
designators in any equation refer to the schematic shown in
Fig. 36.
See PowerCAD online design center to simplify external
component calculations.
Output Voltage Adjustment
If a different output voltage is needed, simply change the
value of VOUT and solve for R_FB_H based on the following
formula:
R _FB_L V OUT - VFB
R _FB_H = ----------------------------------------------------V FB
Where VFB is 0.6 V for the SiC43X. R_FB_L should be a
maximum of 10 k to prevent VOUT from drifting at no load.
Inductor Selection
In order to determine the inductance, the ripple current must
first be defined. Low inductor values allow for the use of
smaller package sizes but create higher ripple current which
can reduce efficiency. Higher inductor values will reduce the
ripple current and, for a given DC resistance, are more
efficient. However, larger inductance translates directly into
larger packages and higher cost. Cost, size, output ripple,
and efficiency are all used in the selection process.
The ripple current will also set the boundary for power save
operation. The SiC431 will typically enter power save mode
when the load current decreases to 1/2 of the ripple current.
For example, if ripple current is 4 A, power save operation
will be active for loads less than 2 A. If ripple current is set
at 40 % of maximum load current, power save will typically
start at a load which is 20 % of maximum current.
The inductor value is typically selected to provide ripple
current of 25 % to 50 % of the maximum load current. This
provides an optimal trade-off between cost, efficiency, and
transient performance. During the on-time, voltage across
the inductor is (VIN - VOUT). The equation for determining
inductance is shown below.
V IN - V OUT x D
L O = -----------------------------------------------------K x IOUT_MAX. x f SW
where, K is the maximum percentage of ripple current, D is
the duty cycle, IOUT_MAX. is the maximum load current and
fSW is the switching frequency.
Capacitor Selection
The output capacitors are chosen based upon required ESR
and capacitance. The maximum ESR requirement is
controlled by the output ripple requirement and the DC
tolerance. The output voltage has a DC value that is equal to
the valley of the output ripple plus 1/2 of the peak-to-peak
ripple. A change in the output ripple voltage will lead to a
change in DC voltage at the output.
For instance, the design goal for output voltage ripple is 3 %
(45 mV for VOUT = 1.5 V) with ripple current of 4.43 A. The
maximum ESR value allowed is shown by the following
equation.
V RIPPLE
45 mV
ESR MAX. = --------------------- = ----------------I RIPPLE
4.43 A
The output capacitance is usually chosen to meet transient
requirements. A worst-case load release (from maximum
load to no load) at the moment of peak inductor current,
determines the required capacitance. If the load release is
instantaneous (maximum load to no load in less than 1 μs)
the output capacitor must absorb all the inductor’s stored
energy. The output capacitor can be calculated according to
the following equation.
2
C OUT_MIN.
L O I OUT + 0.5 x I RIPPLE
MAX.
= -----------------------------------------------------------------------------2
2
V PK - VOUT
Where IOUT is the output current, IRIPPLE_MAX. is the
maximum ripple current, VPK is the peak VOUT during load
release, VOUT is the output voltage.
The duration of the load release is determined by VOUT and
the inductor. During load release, the voltage across the
inductor is approximately -VOUT, causing a down-slope or
falling di/dt in the inductor. If the di/dt of the load is not
much larger than di/dt of the inductor, then the inductor
current will tend to track the falling load current. This will
reduce the excess inductive energy that must be absorbed
by the output capacitor; therefore a smaller capacitance can
be used.
Under this circumstance, the following equation can be
used to calculate the needed capacitance for a given rate of
load release (diLOAD/dt).
2
L x I PK
dT
--------------------- - I PK x I RELEASE x ------------------V OUT
di LOAD
C OUT = ---------------------------------------------------------------------------------------------------2 V PK - VOUT
1
I PK = I RELEASE + --- x I RIPPLE
2
MAX.
S18-0866-Rev. D, 27-Aug-2018
ESR MAX. = 10.2 m
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Where IPK is the peak inductor current, IRIPPLE_MAX. is the
maximum peak to peak inductor current, IRELEASE is the
maximum load release current, VPK is the peak VOUT during
load release, dILOAD /dt is the rate of load release.
If the load step does not meet the requirement, increasing
the crossover frequency can help by adding feed forward
capacitor (CFF) in parallel to the upper feedback resistor to
generate another zero and pole. Placing the geometrical
mean of this pole and zero around the crossover frequency
will result in faster transient response. fZ and fP are the
generated zero and pole, see equations below.
1
f Z = --------------------------------------------2 x R FB1 x C FF
Input Capacitance
In order to determine the minimum capacitance the input
voltage ripple needs to be specified; VCINPKPK 500 mV is a
suitable starting point. This magnitude is determined by the
final application specification. The input current needs to be
determined for the lowest operating input voltage,
I CIN RMS =
IO x
2
V OUT
2
1
D x 1 – D + ------ ------------------------------------- 1 – D D
L ƒ sw I OUT
12
The minimum input capacitance can then be found,
1
f P = ----------------------------------------------------------------------2 x RFB1 // R FB2 x C FF
D x 1 - D
C IN_min. = I OUT x ----------------------------------------V CINPKPK x f sw
Where RFB1 is the upper feedback resistor, RFB2 is the lower
feedback resistor CFF is the feed forward capacitor, fZ is the
zero from feed forward capacitor, fP is the pole frequency
generated from the feed forward capacitor.
A calculator is available to assist user to obtain the value of
the feed forward capacitance value.
If high ESR capacitors are used, it is good practice to also
add low ESR ceramic capacitance. A 4.7 μF ceramic input
capacitance is a suitable starting point.
Care must be taken to account for voltage derating of the
capacitance when choosing an all ceramic input
capacitance.
From the calculator, obtain the crossover frequency (fC). Use
the equation below for the calculation of the feed forward
capacitance value.
fC = fZ x fP
1
C FF = ----------------------------------------------------------------------------------------------------2 x f C x R FB1 x R FB1 // R FB2
As the internal RC compensation of the SiC431 works with
a wide range of output LC filters, the SiC431 offers stable
operation for a wide range of output capacitance, making
the product versatile and usable in a wide range of
applications.
S18-0866-Rev. D, 27-Aug-2018
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PCB LAYOUT RECOMMENDATIONS
Step 1: VIN/GND Planes and Decoupling
Step 3: VDD/VDRV Input Filter
VIN plane
AGND
CVDD
PGND
PGND plane
CVDRV
SW
1. Layout VIN and PGND planes as shown above
2. Ceramic capacitors should be placed between VIN and
PGND, and very close to the device for best decoupling
effect
3. Various ceramic capacitor values and package sizes
should be used to cover entire decoupling spectrum e.g.
1210 and 0603
4. Smaller capacitance values, closer to VIN pin(s), provide
better high frequency response
1. CVDD cap should be placed between VDD and AGND to
achieve best noise filtering
2. CVDRV cap should be placed close to VDRV and PGND pins
to reduce effects of trace impedance and provide
maximum instantaneous driver current for low side
MOSFET during switching cycle
Step 4: BOOT Resistor and Capacitor Placement
Step 2: SW Plane
PGND plane
Cboot
Snubber
Rboot
SW
1. Connect output inductor to device with large plane to
lower resistance
2. If a snubber network is required, place the components
on the bottom layer as shown above
S18-0866-Rev. D, 27-Aug-2018
1. CBOOT and RBOOT need to be placed very close to the
device, between PHASE and BOOT pins
2. In order to reduce parasitic inductance, it is
recommended to use 0402 chip size for the resistor and
the capacitor
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3. SW pad is a noise source and it is not recommended to
place vias on this pad
Step 5: Signal Routing
4. 8 mil vias on pads and 10 mil vias on planes are ideal via
sizes. The vias on pad may drain solder during assembly
and cause assembly issues. Please consult with the
assembly house for guideline
Step 7: Ground Connection
AGND
plane
PGND
V
o
u
t
s
i
g
n
a
l
1. Separate the small analog signal from high current path.
As shown above, the high paths with high dv/dt, di/dt are
placed on the left side of the IC, while the small control
signals are placed on the right side of the IC. All the
components for small analog signal should be placed
closer to IC with minimum trace length
2. IC analog ground (AGND), pin 16, should have a single
connection to PGND. The AGND ground plane connected
to pin16 helps to keep AGND quiet and improves noise
immunity
Vias
Vias
1. In order to minimize the ground voltage drop due to high
current, it is recommended to place vias on the PGND
planes. Make use of the inner ground layers to lower the
impedance
Step 7: Ground Layer
3. The output signal can be routed through inner layers.
Make sure this signal is far away from SW node and
shielded by an inner ground layer
AGND plane
Step 6: Thermal Management
VIN plane
PGND plane
1. It is recommended to make the whole inner 1 layer (next
to top layer) ground plane
PGND plane
SW
1. Thermal relief vias can be added to the VIN and PGND
pads to utilize inner layers for high current and thermal
dissipation
2. This ground plane provides shielding between noise
source on top layer and signal trace within inner layer
3. The ground plane can be broken into two section, PGND
and AGND
2. To achieve better thermal performance, additional vias
can be placed on VIN and PGND planes. It is also
necessary to duplicate the VIN and ground plane at
bottom layer to maximize the power dissipation
capability of the PCB
S18-0866-Rev. D, 27-Aug-2018
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PRODUCT SUMMARY
Part number
SiC431A
SiC431B
SiC431C
SiC431D
Description
24 A, 4.5 V to 24 V input,
300 kHz, 500 kHz,
750 kHz, 1 MHz,
synchronous buck
regulator with ultrasonic
mode and internal 5 V
bias
24 A, 4.5 V to 24 V input,
300 kHz, 500 kHz,
750 kHz, 1 MHz,
synchronous buck
regulator with power save
mode and internal 5 V
bias
24 A, 3 V to 24 V input,
300 kHz, 500 kHz,
750 kHz, 1 MHz,
synchronous buck
regulator with ultrasonic
mode (external 5 V bias)
24 A, 3 V to 24 V input,
300 kHz, 500 kHz,
750 kHz, 1 MHz,
synchronous buck
regulator with power save
mode (external 5 V bias)
Input voltage min. (V)
4.5
4.5
3.0
3.0
Input voltage max. (V)
24
24
24
24
Output voltage min. (V)
0.6
0.6
0.6
0.6
Output voltage max. (V)
0.90 x VIN
0.90 x VIN
0.90 x VIN
0.90 x VIN
Continuous current (A)
24
24
24
24
Switch frequency min. (kHz)
300
300
300
300
Switch frequency max. (kHz)
1000
1000
1000
1000
Pre-bias operation (yes / no)
Y
Y
Y
Y
Internal bias reg. (yes / no)
Y
Y
N
N
Compensation
Internal
Internal
Internal
Internal
Enable (yes / no)
Y
Y
Y
Y
PGOOD (yes / no)
Y
Y
Y
Y
Over current protection
Y
Y
Y
Y
Protection
OVP, OCP, UVP/SCP,
OTP, UVLO
OVP, OCP, UVP/SCP,
OTP, UVLO
OVP, OCP, UVP/SCP,
OTP, UVLO
OVP, OCP, UVP/SCP,
OTP, UVLO
Light load mode
Selectable ultrasonic
Selectable powersave
Selectable ultrasonic
Selectable powersave
97
97
97
97
PowerPAK MLP 44-24L
PowerPAK MLP 44-24L
PowerPAK MLP 44-24L
PowerPAK MLP 44-24L
4 x 4 x 0.75
4 x 4 x 0.75
4 x 4 x 0.75
4 x 4 x 0.75
Peak efficiency (%)
Package type
Package size (W, L, H) (mm)
Status code
1
1
1
1
Product type
microBUCK (step down
regulator)
microBUCK (step down
regulator)
microBUCK (step down
regulator)
microBUCK (step down
regulator)
Applications
Computers, consumer,
industrial, healthcare,
networking
Computers, consumer,
industrial, healthcare,
networking
Computers, consumer,
industrial, healthcare,
networking
Computers, consumer,
industrial, healthcare,
networking
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?74589.
S18-0866-Rev. D, 27-Aug-2018
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Package Information
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PowerPAK® MLP44-24L Case Outline
0.08 C
A1
A2
K5
b
MILLIMETERS
NOM.
0.75
0.20 ref.
0.25
0.20
4.00
0.45 BSC
0.70 BSC
0.90 BSC
4.00
0.40
24
1.05
1.50
2.73
2.07
0.52
1.00
1.15
0.38
1.00
0.32
0.40 ref.
0.57 ref.
0.35 ref.
0.35 ref.
0.35 ref.
0.525 ref.
0.725 ref.
0.575 ref.
0.975 ref.
Side view
MAX.
0.80
0.05
D2-2
K
D2-1 L1
1
15
14
13
D2-3
K1
K3
12
11
K7
0.10 C A
K4
22 23 24
L1
2
3
D2-4
D2-5
4
10 9 8
6 5
e e e1 7
K5
e x 2 = 0.9
Bottom view
MIN.
0.027
0.000
INCHES
NOM.
0.029
0.008 ref.
0.010
0.008
0.157
0.018 BSC
0.028 BSC
0.035 BSC
0.157
0.016
24
0.041
0.059
0.108
0.081
0.020
0.039
0.045
0.015
0.039
0.013
0.016 ref.
0.022 ref.
0.014 ref.
0.014 ref.
0.014 ref.
0.021 ref.
0.029 ref.
0.023 ref.
0.038 ref.
MAX.
0.031
A (8)
A1
0.002
A2
b (4)
0.20
0.30
0.008
0.012
b1
0.15
0.25
0.006
0.010
D
3.90
4.10
0.155
0.159
e
e1
e2
E
3.90
4.10
0.154
0.161
L
0.35
0.45
0.014
0.018
N (3)
D2-1
1.00
1.10
0.039
0.043
D2-2
1.45
1.55
0.057
0.061
D2-3
2.68
2.78
0.106
0.110
D2-4
2.02
2.12
0.079
0.083
D2-5
0.47
0.57
0.018
0.022
E2-1
0.95
1.05
0.037
0.041
E2-2
1.10
1.20
0.043
0.047
E2-3
0.33
0.43
0.013
0.017
E2-4
0.95
1.05
0.037
0.041
E2-5
0.27
0.37
0.011
0.015
K
K1
K2
K3
K4
K5
K6
K7
K8
ECN: T17-0551-Rev. B, 16-Oct-17
DWG: 6055
Notes
(1) Use millimeters as the primary measurement
(2) Dimensioning and tolerances conform to ASME Y14.5M. - 1994
(3) N is the number of terminals
(4) Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip
(5) The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
(6) Exact shape and size of this feature is optional
(7) Package warpage max. 0.08 mm
(8) Applied only for terminals
Revision: 16-Oct-17
MIN.
0.70
0.00
e x 2 = 0.9
K5
16
K8
2x
DIM.
17
K2
(4)
Top view
e1
e
e
e2
E2-2 K4 E2-1 K4 L
18 19 20 21
MLP44-24L
(4 mm x 4 mm)
B
e x 3 = 1.35
b1
E2-5
0.10 C A
0.10 M C A B
D
K6
e x 6 = 2.7
K4 E2-4 K4
E2-3
E
A
L K4
A
2x
(5) (6)
Pin 1 dot
by marking
Document Number: 74345
1
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PAD Pattern
www.vishay.com
Vishay Siliconix
Recommended Land Pattern PowerPAK® MLP44-24L
24
18
17
1
4
11
5
10
4
0.525
0.45 x 2 = 0.9
0.7
0.45 x 3 = 1.35
0.45
0.525
0.3
18
0.45 x 6 = 2.7
0.3
0.455
0.65
0.27 0.58
0.3
0.38
1.2
0.55
0.45
0.3
0.45
0.725
2.175
11
0.3
0.575
4
1.025
0.5
0.27
0.3
0.3
2.825
0.73 0.39
0.45
1
0.45
0.9
17
0.3
1.575
1.05
0.3
4
0.3
0.725
1.15
0.3
0.25
0.3
1.175
0.725
0.3
24
0.725
5
10
0.3
0.525
0.9
0.7
0.45
0.45
0.975
All dimensions are in millimeters
Revision: 15-Aug-17
Document Number: 78231
1
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Legal Disclaimer Notice
www.vishay.com
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
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Document Number: 91000
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