SiC437, SiC438
www.vishay.com
Vishay Siliconix
3 V to 28 V Input, 8 A, 12 A
microBUCK® DC/DC Converter
FEATURES
LINKS TO ADDITIONAL RESOURCES
Simulation
Tool
Evaluation
Boards
Design Tools
DESCRIPTION
The SiC43x are synchronous buck regulators with
integrated high side and low side power MOSFETs. Its
power stage is capable of supplying 12 A (SiC437) and 8 A
(SiC438) continuous current at up to 1 MHz switching
frequency. This regulator produces an adjustable output
voltage down to 0.6 V from 3 V to 28 V input rail to
accommodate a variety of applications, including
computing, consumer electronics, telecom, and industrial.
SiC437’s and SiC438’s architecture delivers ultrafast
transient response with minimum output capacitance and
tight ripple regulation at very light load. The device is
internally compensated and is stable with any capacitor. No
external ESR network is required for loop stability purposes.
The device also incorporates a power saving scheme that
significantly increases light load efficiency.
The regulator family integrates a full protection feature set,
including output overvoltage protection (OVP), cycle by
cycle overcurrent protection (OCP) short circuit protection
(SCP) and thermal shutdown (OTP). It also has UVLO and a
user programmable soft start.
The SiC437 and SiC438 are available in lead (Pb)-free power
enhanced MLP-44L package in 4 mm x 4 mm dimension.
APPLICATIONS
•
•
•
•
5 V, 12 V, and 24 V input rail POLs
Desktop, notebooks, server, and industrial computing
Industrial and automation
consumer electronics
• Versatile
- Operation from 3 V to 28 V input voltage
- Adjustable output voltage down to 0.6 V
- Scalable solution 8 A (SiC438), 12 A (SiC437),
and 24 A (SiC431)
- Output voltage tracking and sequencing with pre-bias
start up
- ± 1 % output voltage accuracy at -40 °C to +125 °C
• Highly efficient
- 97 % peak efficiency
- 1 μA supply current at shutdown
- 50 μA operating current not switching
• Highly configurable
- Four programmable switching frequencies available:
300 kHz, 500 kHz, 750 kHz, and 1 MHz
- Adjustable soft start and adjustable current limit
- Three modes of operation: forced continuous
conduction, power save (SiC43xB, SiC43xD), or
ultrasonic (SiC43xA, SiC43xC)
• Robust and reliable
- Cycle-by-cycle current limit
- Output overvoltage protection
- Output undervoltage / short circuit protection with auto
retry
- Power good flag and over temperature protection
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
TYPICAL APPLICATION CIRCUIT AND PACKAGE OPTIONS
Axis Title
100
10000
98
CIN
CBOOT
Phase
SiC43x
VOUT
SW
GL
VDRV
MODE1
VOUT
MODE2
VFB
PGND
AGND
RUP
RDOWN
94
VOUT = 5 V, L = 1.5 µH
1000
92
1st line
2nd line
VDD
96
BOOT
2nd line
eff - Efficiency (%)
VIN
PGOOD
EN
INPUT
3.0 VDC to 24 VDC
90
88
VOUT = 1.2 V, L = 0.56 µH
86
100
84
COUT
82
10
80
0
1
2
3
4
5
6
7
8
9 10 11 12
IOUT - Output Current (A)
Fig. 1 - Typical Application Circuit
S20-0679-Rev. D, 27-Aug-2020
Fig. 2 - Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, Power Saving Mode)
Document Number: 75921
1
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
17 FB
16 AGND
VIN 2
15 VDD
VDD 15
PGOOD 14
PGND 3
13 PGND
PGND 13
PGND 4
12 VDRV
VDRV 12
23 BOOT
22 VIN
21 MODE1
24 PHASE
1 VIN
2 VIN
27
PGND
3 PGND
4 PGND
SW 5
SW 6
SW 7
SW 8
SW 9
28
GL
GL 10
SW 9
26
VIN
GL 11
GL 10
SW 8
11 GL
SW 7
25
AGND
AGND 16
14 PGOOD
SW 6
20 MODE2
FB 17
VIN 1
SW 5
19 EN
18 VOUT
18 VOUT
19 EN
20 MODE2
21 MODE1
22 VIN
23 BOOT
Pin 1 indicator
24 PHASE
PIN CONFIGURATION
Fig. 3 - SiC43x Pin Configuration
PIN DESCRIPTION
PIN NUMBER
SYMBOL
1, 2, 22, 26
3, 4, 13, 27
5 to 9
10, 11, 28
12
14
15
16, 25
17
18
19
20
VIN
PGND
SW
GL
VDRV
PGOOD
VDD
AGND
FB
VOUT
EN
MODE2
Input voltage
Power signal return ground
Switching node signal; output inductor connection point
Low side power MOSFET gate signal
Supply voltage for internal gate driver. Connect a 2.2 μF decoupling capacitor to PGND
Power good signal output; open drain
Supply voltage for internal logic. Connect a 1 μF decoupling capacitor to AGND
Analog signal return ground
Output voltage feedback pin; connect to VOUT through a resistor divider network.
Output voltage sense pin
Enable pin
Soft start and current limit selection; connect a resistor to VDD or AGND per table 2
DESCRIPTION
21
23
24
MODE1
BOOT
PHASE
Operating mode and switching frequency selection; connect a resistor to VDD or AGND per table 1
Bootstrap pin; connect a capacitor to PHASE pin for HS power MOSFET gate voltage supply
Switching node signal for bootstrap return path
ORDERING INFORMATION
PART NUMBER
SiC437AED-T1-GE3
PART
MARKING
MAXIMUM
CURRENT
SiC437A
SiC437BED-T1-GE3
SiC437B
SiC437CED-T1-GE3
SiC437C
SiC437DED-T1-GE3
SiC437D
SiC438AED-T1-GE3
SiC438A
SiC438BED-T1-GE3
SiC438B
SiC438CED-T1-GE3
SiC438C
SiC438DED-T1-GE3
SiC438D
S20-0679-Rev. D, 27-Aug-2020
VDD, VDRV
Internal
12 A
External
Internal
8A
External
LIGHT LOAD
MODE
OPERATING
JUNCTION
TEMPERATURE
PACKAGE
-40 °C to +125 °C
PowerPAK® MLP44-24L
Ultrasonic
Power saving
Ultrasonic
Power saving
Ultrasonic
Power saving
Ultrasonic
Power saving
Document Number: 75921
2
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
ELECTRICAL PARAMETER
CONDITIONS
LIMITS
VIN
Reference to PGND
-0.3 to +30
VOUT
Reference to PGND
-0.3 to +22
VDD / VDRV
Reference to PGND
-0.3 to +6
SW / PHASE
Reference to PGND
-0.3 to +30
SW / PHASE (AC)
100 ns;
reference to PGND
-8 to +35
BOOT
Reference to PGND
-0.3 to +6
BOOT to SW
UNIT
V
-0.3 to +6
AGND to PGND
-0.3 to +0.3
EN
Reference to AGND
-0.3 to +30
All other pins
Reference to AGND
-0.3 to +6
Junction temperature
TJ
-40 to +150
Storage temperature
TSTG
-65 to +150
Temperature
°C
Power Dissipation
Junction to ambient thermal impedance (RJA)
16
Junction to case thermal impedance (RJC)
2
Maximum power dissipation
Ambient temperature = 25 °C
°C/W
7.75
W
ESD Protection
Electrostatic discharge protection
Human body model
4000
Charged device model
1000
V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating/conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (all voltages referenced to GND = 0 V)
PARAMETER
MIN.
TYP.
MAX.
Input voltage (VIN) (SiC43xA, SiC43xB)
4.5
-
28
Input voltage (VIN) (SiC43xC, SiC43xD)
3
-
28
4.5
-
28
Enable (EN)
0
-
28
Input voltage (VIN), external supply on VDD / VDRV
3
-
28
-
0.9 x VIN
and < 20 V
Logic supply voltage, gate driver supply voltage (VDD, VDRV)
(SiC43xC, SiC43xD)
Output voltage (VOUT)
0.6
UNIT
V
Temperature
Recommended ambient temperature
-40 to +105
Operating junction temperature
-40 to +125
S20-0679-Rev. D, 27-Aug-2020
°C
Document Number: 75921
3
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
ELECTRICAL SPECIFICATIONS (VIN = 12 V, VEN = 5 V, TJ = -40 °C to +125 °C, unless otherwise stated)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
VDD
VIN = 6 V to 28 V
(SiC43xA, SiC43xB)
4.75
5
5.25
3.3
3.6
3.9
UNIT
Power Supplies
VDD supply
VDD UVLO threshold, rising
VDD_UVLO
V
VDD UVLO hysteresis
VDD_UVLO_HYST
-
300
-
mV
Maximum VDD current
IDD
VIN = 6 V to 28 V
3
-
-
mA
VDRV supply
VDRV
VIN = 6 V to 28 V
(SiC43xA, SiC43xB)
4.75
5
5.25
V
Maximum VDRV current
IDRV
VIN = 6 V to 28 V
50
-
-
mA
Input current
IVIN
Non-switching, VFB > 0.6 V
-
50
120
IVIN_SHDN
VEN = 0 V
-
0.5
3
Shutdown current
μA
Controller and Timing
Feedback voltage
VFB
VFB input bias current
IFB
Minimum on-time
tON accuracy
On-time range
TJ = 25 °C
597
600
603
TJ = -40 °C to +125 °C (1)
594
600
606
-
2
-
nA
ns
m/V
tON_MIN.
-
50
65
tON_ACCURACY
-10
-
10
%
tON_RANGE
65
-
2250
ns
Ultrasonic version (SiC43xA, SiC43xC)
20
-
30
Power save version (SiC43xB, SiC43xD)
0
-
-
205
250
305
-
10.1
-
-
3.9
-
-
10.1
-
-
5.5
-
-20
-
20
-
20
-
Minimum frequency, skip mode
fSW_MIN.
Minimum off-time
tOFF_MIN.
kHz
ns
Power MOSFETs (SiC437)
High side on resistance
RON_HS
Low side on resistance
RON_LS
VDRV = 5 V, TA = 25 °C
m
Power MOSFETs (SiC438)
High side on resistance
RON_HS
Low side on resistance
RON_LS
VDRV = 5 V, TA = 25 °C
m
Fault Protections
Over current protection
(inductor valley current)
IOCL_P
Output OVP threshold
VOVP
Output UVP threshold
Over temperature protection
VUVP
TJ = -10 °C to +125 °C
VFB with respect to 0.6 V reference
-
-80
-
TOTP_RISING
Rising temperature
-
150
-
TOTP_HYST
Hysteresis
-
25
-
%
°C
Power Good
Power good output threshold
Power good hysteresis
VFB_RISING_VTH_OV
VFB rising above 0.6 V reference
-
20
-
VFB_FALLING_VTH_UV
VFB falling below 0.6 V reference
-
-10
-
-
40
-
VFB_HYST
%
mV
Power good on resistance
RON_PGOOD
-
7.5
15
Power good delay time
tDLY_PGOOD
15
25
35
μs
EN logic high level
VEN_H
1.6
-
-
EN logic low level
VEN_L
-
-
0.4
REN
-
5
-
-
51
55
EN / MODE / Ultrasonic Threshold
EN pull down resistance
V
M
Switching Frequency
fsw = 300 kHz
MODE1 (switching frequency)
S20-0679-Rev. D, 27-Aug-2020
RMODE1
fsw = 500 kHz
90
100
110
fsw = 750 kHz
180
200
220
fsw = 1000 kHz
450
499
550
k
Document Number: 75921
4
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
ELECTRICAL SPECIFICATIONS (VIN = 12 V, VEN = 5 V, TJ = -40 °C to +125 °C, unless otherwise stated)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
Connect RMODE2 between
MODE2 and AGND
1.8
3
4.2
Connect RMODE2 between
MODE2 and VDD
3.6
6
8.4
UNIT
Soft Start
Soft start time
tss
ms
Over Current Protection - SiC437
MODE 2 (over current protection)
RMODE2
IOCP = 18 A
450
499
550
IOCP = 14 A
180
200
220
IOCP = 9.7 A
90
100
110
IOCP = 5.4 A
-
51
55
k
Over Current Protection - SiC438
MODE 2 (over current protection)
RMODE2
IOCP = 12 A
450
499
550
IOCP = 9.3 A
180
200
220
IOCP = 6.5 A
90
100
110
IOCP = 3.6 A
-
51
55
k
Note
(1) Guaranteed by design
FUNCTIONAL BLOCK DIAGRAM
VOUT
VIN
VDRV
Sync
rectifier
Regulator
Rr
VDD
BOOT
UVLO
EN
Enable
MODE1
PH
Over voltage
under voltage
Control
logic
VDRV
SW
VOUT
Ramp
On time
generator
EA
FB
SW
Reference
Rc
Zero
crossing
GL
PGOOD
Cc
Soft start
Over
current
MODE2
Over
temperature
Power good
AGND
PGND
Fig. 4 - SiC43x Functional Block Diagram
S20-0679-Rev. D, 27-Aug-2020
Document Number: 75921
5
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
OPERATIONAL DESCRIPTION
Device Overview
The SiC43x is high efficiency synchronous buck regulators
capable of delivering up to 8 A (SiC438) and 12 A (SiC437)
continuous current. The device has user programmable
switching frequency of 300 kHz, 500 kHz, 750 kHz, and
1 MHz. The control scheme delivers fast transient response
and minimizes the number of external components. Thanks
to the internal ramp information, no high ESR output bulk or
virtual ESR network is required for the loop stability. This
device also incorporates a power saving feature that
enables diode emulation mode and frequency fold back as
the load decreases.
SiC43x has a full set of protection and monitoring features:
• Over current protection in pulse-by-pulse mode
• Output over voltage protection
• Output under voltage protection with device latch
• Over temperature protection with hysteresis
• Dedicated enable pin for easy power sequencing
• Power good open drain output
This device is available in MLP44-24L package to deliver
high power density and minimize PCB area.
Power Stage
SiC43x integrates a high performance power stage with a
low on resistance and gate charge, high side and low
side MOSFETs. The MOSFETs are optimized to achieve up
to 97 % efficiency.
The input voltage (VIN) can go up to 28 V and down to as low
as 3 V for power conversion. For input voltages (VIN) below
4.5 V an external VDD and VDRV supply is required (SiC43xC,
SiC43xD). For input voltages (VIN) above 4.5 V only a single
input supply is required (SiC43xA, SiC43xB).
Control Mechanism
SiC43x employs an advanced voltage - mode COT control
mechanism. During steady-state operation, feedback
voltage (VFB) is compared with internal reference (0.6 V typ.)
and the amplified error signal (VCOMP) is generated at the
internal comp node. An internally generated ramp signal and
VCOMP feed into a comparator. Once VRAMP crosses VCOMP,
an on-time pulse is generated for a fixed time. During the
on-time pulse, the high side MOSFET will be turned on.
Once the on-time pulse expires, the low side MOSFET will
be turned on after a dead time period. The low side MOSFET
will stay on for a minimum duration equal to the minimum
off-time (tOFF_MIN.) and remains on until VRAMP crosses
VCOMP. The cycle is then repeated.
Fig. 5 illustrates the basic block diagram for VM-COT
architecture. In this architecture the following is achieved:
• The reference of a basic ripple control regulator is
replaced with a high again error amplifier loop
• This establishes two parallel voltage regulating feedback
paths, a fast and slow path
• Fast path is the ripple injection which ensures rapid
correction of the transient perturbation
S20-0679-Rev. D, 27-Aug-2020
• Slow path is the error amplifier loop which ensures the DC
component of the output voltage follows the internal
accurate reference voltage
VOUT
L
VIN
VOUT
SW
Ramp
Cinj2 Rinj Cinj1
PWM
Comp Error Amp
INPUT
Ripple based
controller
SiC43x
FB
RUP
RDOWN
Load
COUT
Ref.
RCOMP
CCOMP
AGND
Fig. 5 - VM-COT Block Diagram
All components for RAMP signal generation and error
amplifier compensation required for the control loop are
internal to the IC, see Fig. 5. In order for the device to cover
a wide range of VOUT operation, the internal RAMP signal
components (RX, CX, CY) are automatically selected
depending on the VOUT voltage and switching frequency.
This method allows the RAMP amplitude to remain constant
throughout the VOUT voltage range, achieving low jitter and
fast transient Response. The error amplifier internal
compensation consists of a resistor in series with a
capacitor (RCOMP, CCOMP).
Fig. 6 demonstrates the basic operational waveforms:
VRAMP
VCOMP
PWM
Fixed on-time
Fig. 6 - VM-COT Operational Principle
Light Load Condition
To improve efficiency at light-load condition, SiC437,
SiC438 provide a set of innovative implementations to
eliminate LS recirculating current and switching losses. The
internal zero crossing detector monitors SW node voltage to
determine when inductor current starts to flow negatively. In
power saving mode, as soon as inductor valley current
crosses zero, the device deploys diode emulation mode by
turning off low side MOSFET. If load further decreases,
switching frequency is reduced proportional to load
condition to save switching losses while keeping output
ripple within tolerance. The switching frequency is set by the
controller to maintain regulation. In the standard power save
mode, there is no minimum switching frequency (SiC43xB,
SiC43xD). For SiC43xA, SiC43xC, the minimum switching
frequency that the regulator will reduce to is > 20 kHz as the
part avoids switching frequencies in the audible range. This
light load mode implementation is called ultrasonic mode.
Document Number: 75921
6
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
MODE SETTING, OVER CURRENT PROTECTION, SWITCHING FREQUENCY, AND SOFT START
SELECTION
The SiC437, SiC438 has a low pin count, minimal external
components, and offers the user flexibility to choose soft
start times, current limit settings, switching frequencies and
to enable or disable the light load mode. Two MODE pins,
MODE1 and MODE2, are user programmable by connecting
a resistor from MODEx to VDD or AGND, allowing the user to
choose various operating modes. This is best explained in
the tables below.
TABLE 1 - MODE1 CONFIGURATION SETTINGS
OPERATION
Skip
Forced CCM
CONNECTION
fSWITCH (kHz)
RMODE1 (k)
300
51
500
100
750
200
1000
499
to AGND
to VDD
300
51
500
100
750
200
1000
499
ILIMIT (%)
RMODE2 (k)
TABLE 2 - MODE2 CONFIGURATION SETTINGS
SOFT-START TIME
3 ms
6 ms
CONNECTION
30
51
54
100
78
200
100 % (18 A on SiC437)
100 % (12 A on SiC438)
499
to AGND
30
51
54
100
78
200
100 % (18 A on SiC437)
100 % (12 A on SiC438)
499
to VDD
OUTPUT MONITORING AND PROTECTION FEATURES
Output Overcurrent Protection (OCP)
SiC437, SiC438 has pulse-by-pulse over current limit
control. The inductor current is monitored during low side
MOSFET conduction time through RDS(on) sensing. After a
pre-defined blanking time, the inductor current is compared
with an internal OCP threshold. If inductor current is higher
than OCP threshold, high side MOSFET is kept off until the
inductor current falls below OCP threshold.
OCP is enabled immediately after VDD passes UVLO rising
threshold.
OCPthreshold
Iload
Iinductor
GH
Fig. 7 - Over-Current Protection Illustration
S20-0679-Rev. D, 27-Aug-2020
Document Number: 75921
7
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
Output Undervoltage Protection (UVP)
UVP is implemented by monitoring the FB pin. If the voltage
level at FB drops below 0.12 V for more than 25 μs, a UVP
event is recognized and both high side and low side
MOSFETs are turned off. After a duration equivalent to
20 soft start periods, the IC attempts to re-start. If the fault
condition still exists, the above cycle will be repeated.
UVP is active after the completion of soft start sequence.
Output Overvoltage Protection (OVP)
OVP is implemented by monitoring the FB pin. If the voltage
level at FB rising above 0.72 V, a OVP event is recognized
and both high side and low side MOSFETs are turned off.
Normal operation is resumed once FB voltage drop below
0.68 V.
Fig. 8 - Pre-Bias Start-Up
OOVP is active after VDD passes UVLO rising threshold.
Power Good
Over-Temperature Protection (OTP)
OTP is implemented by monitoring the junction
temperature. If the junction temperature rises above 150 °C,
a OTP event is recognized and both high side and low
MOSFETs are turned off. After the junction temperature falls
below 125 °C (25 °C hysteresis), the device restarts by
initiating a soft start sequence.
SiC437, SiC438 power good is an open-drain output. Pull
PGOOD pin high through a > 10 k resistor to use this signal.
Power good window is shown in the below diagram. If
voltage on FB pin is out of this window, PGOOD signal is
de-asserted by pulling down to AGND. To prevent false
triggering during transient events, PGOOD has a 25 μs
blanking time.
Sequencing of Input / Output Supplies
SiC437, SiC438 have no sequencing requirements on its
supplies or enables (VIN, VDD, VDRV, EN).
VFB_Rising_Vth_OV
(typ. = 0.72 V)
VFB_Falling_Vth_OV
(typ. = 0.68 V)
Vref (0.6 V)
Enable
VFB_Falling_Vth_UV
VFB_Rising_Vth_UV
(typ. = 0.54 V)
(typ. = 0.58 V)
VFB
The SiC437, SiC438 have an enable pin to turn the part on
and off.
Pull-high
Driving the pin high enables the device, while driving the pin
low disables the device.
PG
The EN pin is internally pulled to AGND by a 5 M resistor to
prevent unwanted turn on due to a floating GPIO.
Pull-low
Fig. 9 - PGOOD Window Diagram
Pre-Bias Start-Up
In case of pre-bias startup, output is monitored through FB
pin. If the sensed voltage on FB is higher than the internal
reference ramp value, control logic prevents high side and
low side MOSFETs from switching to avoid negative output
voltage spike and excessive current sinking through low
side MOSFET.
S20-0679-Rev. D, 27-Aug-2020
Document Number: 75921
8
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 7, CIN = 10 μF x 6, unless otherwise noted)
Axis Title
Axis Title
100
100
10000
VOUT = 5 V, L = 1.5 µH
98
94
90
VOUT = 1.2 V, L = 0.56 µH
88
100
86
84
91
VOUT = 5 V, L = 1.5 µH
1000
88
1st line
2nd line
1000
92
2nd line
eff - Efficiency (%)
94
1st line
2nd line
85
82
79
100
VOUT = 1.2 V, L = 0.56 µH
76
82
73
10
80
0
1
2
3
4
5
6
7
8
70
0.01
9 10 11 12
IOUT - Output Current (A)
10
0.1
1
IOUT - Output Current (A)
Fig. 13 - SiC437 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, Light Load)
Fig. 10 - SiC437 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, Full Load)
Axis Title
Axis Title
100
100
10000
10000
95
98
90
96
1000
1st line
2nd line
92
90
VOUT = 1.2 V, L = 0.56 µH
88
100
86
2nd line
eff - Efficiency (%)
VOUT = 5 V, L = 1.5 µH
94
VOUT = 5 V, L = 1.5 µH
85
80
75
1000
VOUT = 1.2 V, L = 0.56 µH
1st line
2nd line
2nd line
eff - Efficiency (%)
96
2nd line
eff - Efficiency (%)
10000
97
70
65
60
100
55
84
50
82
45
10
80
0
1
2
3
4
5
6
7
8
40
0.01
9 10 11 12
1
IOUT - Output Current (A)
IOUT - Output Current (A)
Fig. 11 - SiC437 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, Ultrasonic Mode, Full Load)
Fig. 14 - SiC437 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, Ultrasonic Mode, Light Load)
Axis Title
Axis Title
100
10000
97
96
94
94
1000
1st line
2nd line
92
VOUT = 1.2 V, L = 0.56 µH
90
88
100
86
84
2nd line
eff - Efficiency (%)
98
10000
91
1000
88
85
1st line
2nd line
100
2nd line
eff - Efficiency (%)
10
0.1
VOUT = 1.2 V, L = 0.56 µH
82
100
79
76
82
73
10
80
0
1
2
3
4
5
6
7
8
9 10 11 12
IOUT - Output Current (A)
Fig. 12 - SiC437 Efficiency vs. Output Current
(VIN = 5 V, fsw = 500 kHz, Full Load)
S20-0679-Rev. D, 27-Aug-2020
70
0.01
10
0.1
1
IOUT - Output Current (A)
Fig. 15 - SiC437 Efficiency vs. Output Current
(VIN = 5 V, fsw = 500 kHz, Light Load)
Document Number: 75921
9
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 7, CIN = 10 μF x 6, unless otherwise noted)
Axis Title
Axis Title
100
100
10000
VOUT = 5 V, L = 0.82 µH
98
97
VOUT = 5 V, L = 0.82 µH
1000
92
VOUT = 3.3 V, L = 0.56 µH
90
88
VOUT = 1.2 V, L = 0.36 µH
86
100
84
91
1000
88
85
VOUT = 3.3 V, L = 0.56 µH
82
79
100
VOUT = 1.2 V, L = 0.36 µH
76
82
73
10
80
0
1
2
3
4
5
6
7
8
10
70
0.01
9 10 11 12
IOUT - Output Current (A)
0.1
1
IOUT - Output Current (A)
Fig. 19 - SiC437 Efficiency vs. Output Current
(VIN = 12 V, fsw = 1 MHz, Light Load)
Fig. 16 - SIC437 Efficiency vs. Output Current
(VIN = 12 V, fsw = 1 MHz, Full Load)
Axis Title
Axis Title
100
100
10000
10000
92
98
84
76
1000
1st line
2nd line
92
90
88
VOUT = 1.2 V, L = 0.56 µH
86
100
2nd line
eff - Efficiency (%)
VOUT = 5 V, L = 1.5 µH
94
VOUT = 5 V, L = 1.5 µH
68
1000
60
1st line
2nd line
96
2nd line
eff - Efficiency (%)
1st line
2nd line
94
2nd line
eff - Efficiency (%)
94
1st line
2nd line
2nd line
eff - Efficiency (%)
96
10000
52
44
36
100
28
84
20
82
12
80
10
0
1
2
3
4
5
6
7
8
4
0.001
9 10 11 12
IOUT - Output Current (A)
VOUT = 1.2 V, L = 0.56 µH
10
0.01
0.1
1
IOUT - Output Current (A)
Fig. 17 - SiC437 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, FCCM, Full Load)
Fig. 20 - SiC437 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, FCCM, Light Load)
Axis Title
Axis Title
10000
100
100
VOUT = 5 V, L = 2.2 µH
96
95
10000
VOUT = 5 V, L = 2.2 µH
80
VOUT = 1.2 V, L = 0.56 µH
75
100
88
84
1000
VOUT = 3.3 V, L = 1.5 µH
1st line
2nd line
1000
85
1st line
2nd line
2nd line
eff - Efficiency (%)
VOUT = 3.3 V, L = 1.5 µH
2nd line
eff - Efficiency (%)
92
90
80
76
100
72
70
68
65
VOUT = 1.2 V, L = 0.56 µH
64
10
60
0
1
2
3
4
5
6
7
8
9 10 11 12
IOUT - Output Current (A)
Fig. 18 - SiC437 Efficiency vs. Output Current
(VIN = 24 V, fsw = 500 kHz, Full Load)
S20-0679-Rev. D, 27-Aug-2020
60
0.01
10
0.1
1
IOUT - Output Current (A)
Fig. 21 - SiC437 Efficiency vs. Output Current
(VIN = 24 V, fsw = 500 kHz, Light Load)
Document Number: 75921
10
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 7, CIN = 10 μF x 6, unless otherwise noted)
Axis Title
Axis Title
100
10000
VOUT = 5 V, L = 2.2 µH
98
97
96
VOUT = 5 V, L = 2.2 µH
1000
90
VOUT = 1.2 V, L = 0.82 µH
88
100
86
91
1000
VOUT = 3 .3V, L = 2.2 µH
88
1st line
2nd line
VOUT = 3.3 V, L = 2.2 µH
92
2nd line
eff - Efficiency (%)
94
94
1st line
2nd line
2nd line
eff - Efficiency (%)
10000
100
85
82
79
VOUT = 1.2 V, L = 0.82 µH
100
76
84
73
82
70
0.01
10
80
0
1
2
3
4
5
6
7
8
1
IOUT - Output Current (A)
IOUT - Output Current (A)
Fig. 25 - SiC438 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, Light Load)
Fig. 22 - SiC438 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, Full Load)
Axis Title
Axis Title
100
100
10000
VOUT = 5 V, L = 2.2 µH
98
10
0.1
10000
95
90
96
VOUT = 5 V, L = 2.2 µH
90
VOUT = 1.2 V, L = 0.82 µH
88
100
86
80
VOUT = 3.3 V, L = 2.2 µH
1000
75
1st line
2nd line
1000
VOUT = 3.3 V, L = 2.2 µH
92
2nd line
eff - Efficiency (%)
94
1st line
2nd line
2nd line
eff - Efficiency (%)
85
70
65
60
VOUT = 1.2 V, L = 0.82 µH
100
55
84
50
82
45
10
80
0
1
2
3
4
5
6
7
40
0.01
8
1
IOUT - Output Current (A)
IOUT - Output Current (A)
Fig. 23 - SiC438 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, Ultrasonic Mode, Full Load)
Fig. 26 - SiC438 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, Ultrasonic Mode, Light Load)
Axis Title
Axis Title
100
10000
97
96
94
94
1st line
2nd line
1000
92
VOUT = 1.2 V, L = 0.82 µH
90
88
100
86
84
2nd line
eff - Efficiency (%)
98
10000
91
1000
88
85
1st line
2nd line
100
2nd line
eff - Efficiency (%)
10
0.1
VOUT = 1.2 V, L = 0.82 µH
82
100
79
76
82
73
10
80
0
1
2
3
4
5
6
7
8
IOUT - Output Current (A)
Fig. 24 - SiC438 Efficiency vs. Output Current
(VIN = 5 V, fsw = 500 kHz, Full Load)
S20-0679-Rev. D, 27-Aug-2020
70
0.01
10
0.1
1
IOUT - Output Current (A)
Fig. 27 - SiC438 Efficiency vs. Output Current
(VIN = 5 V, fsw = 500 kHz, Light Load)
Document Number: 75921
11
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 7, CIN = 10 μF x 6, unless otherwise noted)
Axis Title
Axis Title
100
10000
100
94
1000
85
1st line
2nd line
88
VOUT= 1.2 V, L = 0.47 µH
82
100
79
91
88
85
82
76
73
73
10
0
1
2
3
4
5
6
7
100
79
76
70
1000
VOUT = 3.3 V, L = 1 µH
VOUT = 1.2 V, L = 0.47 µH
10
70
0.01
8
IOUT - Output Current (A)
0.1
1
IOUT - Output Current (A)
Fig. 31 - SiC438 Efficiency vs. Output Current
(VIN = 12 V, fsw = 1 MHz, Light Load)
Fig. 28 - SiC438 Efficiency vs. Output Current
(VIN = 12 V, fsw = 1 MHz, Full Load)
Axis Title
Axis Title
100
10000
100
10000
VOUT = 5 V, L = 2.2 µH
98
1st line
2nd line
VOUT = 3.3 V, L = 1 µH
91
2nd line
eff - Efficiency (%)
94
2nd line
eff - Efficiency (%)
10000
97
97
VOUT = 5 V, L = 2.2 µH
88
96
90
88
VOUT = 1.2 V, L = 0.82 µH
100
86
64
1000
VOUT = 3.3 V, L = 2.2 µH
1st line
2nd line
92
2nd line
eff - Efficiency (%)
1000
VOUT = 3.3 V, L = 2.2 µH
1st line
2nd line
2nd line
eff - Efficiency (%)
76
94
52
40
100
28
84
16
82
4
0.001
10
80
0
1
2
3
4
5
6
7
8
10
0.01
0.1
1
IOUT - Output Current (A)
IOUT - Output Current (A)
Fig. 29 - SiC438 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, FCCM, Full Load)
Fig. 32 - SiC438 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, FCCM, Light Load)
Axis Title
Axis Title
10000
100
100
VOUT = 5 V, L = 3.3 µH
95
VOUT = 1.2 V, L = 0.82 µH
96
10000
VOUT = 5 V, L = 2.2 µH
92
80
VOUT = 1.2 V, L = 1 µH
75
100
88
84
1000
1st line
2nd line
1000
2nd line
eff - Efficiency (%)
VOUT = 3.3 V, L = 2.2 µH
85
1st line
2nd line
2nd line
eff - Efficiency (%)
90
VOUT = 3.3 V, L = 2.2 µH
80
76
100
72
70
68
65
VOUT = 1.2 V, L = 0.82 µH
64
10
60
0
1
2
3
4
5
6
7
8
IOUT - Output Current (A)
Fig. 30 - SiC438 Efficiency vs. Output Current
(VIN = 24 V, fsw = 500 kHz, Full Load)
S20-0679-Rev. D, 27-Aug-2020
60
0.01
10
0.1
1
IOUT - Output Current (A)
Fig. 33 - SiC438 Efficiency vs. Output Current
(VIN = 24 V, fsw = 500 kHz, Light Load)
Document Number: 75921
12
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
2.00
1.2
1.75
1.1
EN Logic Threshold, VEN (V)
Normalized On-State Resistance, RDS(on)
ELECTRICAL CHARACTERISTICS
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 7, CIN = 10 μF x 6, unless otherwise noted)
1.50
1.25
1.00
0.75
0.50
0.25
1.0
0.9
VIH_EN
0.8
0.7
0.6
VIL_EN
0.5
0.00
-60 -40 -20
0
20
40
60
80
0.4
100 120 140
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (°C)
Temperature (°C)
Fig. 37 - EN Logic Threshold vs. Junction Temperature
608
100
606
90
604
80
Input Current, I VIN (uA)
Voltage Reference, VFB (mv)
Fig. 34 - On-Resistance vs. Junction Temperature
602
600
598
596
70
60
50
40
30
594
20
592
-60 -40 -20
0
3
20 40 60 80 100 120 140
Temperature (°C)
9
12
15
18
21
24
27
30
33
Input Voltage (V)
Fig. 38 - Input Current vs. Input Voltage
Fig. 35 - Voltage reference vs. Junction Temperature
1.4
100
VEN = 5 V
1.3
90
1.2
80
Input Current, IVIN (μA)
EN Current, IEN (μA)
6
1.1
1.0
0.9
0.8
70
60
50
40
0.7
30
0.6
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (°C)
Fig. 36 - EN Current vs. Junction Temperature
S20-0679-Rev. D, 27-Aug-2020
20
-60 -40 -20
0
20 40 60 80
Temperature (°C)
100 120 140
Fig. 39 - Input Current vs. Junction Temperature
Document Number: 75921
13
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 7, CIN = 10 μF x 6, unless otherwise noted)
3.0
1.00
0.75
2.5
2.3
Load Regulation (%)
Shutdown Current, IVIN_SHDN (uA)
2.8
2.0
1.8
1.5
1.3
1.0
0.8
0.50
0.25
0.00
-0.25
-0.50
0.5
-0.75
0.3
0.0
0
3
6
9
12
15
18
21
24
27
-1.00
0.0 2.5
30
5
Input Voltage (V)
Fig. 42 - Load Regulation vs. Output Current
1.2
1.00
1.1
0.75
0.9
0.50
0.8
0.25
Line Regulation (%)
Shutdown Current, IVIN_SHDN (μA)
Fig. 40 - Shutdown Current vs. Input Voltage
0.6
0.5
0.3
7.5 10 12.5 15 17.5 20 22.5 25
Output Current (A)
0.00
-0.25
-0.50
-0.75
0.2
-1.00
0.0
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
Fig. 41 - Shutdown Current vs. Junction Temperature
S20-0679-Rev. D, 27-Aug-2020
3
6
9
12
15
18
21
24
27
30
33
Input Voltage (V)
Fig. 43 - Line Regulation vs. Input Voltage
Document Number: 75921
14
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 7, CIN = 10 μF x 6, unless otherwise noted)
Vin, 5V/div
VDD, 5V/div
Vin, 5V/div
VDD, 5V/div
Vo, 500mV/div
VPgood, 5V/div
Vo, 500mV/div
VPgood, 5V/div
Fig. 44 - Startup with VIN, t = 5 ms/div
Fig. 47 - Shut down with VIN, t = 20 ms/div
VEN, 5V/div
VEN, 5V/div
VDD, 5V/div
VDD, 5V/div
Vo, 500mV/div
VPgood, 5V/div
Vo, 500mV/div
VPgood, 5V/div
Fig. 45 - Startup with EN, t = 1 ms/div
Vo, 50mV/div
Fig. 48 - Shut down with EN, t = 100 ms/div
Vo, 50mV/div
Io, 10A/div
Io, 10A/div
SW, 10V/div
Fig. 46 - Load Step, 6 A to 12 A, 1 A/μs, t = 10 μs/div
S20-0679-Rev. D, 27-Aug-2020
SW, 10V/div
Fig. 49 - Load Release, 12 A to 6 A, 1 A/μs, t = 10 μs/div
Document Number: 75921
15
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 7, CIN = 10 μF x 6, unless otherwise noted)
Vo, 50mV/div
Vo, 50mV/div
Io, 5A/div
Io, 5A/div
SW, 10V/div
Fig. 50 - Load Step, 0.1 A to 6 A, 1 A/μs, t = 10 μs/div
Skip Mode Enabled
Vo, 50mV/div
SW, 10V/div
Fig. 53 - Load Release, 6 A to 0.1 A, 1 A/μs, t = 20 μs/div
Skip Mode Enabled
Vo, 50mV/div
Io, 5A/div
Io, 5A/div
SW, 10V/div
Fig. 51 - Load Step, 0.1 A to 6 A, 1 A/μs, t = 10 μs/div
Forced Continuous Conduction Mode
SW, 10V/div
Fig. 54 - Load Release, 6 A to 0.1 A, 1 A/μs, t = 10 μs/div
Forced Continuous Conduction Mode
Vo, 20mV/div
Vo, 20mV/div
Vsw, 10V/div
Vsw, 10V/div
Fig. 52 - Output Ripple, 0.1 A, t = 20 μs/divSkip Mode Enabled
S20-0679-Rev. D, 27-Aug-2020
Fig. 55 - Output Ripple, 6 A, t = 1 μs/div
Forced Continuous Conduction Mode
Document Number: 75921
16
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 7, CIN = 10 μF x 6, unless otherwise noted)
Vo, 500mV/div
Vo, 20mV/div
Vsw, 10V/div
Vsw, 10V/div
Fig. 56 - Output Ripple, 0.1 A, t = 2 μs/div
Forced Continuous Conduction Mode
Fig. 58 - Output Undervoltage Protection Behavior, t = 50 μs/div
VPgood, 5V/div
Vo, 500mV/div
Iinductor, 10A/div
Vsw, 10V/div
Fig. 57 - Overcurrent Protection Behavior, t = 10 μs/div
S20-0679-Rev. D, 27-Aug-2020
Document Number: 75921
17
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
EXAMPLE SCHEMATIC
EN
RBOOT
2.2 Ω
PGOOD
CBOOT
0.1 μF
RPGOOD
BOOT
PHASE
EN
VIN 1
PGOOD
10 kΩ
MODE2
VIN-PAD
VIN = 4.5 V to 28 V
RMODE2
499 kΩ
VIN 2
CIN_D
100 nF
VDD
VIN 3
RMODE1
100 kΩ
MODE1
AGND-PAD
SiC437
PGND-PAD
AGND
PGND 1
R_FB_L
PGND 2
VFB
PGND
VOUT
SW 5
SW 4
SW 3
SW 2
SW 1
VDRV
GL 2
10 kΩ
GL 1
CIN
22 μF
x2
CVDD
1 μF
R_FB_H
45 kΩ
LO
CVDRV
4.7 μF
1.5 μH
3 mΩ
* * Analog ground (AGND), and power ground (PGND) are tied internally
AGND
VOUT = 3.3 V at 12 A
COUT_D
47 μF
COUT_C
47 μF
COUT_B
47 μF
COUT_A
47 μF
PGND
Fig. 59 - SiC437 configured for 4.5 V to 28 V Input, 3.3 V Output at 12 A,
500 kHz Operating Frequency, Continuous Mode enabled,
all Ceramic Output Capacitance Design
S20-0679-Rev. D, 27-Aug-2020
Document Number: 75921
18
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
EXTERNAL COMPONENT SELECTION FOR THE SiC43X
This section explains external component selection for
the SiC43x family of regulators. Component reference
designators in any equation refer to the schematic shown in
Fig. 59.
See PowerCAD online design center to simplify external
component calculations.
Output Voltage Adjustment
If a different output voltage is needed, simply change the
value of VOUT and solve for R_FB_H based on the following
formula:
R _FB_L V OUT - V FB
R _FB_H = ----------------------------------------------------V FB
Capacitor Selection
For instance, the design goal for output voltage ripple is 3 %
(45 mV for VOUT = 1.5 V) with ripple current of 4.43 A. The
maximum ESR value allowed is shown by the following
equation.
The output capacitors are chosen based upon required ESR
and capacitance. The maximum ESR requirement is
controlled by the output ripple requirement and the DC
tolerance. The output voltage has a DC value that is equal to
the valley of the output ripple plus 1/2 of the peak-to-peak
ripple. A change in the output ripple voltage will lead to a
change in DC voltage at the output.
V RIPPLE
45 mV
ESR MAX. = --------------------- = ----------------I RIPPLE
4.43 A
Where VFB is 0.6 V for the SiC43X. R_FB_L should be a
maximum of 10 k to prevent VOUT from drifting at no load.
ESR MAX. = 10.2 m
Inductor Selection
In order to determine the inductance, the ripple current must
first be defined. Low inductor values allow for the use of
smaller package sizes but create higher ripple current which
can reduce efficiency. Higher inductor values will reduce the
ripple current and, for a given DC resistance, are more
efficient. However, larger inductance translates directly into
larger packages and higher cost. Cost, size, output ripple,
and efficiency are all used in the selection process.
The ripple current will also set the boundary for power save
operation. The SiC431 will typically enter power save mode
when the load current decreases to 1/2 of the ripple current.
For example, if ripple current is 4 A, power save operation
will be active for loads less than 2 A. If ripple current is set
at 40 % of maximum load current, power save will typically
start at a load which is 20 % of maximum current.
The inductor value is typically selected to provide ripple
current of 25 % to 50 % of the maximum load current. This
provides an optimal trade-off between cost, efficiency, and
transient performance. During the on-time, voltage across
the inductor is (VIN - VOUT). The equation for determining
inductance is shown below.
V IN - V OUT x D
L O = -----------------------------------------------------K x I OUT_MAX. x f SW
where, K is the maximum percentage of ripple current, D is
the duty cycle, IOUT_MAX. is the maximum load current and
fSW is the switching frequency.
The output capacitance is usually chosen to meet transient
requirements. A worst-case load release (from maximum
load to no load) at the moment of peak inductor current,
determines the required capacitance. If the load release is
instantaneous (maximum load to no load in less than 1 μs)
the output capacitor must absorb all the inductor’s stored
energy. The output capacitor can be calculated according to
the following equation.
2
C OUT_MIN.
L O I OUT + 0.5 x I RIPPLE
MAX.
= -----------------------------------------------------------------------------2
2
V PK - V OUT
Where IOUT is the output current, IRIPPLE_MAX. is the
maximum ripple current, VPK is the peak VOUT during load
release, VOUT is the output voltage.
The duration of the load release is determined by VOUT and
the inductor. During load release, the voltage across the
inductor is approximately -VOUT, causing a down-slope or
falling di/dt in the inductor. If the di/dt of the load is not
much larger than di/dt of the inductor, then the inductor
current will tend to track the falling load current. This will
reduce the excess inductive energy that must be absorbed
by the output capacitor; therefore a smaller capacitance can
be used.
Under this circumstance, the following equation can be
used to calculate the needed capacitance for a given rate of
load release (diLOAD/dt).
2
C OUT
L x I PK
dT
--------------------- - I PK x I RELEASE x ------------------di LOAD
V OUT
= ---------------------------------------------------------------------------------------------------2 V PK - V OUT
1
I PK = I RELEASE + --- x I RIPPLE
MAX.
2
S20-0679-Rev. D, 27-Aug-2020
Document Number: 75921
19
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
Where IPK is the peak inductor current, IRIPPLE_MAX. is the
maximum peak to peak inductor current, IRELEASE is the
maximum load release current, VPK is the peak VOUT during
load release, dILOAD /dt is the rate of load release.
If the load step does not meet the requirement, increasing
the crossover frequency can help by adding feed forward
capacitor (CFF) in parallel to the upper feedback resistor to
generate another zero and pole. Placing the geometrical
mean of this pole and zero around the crossover frequency
will result in faster transient response. fZ and fP are the
generated zero and pole, see equations below.
1
-------------------------------------------fZ =
2 x R FB1 x C FF
Input Capacitance
In order to determine the minimum capacitance the input
voltage ripple needs to be specified; VCINPKPK 500 mV is a
suitable starting point. This magnitude is determined by the
final application specification. The input current needs to be
determined for the lowest operating input voltage,
I CIN RMS =
IO x
2
V OUT
2
1
D x 1 – D + ------ ------------------------------------- 1 – D D
L ƒ sw I OUT
12
The minimum input capacitance can then be found,
1
f P = ----------------------------------------------------------------------2 x R FB1 // R FB2 x C FF
D x 1 - D
C IN_min. = I OUT x ----------------------------------------V CINPKPK x f sw
Where RFB1 is the upper feedback resistor, RFB2 is the lower
feedback resistor CFF is the feed forward capacitor, fZ is the
zero from feed forward capacitor, fP is the pole frequency
generated from the feed forward capacitor.
A calculator is available to assist user to obtain the value of
the feed forward capacitance value.
If high ESR capacitors are used, it is good practice to also
add low ESR ceramic capacitance. A 4.7 μF ceramic input
capacitance is a suitable starting point.
Care must be taken to account for voltage derating of the
capacitance when choosing an all ceramic input
capacitance.
From the calculator, obtain the crossover frequency (fC). Use
the equation below for the calculation of the feed forward
capacitance value.
fC = fZ x fP
1
C FF = ----------------------------------------------------------------------------------------------------2 x f C x R FB1 x R FB1 // R FB2
As the internal RC compensation of the SiC431 works with
a wide range of output LC filters, the SiC431 offers stable
operation for a wide range of output capacitance, making
the product versatile and usable in a wide range of
applications.
S20-0679-Rev. D, 27-Aug-2020
Document Number: 75921
20
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
PCB LAYOUT RECOMMENDATIONS
Step 1: VIN/GND Planes and Decoupling
Step 3: VDD/VDRV Input Filter
VIN plane
AGND
CVDD
PGND
PGND plane
CVDRV
SW
1. Layout VIN and PGND planes as shown above
2. Ceramic capacitors should be placed between VIN and
PGND, and very close to the device for best decoupling
effect
3. Various ceramic capacitor values and package sizes
should be used to cover entire decoupling spectrum e.g.
1210 and 0603
4. Smaller capacitance values, closer to VIN pin(s), provide
better high frequency response
1. CVDD cap should be placed between VDD and AGND to
achieve best noise filtering
2. CVDRV cap should be placed close to VDRV and PGND pins
to reduce effects of trace impedance and provide
maximum instantaneous driver current for low side
MOSFET during switching cycle
Step 4: BOOT Resistor and Capacitor Placement
Step 2: SW Plane
PGND plane
Cboot
Snubber
Rboot
SW
1. Connect output inductor to device with large plane to
lower resistance
2. If a snubber network is required, place the components
on the bottom layer as shown above
S20-0679-Rev. D, 27-Aug-2020
1. CBOOT and RBOOT need to be placed very close to the
device, between PHASE and BOOT pins
2. In order to reduce parasitic inductance, it is
recommended to use 0402 chip size for the resistor and
the capacitor
Document Number: 75921
21
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
3. SW pad is a noise source and it is not recommended to
place vias on this pad
Step 5: Signal Routing
4. 8 mil vias on pads and 10 mil vias on planes are ideal via
sizes. The vias on pad may drain solder during assembly
and cause assembly issues. Please consult with the
assembly house for guideline
Step 7: Ground Connection
AGND
plane
PGND
V
o
u
t
s
i
g
n
a
l
1. Separate the small analog signal from high current path.
As shown above, the high paths with high dv/dt, di/dt are
placed on the left side of the IC, while the small control
signals are placed on the right side of the IC. All the
components for small analog signal should be placed
closer to IC with minimum trace length
2. IC analog ground (AGND), pin 16, should have a single
connection to PGND. The AGND ground plane connected
to pin16 helps to keep AGND quiet and improves noise
immunity
Vias
Vias
1. In order to minimize the ground voltage drop due to high
current, it is recommended to place vias on the PGND
planes. Make use of the inner ground layers to lower the
impedance
Step 7: Ground Layer
3. The output signal can be routed through inner layers.
Make sure this signal is far away from SW node and
shielded by an inner ground layer
AGND plane
Step 6: Thermal Management
VIN plane
PGND plane
1. It is recommended to make the whole inner 1 layer (next
to top layer) ground plane
PGND plane
SW
1. Thermal relief vias can be added to the VIN and PGND
pads to utilize inner layers for high current and thermal
dissipation
2. This ground plane provides shielding between noise
source on top layer and signal trace within inner layer
3. The ground plane can be broken into two section, PGND
and AGND
2. To achieve better thermal performance, additional vias
can be placed on VIN and PGND planes. It is also
necessary to duplicate the VIN and ground plane at
bottom layer to maximize the power dissipation
capability of the PCB
S20-0679-Rev. D, 27-Aug-2020
Document Number: 75921
22
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
PRODUCT SUMMARY
Part number
SiC437A
SiC437B
Description
12 A, 4.5 V to 28 V input,
300 kHz, 500 kHz,
750 kHz, 1 MHz,
synchronous buck
regulator with
ultrasonic mode and
internal 5 V bias
12 A, 4.5 V to 28 V input,
300 kHz, 500 kHz,
750 kHz, 1 MHz,
synchronous buck
regulator with
power save mode and
internal 5 V bias
SiC437C
SiC437D
Input voltage min. (V)
4.5
4.5
3
3
Input voltage max. (V)
28
28
28
28
12 A, 3 V to 28 V input,
12 A, 3 V to 28 V input,
300 kHz, 500 kHz,
300 kHz, 500 kHz,
750 kHz, 1 MHz,
750 kHz, 1 MHz,
synchronous buck
synchronous buck
regulator with
regulator with
power save mode,
ultrasonic mode,
requires external 5 V bias requires external 5 V bias
Output voltage min. (V)
0.6
0.6
0.6
0.6
Output voltage max. (V)
0.9 x VIN
0.9 x VIN
0.9 x VIN
0.9 x VIN
Continuous current (A)
12
12
12
12
Switch frequency min. (kHz)
300
300
300
300
Switch frequency max. (kHz)
1000
1000
1000
1000
Pre-bias operation (yes / no)
Yes
Yes
Yes
Yes
Internal bias reg. (yes / no)
Yes
Yes
No
No
Internal
Internal
Internal
Internal
Enable (yes / no)
Yes
Yes
Yes
Yes
PGOOD (yes / no)
Yes
Yes
Yes
Yes
Over current protection
Yes
Yes
Yes
Yes
Protection
OVP, OCP, UVP/SCP,
OTP, UVLO
OVP, OCP, UVP/SCP,
OTP, UVLO
OVP, OCP, UVP/SCP,
OTP, UVLO
OVP, OCP, UVP/SCP,
OTP, UVLO
Light load mode
Selectable ultrasonic
Selectable powersave
Selectable ultrasonic
Selectable powersave
97
97
97
97
PowerPAK MLP44-24L
PowerPAK MLP44-24L
PowerPAK MLP44-24L
PowerPAK MLP44-24L
4 x 4 x 0.75
Compensation
Peak efficiency (%)
Package type
Package size (W, L, H) (mm)
4 x 4 x 0.75
4 x 4 x 0.75
4 x 4 x 0.75
Status code
1
1
1
1
Product type
microBUCK (step down
regulator)
microBUCK (step down
regulator)
microBUCK (step down
regulator)
microBUCK (step down
regulator)
Applications
Computing, consumer,
industrial, healthcare,
networking
Computing, consumer,
industrial, healthcare,
networking
Computing, consumer,
industrial, healthcare,
networking
Computing, consumer,
industrial, healthcare,
networking
S20-0679-Rev. D, 27-Aug-2020
Document Number: 75921
23
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
PRODUCT SUMMARY
Part number
SiC438A
SiC438B
Description
8 A, 4.5 V to 28 V input,
300 kHz, 500 kHz,
750 kHz, 1 MHz,
synchronous buck
regulator with
ultrasonic mode and
internal 5 V bias
8 A, 4.5 V to 28 V input,
300 kHz, 500 kHz,
750 kHz, 1 MHz,
synchronous buck
regulator with
power save mode and
internal 5 V bias
SiC438C
SiC438D
Input voltage min. (V)
4.5
4.5
3
3
Input voltage max. (V)
28
28
28
28
8 A, 3 V to 28 V input,
8 A, 3 V to 28 V input,
300 kHz, 500 kHz,
300 kHz, 500 kHz,
750 kHz, 1 MHz,
750 kHz, 1 MHz,
synchronous buck
synchronous buck
regulator with
regulator with
power save mode,
ultrasonic mode,
requires external 5 V bias requires external 5 V bias
Output voltage min. (V)
0.6
0.6
0.6
0.6
Output voltage max. (V)
0.9 x VIN
0.9 x VIN
0.9 x VIN
0.9 x VIN
Continuous current (A)
8
8
8
8
Switch frequency min. (kHz)
300
300
300
300
Switch frequency max. (kHz)
1000
1000
1000
1000
Pre-bias operation (yes / no)
Yes
Yes
Yes
Yes
Internal bias reg. (yes / no)
Yes
Yes
No
No
Internal
Internal
Internal
Internal
Enable (yes / no)
Yes
Yes
Yes
Yes
PGOOD (yes / no)
Yes
Yes
Yes
Yes
Overcurrent protection
Yes
Yes
Yes
Yes
Protection
OVP, OCP, UVP/SCP,
OTP, UVLO
OVP, OCP, UVP/SCP,
OTP, UVLO
OVP, OCP, UVP/SCP,
OTP, UVLO
OVP, OCP, UVP/SCP,
OTP, UVLO
Light load mode
Selectable ultrasonic
Selectable powersave
Selectable ultrasonic
Selectable powersave
97
97
97
97
PowerPAK MLP44-24L
PowerPAK MLP44-24L
PowerPAK MLP44-24L
PowerPAK MLP44-24L
4 x 4 x 0.75
Compensation
Peak efficiency (%)
Package type
Package size (W, L, H) (mm)
4 x 4 x 0.75
4 x 4 x 0.75
4 x 4 x 0.75
Status code
2
2
2
2
Product type
microBUCK (step down
regulator)
microBUCK (step down
regulator)
microBUCK (step down
regulator)
microBUCK (step down
regulator)
Applications
Computing, consumer,
industrial, healthcare,
networking
Computing, consumer,
industrial, healthcare,
networking
Computing, consumer,
industrial, healthcare,
networking
Computing, consumer,
industrial, healthcare,
networking
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?75921.
S20-0679-Rev. D, 27-Aug-2020
Document Number: 75921
24
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
PowerPAK® MLP44-24L Case Outline
0.08 C
A1
A2
K5
b
MILLIMETERS
NOM.
0.75
0.20 ref.
0.25
0.20
4.00
0.45 BSC
0.70 BSC
0.90 BSC
4.00
0.40
24
1.05
1.50
2.73
2.07
0.52
1.00
1.15
0.38
1.00
0.32
0.40 ref.
0.57 ref.
0.35 ref.
0.35 ref.
0.35 ref.
0.525 ref.
0.725 ref.
0.575 ref.
0.975 ref.
Side view
MAX.
0.80
0.05
D2-2
K
D2-1 L1
1
15
14
13
D2-3
K1
K3
12
11
K7
0.10 C A
K4
22 23 24
L1
2
3
D2-4
D2-5
4
10 9 8
6 5
e e e1 7
K5
e x 2 = 0.9
Bottom view
MIN.
0.027
0.000
INCHES
NOM.
0.029
0.008 ref.
0.010
0.008
0.157
0.018 BSC
0.028 BSC
0.035 BSC
0.157
0.016
24
0.041
0.059
0.108
0.081
0.020
0.039
0.045
0.015
0.039
0.013
0.016 ref.
0.022 ref.
0.014 ref.
0.014 ref.
0.014 ref.
0.021 ref.
0.029 ref.
0.023 ref.
0.038 ref.
MAX.
0.031
A (8)
A1
0.002
A2
b (4)
0.20
0.30
0.008
0.012
b1
0.15
0.25
0.006
0.010
D
3.90
4.10
0.155
0.159
e
e1
e2
E
3.90
4.10
0.154
0.161
L
0.35
0.45
0.014
0.018
N (3)
D2-1
1.00
1.10
0.039
0.043
D2-2
1.45
1.55
0.057
0.061
D2-3
2.68
2.78
0.106
0.110
D2-4
2.02
2.12
0.079
0.083
D2-5
0.47
0.57
0.018
0.022
E2-1
0.95
1.05
0.037
0.041
E2-2
1.10
1.20
0.043
0.047
E2-3
0.33
0.43
0.013
0.017
E2-4
0.95
1.05
0.037
0.041
E2-5
0.27
0.37
0.011
0.015
K
K1
K2
K3
K4
K5
K6
K7
K8
ECN: T17-0551-Rev. B, 16-Oct-17
DWG: 6055
Notes
(1) Use millimeters as the primary measurement
(2) Dimensioning and tolerances conform to ASME Y14.5M. - 1994
(3) N is the number of terminals
(4) Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip
(5) The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
(6) Exact shape and size of this feature is optional
(7) Package warpage max. 0.08 mm
(8) Applied only for terminals
Revision: 16-Oct-17
MIN.
0.70
0.00
e x 2 = 0.9
K5
16
K8
2x
DIM.
17
K2
(4)
Top view
e1
e
e
e2
E2-2 K4 E2-1 K4 L
18 19 20 21
MLP44-24L
(4 mm x 4 mm)
B
e x 3 = 1.35
b1
E2-5
0.10 C A
0.10 M C A B
D
K6
e x 6 = 2.7
K4 E2-4 K4
E2-3
E
A
L K4
A
2x
(5) (6)
Pin 1 dot
by marking
Document Number: 74345
1
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PAD Pattern
www.vishay.com
Vishay Siliconix
Recommended Land Pattern PowerPAK® MLP44-24L
24
18
17
1
4
11
5
10
4
0.525
0.45 x 2 = 0.9
0.7
0.45 x 3 = 1.35
0.45
0.525
0.3
18
0.45 x 6 = 2.7
0.3
0.455
0.65
0.27 0.58
0.3
0.38
1.2
0.55
0.45
0.3
0.45
0.725
2.175
11
0.3
0.575
4
1.025
0.5
0.27
0.3
0.3
2.825
0.73 0.39
0.45
1
0.45
0.9
17
0.3
1.575
1.05
0.3
4
0.3
0.725
1.15
0.3
0.25
0.3
1.175
0.725
0.3
24
0.725
5
10
0.3
0.525
0.9
0.7
0.45
0.45
0.975
All dimensions are in millimeters
Revision: 15-Aug-17
Document Number: 78231
1
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Legal Disclaimer Notice
www.vishay.com
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay's knowledge of typical
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements
about the suitability of products for a particular application. It is the customer's responsibility to validate that a particular product
with the properties described in the product specification is suitable for use in a particular application. Parameters provided in
datasheets and / or specifications may vary in different applications and performance may vary over time. All operating
parameters, including typical parameters, must be validated for each customer application by the customer's technical experts.
Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited
to the warranty expressed therein.
Hyperlinks included in this datasheet may direct users to third-party websites. These links are provided as a convenience and
for informational purposes only. Inclusion of these hyperlinks does not constitute an endorsement or an approval by Vishay of
any of the products, services or opinions of the corporation, organization or individual associated with the third-party website.
Vishay disclaims any and all liability and bears no responsibility for the accuracy, legality or content of the third-party website
or for that of subsequent links.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please
contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
© 2022 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 01-Jan-2022
1
Document Number: 91000
工商网监
湘ICP备2023018690号
