SiC461, SiC462, SiC463, SiC464
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Vishay Siliconix
4.5 V to 60 V Input, 2 A, 4 A, 6 A, 10 A
microBUCK® DC/DC Converter
FEATURES
LINKS TO ADDITIONAL RESOURCES
Design Tool
Evaluation
Boards
Design Tools
DESCRIPTION
The SiC46x is a family of wide input voltage, high efficiency
synchronous buck regulators with integrated high side and
low side power MOSFETs. Its power stage is capable of
supplying high continuous current at up to 2 MHz switching
frequency. This regulator produces an adjustable output
voltage down to 0.8 V from 4.5 V to 60 V input rail to
accommodate a variety of applications, including
computing, consumer electronics, telecom, and industrial.
SiC46x’s architecture allows for ultrafast transient response
with minimum output capacitance and tight ripple regulation
at very light load. The device enables loop stability
regardless of the type of output capacitor used, including
low ESR ceramic capacitors. The device also incorporates a
power saving scheme that significantly increases light load
efficiency. The regulator integrates a full protection feature
set, including over current protection (OCP), output
overvoltage protection (OVP), short circuit protection (SCP),
output undervoltage protection (UVP) and over temperature
protection (OTP). It also has UVLO for input rail and a user
programmable soft start.
The SiC46x family is available in 2 A, 4 A, 6 A, 10 A pin
compatible 5 mm by 5 mm lead (Pb)-free power enhanced
MLP55-27L package.
• Versatile
- Single supply operation from 4.5 V to 60 V
input voltage
- Adjustable output voltage down to 0.8 V
- Scalable solution 2 A (SiC464), 4 A (SiC463),
6 A (SiC462), 10 A (SiC461)
- Output voltage tracking and sequencing with
pre-bias start up
- ± 1 % output voltage accuracy at -40 °C to +125 °C
• Highly efficient
- 98 % peak efficiency
- 4 μA supply current at shutdown
- 235 μA operating current, not switching
• Highly configurable
- Adjustable switching frequency from 100 kHz to 2 MHz
- Adjustable soft start and adjustable current limit
- 3 modes of operation, forced continuous conduction,
power save or ultrasonic
• Robust and reliable
- Output over voltage protection
- Output under voltage / short circuit protection with auto
retry
- Power good flag and over temperature protection
- Supported by Vishay PowerCAD online design
simulation
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
•
•
•
•
•
•
•
Industrial and automation
Home automation
Industrial and server computing
Networking, telecom, and base station power supplies
Unregulated wall transformer
Robotics
High end hobby electronics: remote control cars, planes,
and drones
• Battery management systems
• Power tools
• Vending, ATM, and slot machines
TYPICAL APPLICATION CIRCUIT
100
10000
VIN = 24 V, VOUT = 12 V
VIN = 48 V, VOUT = 12 V
98
V IN
CBOOT
PHASE
V OUT
SW
V DD
CIN
SiC46x
V DRV
ULTRASONIC
MODE
Cy
Cx
Rup
V FB
SS
ILIMIT
COMP
PGND
fSW
Rlimit
AGND
Css
Rx
V SNS
COUT
Rcomp
Rdown
Ccomp
Rfsw
94
1000
92
90
1st line
2nd line
BOOT
EN
VCIN
PGOOD
INPUT
4.5 VDC to 60 VDC
2nd line
eff - Efficiency (%)
96
VIN = 24 V, VOUT = 5 V
88
VIN = 48 V, VOUT = 5 V
86
100
84
82
10
80
0
1
2
3
4
5
6
IOUT - Output Current (A)
Fig. 1 - Typical Application Circuit for SiC46x
S21-1142-Rev. P, 29-Nov-2021
Fig. 2 - SiC462 Efficiency vs. Output Current
Document Number: 65124
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6
15 GL
GL 1 5
14 SW
SW 1 4
13 SW
SW 1 3
12 SW
SW 1 2
27 MODE
26 VDD
25 ILIM
24 fSW
22 VFB
23 AGND
3 EN
4 BOOT
30 PGND
29
VIN
5 PHASE
6
PGND 11
PGND 10
PGND 9
VIN 8
VIN 7
PHASE 6
VDRV 1 6
2 PGOOD
6 PHASE
VIN 7
29 PGND
16 VDRV
28 AGND
VIN 8
30
VIN
PGND 1 7
PGND 9
BOOT 4
ULTRASONIC 1 8
17 PGND
PGND 11
EN 3
PHASE 5
20 VSNS
18 ULTRASONIC
28 AGND
PGOOD 2
1 VCIN
SS 19
19 SS
PGND 10
1
VCIN 1
21 COMP
20 VSNS
22 VFB
21 COMP
23 AGND
24 fSW
26 VDD
25 ILIM
27 MODE
PIN CONFIGURATION
Fig. 3 - SiC46x Pin Configuration
PIN DESCRIPTION
PIN NUMBER
SYMBOL
DESCRIPTION
1
VCIN
Supply voltage for internal regulators VDD and VDRV. This pin should be tied to VIN, but can also be
connected to a lower supply voltage (> 5 V) to reduce losses in the internal linear regulators
2
PGOOD
3
EN
Open-drain power good indicator - high impedance indicates power is good. An external pull-up
resistor is required
Enable pin. Tie high/low to enable/disable the IC accordingly. This is a high voltage compatible pin,
can be tied to 60 V
4
BOOT
High side driver bootstrap voltage
5, 6
PHASE
Return path of high side gate driver
7, 8, 29
VIN
9, 10, 11, 17, 30
PGND
12, 13, 14
SW
Power stage switch node
15
GL
Low side MOSFET gate signal
16
VDRV
Supply voltage for internal gate driver. When using the internal LDO as a bias power supply, VDRV is
the LDO output. Connect a 4.7 μF decoupling capacitor to PGND
18
ULTRASONIC
Float to disable ultrasonic mode, connect to VDD to enable. Depending on the operation mode set by
the mode pin, power save mode or forced continuous mode will be enabled when the ultrasonic
mode is disabled
19
SS
Set the soft start ramp by connecting a capacitor to AGND. An internal current source will charge the
capacitor
20
VSNS
21
COMP
Output of the internal error amplifier. The feedback loop compensation network is connected from
this pin to the AGND pin
22
VFB
Feedback input for switching regulator used to program the output voltage - connect to an external
resistor divider from VOUT to AGND
23, 28
AGND
24
fSW
25
ILIMIT
26
VDD
27
MODE
S21-1142-Rev. P, 29-Nov-2021
Power stage input voltage. Drain of high side MOSFET
Power ground
Power inductor signal feedback pin for system stability compensation
Analog ground
Set the on-time by connecting a resistor to AGND
Set the current limit by connecting a resistor to AGND
Bias supply for the IC. VDD is an LDO output, connect a 1 μF decoupling capacitor to AGND
Set various operation modes by connecting a resistor to AGND. See specification table for details
Document Number: 65124
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ORDERING INFORMATION
PART NUMBER
PACKAGE
MARKING CODE
PowerPAK® MLP55-27L
SiC461ED-T1-GE3
SiC461EVB
SiC461
Reference board
PowerPAK® MLP55-27L
SiC462ED-T1-GE3
SiC462EVB
SiC462
Reference board
PowerPAK® MLP55-27L
SiC463ED-T1-GE3
SiC463EVB
SiC463
Reference board
PowerPAK® MLP55-27L
SiC464ED-T1-GE3
SiC464EVB
SiC464
Reference board
PART MARKING INFORMATION
=
pin 1 indicator
P/N
P/N =
=
Siliconix logo
LL
=
ESD symbol
assembly factory code
FYWW
part number code
F
=
Y
=
year code
WW
=
week code
LL
=
lot code
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
ELECTRICAL PARAMETER
CONDITIONS
LIMITS
VCIN, VIN
Reference to PGND
-0.3 to 66
EN
Reference to AGND
-0.3 to 60
SW / PHASE
Reference to PGND
-0.3 to 66
VDRV
Reference to PGND
-0.3 to 6
VDD
SW / PHASE (AC)
Reference to AGND
-0.3 to 6
Reference to PGND; 100 ns
-10 to 72
BOOT
V
-0.3 to VPHASE + VDRV
AGND to PGND
All other pins
UNIT
-0.3 to 0.3
Reference to AGND
-0.3 to VDD + 0.3
Junction temperature
TJ
-40 to +150
Storage temperature
TSTG
-65 to +150
Temperature
°C
Power Dissipation
Thermal resistance from junction-to-ambient
12
Thermal resistance from junction-to-case
2
°C/W
ESD Protection
Electrostatic discharge protection
Human body model, JESD22-A114
2000
Charged device model, JESD22-A101
500
V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating/conditions for extended periods may affect device reliability.
S21-1142-Rev. P, 29-Nov-2021
Document Number: 65124
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RECOMMENDED OPERATING CONDITIONS (all voltages referenced to GND = 0 V)
PARAMETER
MIN.
TYP.
MAX.
Input voltage (VIN)
4.5
-
60
Control input voltage (VCIN) (1)
4.5
-
60
Enable (EN)
0
-
60
Bias supply (VDD)
4.75
5
5.25
Drive supply voltage (VDRV)
4.75
5.3
5.55
Output voltage (VOUT)
0.8
-
0.92 x VIN
UNIT
V
Temperature
Recommended ambient temperature
-40 to +105
Operating junction temperature
-40 to +125
°C
Note
(1) For input voltages below 5 V, provide a separate supply to V
CIN of at least 5 V to prevent the internal VDD rail UVLO from triggering
ELECTRICAL SPECIFICATIONS (VIN = VCIN = 48 V, VEN = 5 V, TJ = -40 °C to +125 °C, unless otherwise stated)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
VIN = VCIN = 6 V to 60 V
VIN = VCIN = 5 V
4.75
5
5.25
4.7
5
-
UNIT
Power Supplies
VDD supply
VDD
VDD dropout
VDD_DROPOUT
-
70
-
VDD_UVLO
4
4.25
4.5
V
VDD UVLO hysteresis
VDD_UVLO_HYST
-
225
-
mV
Maximum VDD current
IDD
mA
VDD UVLO threshold, rising
VIN = VCIN = 5 V, IVDD = 1 mA
V
VIN = VCIN = 6 V to 60 V
3
-
-
VIN = VCIN = 6 V to 60 V
4.75
5.3
5.55
VIN = VCIN = 5 V
4.8
5
5.2
mV
VDRV supply
VDRV
VDRV dropout
VDRV_DROPOUT
VIN = VCIN = 5 V, IVDD = 10 mA
-
160
-
mV
VDRV
VIN = VCIN = 6 V to 60 V
30
-
-
mA
VDRV_UVLO
4
4.25
4.5
V
VDRV_UVLO_HYST
-
295
-
mV
Maximum VDRV current
VDRV UVLO threshold, rising
VDRV UVLO hysteresis
Input current
Shutdown current
V
IVCIN
Non-switching, VFB > 0.8 V
-
235
325
IVCIN_SHDN
VEN = 0 V
-
4
8
TJ = 25 °C
796
800
804
TJ = -40 °C to +125 °C (1)
792
800
808
-
2
-
nA
mS
μA
Controller and Timing
Feedback voltage
VFB
VFB input bias current
IFB
Transconductance
COMP source current
COMP sink current
Minimum on-time
tON accuracy
On-time range
m/V
gm
-
0.3
-
ICOMP_SOURCE
15
20
-
ICOMP_SINK
15
20
-
tON_MIN.
-
90
110
ns
tON_ACCURACY
-10
-
10
%
ns
tON_RANGE
Frequency range
fsw
110
-
8000
Ultrasonic mode enabled
20
-
2000
Ultrasonic mode disabled
0
-
2000
μA
kHz
Minimum off-time
tOFF_MIN.
190
250
310
ns
Soft start current
ISS
3
5
7
μA
Soft start voltage
VSS
-
1.5
-
V
S21-1142-Rev. P, 29-Nov-2021
When VOUT reaches regulation
Document Number: 65124
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ELECTRICAL SPECIFICATIONS (VIN = VCIN = 48 V, VEN = 5 V, TJ = -40 °C to +125 °C, unless otherwise stated)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
SiC461 (10 A),
RILIM = 60 kΩ, TJ = -10 °C to +125 °C
10.4
13
15.6
SiC462 (6 A),
RILIM = 60 kΩ, TJ = -10 °C to +125 °C
6.4
8
9.6
SiC463 (4 A),
RILIM = 40 kΩ, TJ = -10 °C to +125 °C (2)
4.8
6
7.2
SiC464 (2 A),
RILIM = 60 kΩ, TJ = -10 °C to +125 °C
3.2
4
4.8
-
20
-
-
-80
-
UNIT
Fault Protections
Valley current limit
IOCP
Output OVP threshold
VOVP
Output UVP threshold
VUVP
Over temperature protection
VFB with respect to 0.8 V reference
A
TOTP_RISING
Rising temperature
-
150
-
TOTP_HYST
Hysteresis
-
35
-
VFB_RISING_VTH_OV
VFB rising above 0.8 V reference
-
20
-
VFB_FALLING_VTH_UV
VFB falling below 0.8 V reference
-
-10
-
%
°C
Power Good
Power good output threshold
Power good hysteresis
%
VFB_HYST
-
50
-
Power good on resistance
RON_PGOOD
-
7.5
15
Ω
Power good delay time
tDLY_PGOOD
15
25
35
μs
EN logic high level
VEN_H
-
1.35
-
EN logic low level
VEN_L
-
1.2
-
EN hysteresis
VHYST
-
0.15
-
mV
EN / MODE / Ultrasonic Threshold
REN
-
5
-
Ultrasonic mode high Level
EN pull down resistance
VULTRASONIC_H
2
-
-
Ultrasonic mode low level
VULTRASONIC_L
-
-
0.8
Mode pull up current
IMODE
3.75
5
6.25
Mode 1
Power save mode enabled, VDD, VDRV
Pre-reg on
0
2
100
Mode 2
Power save mode disabled, VDD, VDRV
Pre-reg on
298
301
304
Mode 3
Power save mode disabled, VDRV Pre-reg
off, VDD Pre-reg on, provide external VDRV
494
499
504
Mode 4
Power save mode enabled, VDRV Pre-reg off,
VDD Pre-reg on, provide external VDRV
900
1000
1100
RMODE
V
MΩ
V
μA
kΩ
Notes
(1) Guaranteed by design
(2) Guaranteed by design for SiC463 OCP measurements
S21-1142-Rev. P, 29-Nov-2021
Document Number: 65124
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FUNCTIONAL BLOCK DIAGRAM
VCIN
BOOT
VDRV
VDRV
regulator
VDD
VDD
regulator
Sync
rectifier
VDD UVLO
HS UVLO
Enable
EN
fSW
ULTRASONIC
VIN
On time
generator
VDD
5 μA
tON
Min. tOFF
HS
driver
PHASE
MODE
MODE
VSNS
SW
Control
logic
Ramp
VDRV
PWM
COMP
COMP
VDD
0.8 V
5 μA
LS
driver
Reference
PHASE
Zero
crossing
GL
OTA
SS
PGOOD
VFB
Over voltage
under voltage
VFB
ILIMIT
PHASE
Over
current
Over
temperature
Power good
AGND
PGND
Fig. 4 - SiC46x Functional Block Diagram
OPERATIONAL DESCRIPTION
Device Overview
Power Stage
SiC46x is a high efficiency synchronous buck regulator
family capable of delivering up to 10 A continuous current.
The device has programmable switching frequency of
100 kHz to 2 MHz. The voltage mode, constant on time
control scheme delivers fast transient response, minimizes
the number of external components and enables loop
stability regardless of the type of output capacitor used,
including low ESR ceramic capacitors. The device also
incorporates a power saving feature that enables diode
emulation mode and frequency fold back as the load
decreases.
SiC46x integrates a high performance power stage with a
n-channel high side MOSFET and a n-channel low side
MOSFET optimized to achieve up to 98 % efficiency.
SiC46x has a full set of protection and monitoring features:
• Over current protection in pulse-by-pulse mode
• Output overvoltage protection
• Output undervoltage protection with auto retry
• Over temperature protection with hysteresis
• Dedicated enable pin for easy power sequencing
• Power good open drain output
• This device is available in MLP55-27L package to deliver
high power density and minimize PCB area
S21-1142-Rev. P, 29-Nov-2021
The power input voltage (VIN) can go up to 60 V and down
as low as 4.5 V for power conversion.
Control Scheme
SiC46x employs a voltage mode COT control mechanism in
conjunction with adaptive zero current detection which
allows for power saving in discontinuous conduction mode
(DCM). The switching frequency, fSW, is set by an external
resistor to AGND, Rfsw. The SiC46x operates between
100 kHz to 2 MHz depending on VIN and VOUT conditions.
V OUT
R fsw = --------------------------------------------12
f sw × 190 × 10
Note, as long as VIN and VCIN are connected together, fSW
has no dependency on VIN as the on time is adjusted as VIN
varies. During steady-state operation, feedback voltage
(VFB) is compared with internal reference (0.8 V typ.) and the
amplified error signal (VCOMP) is generated at the comp node
by the external compensation components, RCOMP and
CCOMP. An externally generated ramp signal and VCOMP feed
into a comparator. Once VRAMP crosses VCOMP, an on-time
Document Number: 65124
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pulse is generated for a fixed time. During the on-time pulse,
the high side MOSFET will be turned on. Once the on-time
pulse expires, the low side MOSFET will be turned on after
a dead time period. The low side MOSFET will stay on for a
minimum duration equal to the minimum off-time (tOFF_MIN.)
and remains on until VRAMP crosses VCOMP. The cycle is then
repeated.
Fig. 6 illustrates the basic block diagram for voltage mode,
constant on time architecture with external ripple injection,
VRAMP, while Fig. 5 illustrates the basic operational principle.
Vishay Siliconix
VIN
Q1
Q2
CIN
Ripple
based
controller
L
Rx
Cx
COUT
Cy
R_FB_H
EA
RCOMP
CCOMP
REF
Load
R_FB_L
VRAMP
Fig. 6 - SiC46x Control Block Diagram
Below is the equation for calculating the VRAMP amplitude.
VCOMP
( V IN – V OUT ) × V OUT
V RAMP = -----------------------------------------------------( V IN × f sw × C x × R x )
PWM
Fixed on-time
Fig. 5 - SiC46x Operational Principle
The need for ripple injection in this architecture is explained
below. First, let us understand the basic principles of this
control architecture:
• The reference of a basic voltage mode COT regulator
is replaced with a high gain error amplifier loop. The loop
ensures the DC component of the output voltage follows
the internal accurate reference voltage, providing
excellent regulation
• A second voltage feedback path via VSNS with a VRAMP
scheme ensures rapid correction of the transient
perturbation
• This establishes two voltage loops, one is the steady state
voltage feedback path (via the FB pin) and the other is the
feed forward path (via the VSNS pin). The scheme gives the
user the fast transient response of a COT regulator and
the stable, jitter free, line and load regulation performance
of a PWM controller
Choosing the Ripple Injection Component Values
For stability purposes the SiC46x requires adequate ripple
injection amplitude. Adequate ripple amplitude is required
for two main reasons:
1. To reduce jitter due to noise coupled into the system
2. To provide stable operation. Sub harmonic oscillation
can occur with constant on time ripple control if below
condition is not met
t ON
ESR × C OUT > --------2
Therefore, when the converter design uses an all ceramic
output capacitor or other low ESR output capacitors,
instability can occur. In order to avoid this, a VRAMP network
is used to increase the equivalent RESR in order to satisfy the
above condition. The VRAMP amplitude must be large
enough to avoid instability or noise sensitivity but not too
large that it degrades transient performance. To ensure
stable operation under CCM, DCM and ultrasonic mode,
minimum VRAMP amplitude of 100 mV is recommended for
the SiC46x family of regulators. A maximum VRAMP of
900 mV is recommended so as not to degrade transient
response.
S21-1142-Rev. P, 29-Nov-2021
VRAMP amplitude is a function of VIN, VOUT, and switching
frequency and should be adjusted whenever VIN, VOUT, or
switching frequency is changed.
For a given buck regulator design, VOUT and switching
frequency is typically fixed, while the converter may be
expected to work for a wide VIN range. The VRAMP amplitude
will increase as VIN is increased and increase the power
dissipated by Rx. A proper selection of RX, package size and
value, should take into account the maximum power
dissipation at the expected operating conditions.
In order to optimize the VRAMP amplitude over a desired VIN
range use the following procedure to calculate Rx, Cx, and
Cy.
1. The equation below calculates RX as a function of VIN,
VOUT, and maximum allowable power dissipated by RX.
V IN_MAX. × V OUT × ( 1 – D )
R x = -------------------------------------------------------------------P RX_MAX.
where PRX_MAX. is the maximum allowed power
dissipation in Rx. Note, the maximum power dissipation
of a 0603 sized resistor is typically 25 mW. Power
dissipation derating must be taken into account for high
ambient temperatures
2. The equation below calculates CX_MIN. as a function of
VIN and maximum allowed VRAMP amplitude.
P RX_MAX.
C X_MIN. = --------------------------------------------------------------------------V IN_MAX. × f sw × V RAMP_MAX.
where VRAMP_MAX. = 900 mV
3. Using VRAMP equation, calculate VRAMP_MIN. at minimum
VIN based on the Rx and the minimum Cx value
calculated above
4. If VRAMP_MIN. is > 200 mV, set Cx to CX_MIN., otherwise set
Cx to (Cx_MIN. x VRAMP_MIN./200 mV). If VRIPPLE_MIN. is
< 100 mV, increase PRX_MAX. and recalculate RX and CX
5. Cy should be large enough not to distort the VRAMP and
small enough not to load excessively the VRAMP network
(Rx and Cx). Please use the follow formula:
Cy = 1/(820 x fsw)
This procedure allows for a maximum range of operation.
Document Number: 65124
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Error Amplifier Compensation Value Selection (for reference only)
RCOMP and CCOMP in the Fig. 6 are the components used to compensate the control loop.
For optimal transient response, the crossover frequency should be:
• Set typically at 1/10th to 1/5th of the converter switching frequency (Vishay’s component calculator tool uses 1/10th the
converter switching frequency)
• Be above the LC filter resonance frequency which is 1/2 π LC
The procedure to select the RCOMP and CCOMP such that the above conditions are met is as follows:
1. Plot the magnitude and phase of the control to output transfer function using the equation below.
Control to output transfer function.
1 + sR C C o × ( 1 + sR x C x ) × ( 1 + sR y C y )
H(s) = A × -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------sL
2
L
2
1 + ------ + s LC o × ( 1 + sR x C x ) × ( 1 + sR y C y ) + AR y C y s × 1 + s × R x C x + ------- + s × ( R x R c C x C o + LC o )
Ro
R o
Where A = (2VIN x Rx x Cx x f)/VOUT, Rx, Cx, Cy are components for ripple injection as shown in Fig. 6 and Ry is the internal
impedance of the VSNS pin and is = 65 kΩ.
Co - output capacitance
Rc - output capacitor ESR
2. From the plot of the control to output transfer function, determine the gain and phase at the crossover frequency
3. Calculate the RCOMP using the equation
1
R COMP = -------------------------------------G H × gm × r FB
where GH is the gain of the transfer function at cross over frequency, “gm” is the transconductance of the error amplifier
(300 μS) and rFB is the ratio of the feedback divider, rFB = R_FB_L/(R_FB_L + R_FB_H)
4. Select CCOMP based on the placement of the zero such that phase margin is sufficient at the cross over frequency. A phase
margin of over 60° is sufficient for converter stability. A good starting point is to place the compensation zero at 1/5th of the
LC pole
5 LC
C COMP = ------------------R COMP
Once the component values are calculated, it is now possible to calculate the total loop gain. The total loop gain is the product
of the control to output transfer function and the error amplifier transfer function.
The transfer function of the error amplifier is given by the equation below.
( 1 + sR COMP C COMP ) × r FB
G ( s ) = gmR o × ----------------------------------------------------------------------------------------------------( 1 + s × ( R COMP C COMP + R o C COMP ) )
Where Ro = 40 MΩ is the output resistance of the transconductance amplifier.
Total loop transfer function = H(s)G(s)
S21-1142-Rev. P, 29-Nov-2021
Document Number: 65124
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Power-Save Mode, Mode Pin, and Ultrasonic Pin Operation
To improve efficiency at light-loads, SiC46x provides a set
of innovative implementations to reduce low side
re-circulating current and switching losses. The internal zero
crossing detector monitors SW node voltage to determine
when inductor current starts to flow negatively. In power
saving mode, as soon as inductor current crosses zero, the
device first deploys diode mode by turning off the low side
MOSFET. If load further decreases, switching frequency is
reduced proportional to the load condition to save switching
losses while keeping output ripple within tolerance. If the
ultrasonic pin is tied to VDD, the minimum switching
frequency in discontinuous mode is > 20 kHz to avoid
switching frequencies in the audible range. If this feature is
not required ultrasonic mode can be disabled by floating the
ULTRASONIC pin. When ultrasonic mode is disabled, the
regulator will operate in forced continuous mode or power
save mode where there is no limit to the lower frequency
limit. In this state, at zero load, switching frequency can go
as low as hundreds of hertz.
Vishay Siliconix
To improve the converter efficiency, the user can choose to
disable the internal VDRV regulator by picking either mode 3
or mode 4 and connecting a 5 V supply to the VDRV pin. This
reduces power dissipation in the SiC46x by eliminating the
VDRV linear regulator losses.
The mode pin supports several modes of operation as
shown in table 1. An internal current source is used to set
the voltage on this pin using an external resistor:
TABLE 1 - OPERATION MODES
MODE
RANGE (kΩ)
1
2
3
4
0 to 100
298 to 304
494 to 504
900 to 1100
POWER SAVE
MODE
Enabled
Disabled
Disabled
Enabled
INTERNAL VDRV
REGULATOR
ON
ON
OFF (1)
OFF (1)
Note
(1) Connect a 5 V (± 5 %) supply to the V
DRV pin
The mode pin is not latched to any state and can be
changed on the fly.
OUTPUT MONITORING AND PROTECTION FEATURES
Output Over-Current Protection (OCP)
SiC46x has pulse-by-pulse over current limit control. The
inductor current is monitored during low side MOSFET
conduction time through RDS(on) sensing. After a pre-defined
blanking time, the inductor current is compared with an
internal OCP threshold. If inductor current is higher than
OCP threshold, high side MOSFET is kept off until the
inductor current falls below OCP threshold.
OCP is enabled immediately after VDD passes UVLO level.
OCP is set by an external resistor, RLIM to AGND. (See table 2)
OCPthreshold
Iload
Iinductor
GH
Fig. 7 - Over-Current Protection Illustration
Output Undervoltage Protection (UVP)
UVP is implemented by monitoring the FB pin. If the voltage
level at FB drops below 0.16 V for more than 25 μs, a UVP
event is recognized and both high side and low side
MOSFETs are turned off. After a duration equivalent to
20 soft start periods, the IC attempts to re-start. If the fault
condition still exists, the above cycle will be repeated.
UVP is only active after the completion of soft-start
sequence.
Output Over Voltage Protection (OVP)
OVP is implemented by monitoring the FB pin. If the voltage
level at FB rising above 0.96 V, a OVP event is recognized
and both high side and low side MOSFETs are turned off.
Normal operation is resumed once FB voltage drop below
0.91 V.
S21-1142-Rev. P, 29-Nov-2021
Over Temperature Protection (OTP)
OTP is implemented by monitoring the junction
temperature. If the junction temperature rises above 150 °C,
a OTP event is recognized and both high side and low
MOSFETs are turned off. After the junction temperature falls
below 115 °C (35 °C hysteresis), the device restarts by
initiating a soft start sequence.
Sequencing of Input / Output Supplies
SiC46x has no sequencing requirements on its supplies or
enables (VIN, VCIN, VDD, VDRV, EN).
Enable
The SiC46x has an enable pin to turn the part on and off.
Driving this pin above 1.35 V enables the device, while
driving the pin below 1.2 V disables the device.
The EN pin is internally pulled to AGND by a 5 MΩ resistor to
prevent unwanted turn on due to a floating GPIO.
Soft-Start
During soft start time period, inrush current is limited and the
output voltage is ramped gradually. The following control
scheme is implemented:
Once the VDD voltage reaches the UVLO trip point, an
internal “Soft start Reference” (SR) begins to ramp up. The
SR ramp rate is determined by the external soft start
capacitor and an internal 5 μA current source tied to the soft
start pin.
The internal SR signal is used as a reference voltage to the
error amplifier (see functional block diagram). The control
scheme guarantees that the output voltage during the soft
start interval will ramp up coincidently with the SR voltage.
The soft-start time, tSS, is adjustable by calculating a
capacitor value from the following equation.
C ss x 0.8 V
t ss = -----------------------------5 μA
During soft-start period, OCP is activated. Short circuit
protection is not active until soft-start is complete.
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Pre-Bias Start-Up
Power Good
In case of pre-bias startup, output is monitored through FB
pin. If the sensed voltage on FB is higher than the internal
reference ramp value, control logic prevents high side and
low side MOSFETs from switching to avoid negative output
voltage spike and excessive current sinking through low
side MOSFET.
SiC46x’s power good is an open-drain output. Pull PGOOD
pin high through a > 10K resistor to use this signal. Power
good window is shown in Fig. 9. If voltage on FB pin is out
of this window, PGOOD signal is de-asserted by pulling down
to AGND. To prevent false triggering during transient events,
PGOOD has a 25 μs blanking time.
VFB_Rising_Vth_OV
(typ. = 0.96 V)
VFB_Falling_Vth_OV
(typ. = 0.91 V)
Vref (0.8 V)
VFB_Falling_Vth_UV
VFB_Rising_Vth_UV
(typ. = 0.72 V)
(typ. = 0.77 V)
VFB
Pull-high
PG
Pull-low
Fig. 9 - PGOOD Window
Fig. 8 - Pre-Bias Start-Up
EXAMPLE SCHEMATIC OF SiC462
EN
R_ EN _ H
R_ EN _ L
560K
8
0.1 μF
C_ boot
Css
SS
Mode
26
VDD
VIN1
ILIMIT
VIN2
Rmode
27
Cdd
PGND2
VFB
PGND3
COMP
60.4K
R_ fsw
R_ FB_ L
22
232K
10 K470pF
Rcomp
VSNS
21
Ccomp
R_ FB_ H
1.8nF
4.7μH
Cx
L
Cdrv
52.3K
23
52.3K
2.2nF
8.66K Cy
Rx
24
AGND
20
SW3
14
15
Analog ground (AGND), and
power ground (PGND) are
tied internally in the SiC46X
SW2
PGND
GL
47 μF
AGND
PGND1
SW1
17
Cin
SiC462
PGND-PAD
13
11
fSW
VDRV
9
10
AGND-PAD
12
30
16
28
2K
1 μF
Rlim
25
Cin _ D
0.1μF
33 nF
19
2
PGOOD
18
4
BOOT
5
VIN-PAD
PGOOD
R_ PGD
ULTRASONIC
7
+ VIN
6 V to 60 V
VCIN
Zero ohm ultrasonic select
102K
PHASE1
29
PHASE2
1
3.3
R_ boot
6
3
EN
Notes in small black text near
component values refer to Vishay
SiC46X spreadsheet calcualtor
references
DNP
R_ U _ SONIC
+ Vout = 5 V
0.1μF
4.7μF
Cout _ D
64 μF
64 μF
Cout _ C
Cout _ B
PGND
Fig. 10 - SiC462 Configured for 6 V to 60 V Input, 5 V Output at 6 A, 500 kHz Operation with Ultrasonic Power Save Mode Enabled
all Ceramic Output Capacitance Design
S21-1142-Rev. P, 29-Nov-2021
Document Number: 65124
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Vishay Siliconix
EXTERNAL COMPONENT SELECTION FOR THE SiC46x
This section explains external component selection for the
SiC46x family of regulators. Component reference
designators in any equation refer to the schematic shown in
Fig. 10.
The online simulation tool PowerCAD helps to make external
component calculation simple. The user simply needs to
enter required operating conditions.
Output Voltage Adjustment
If a different output voltage is needed, simply change the
value of VOUT and solve for R_FB_H based on the following
formula:
R _FB_L ( V OUT - V FB )
R _FB_H = ----------------------------------------------------V FB
where VFB is 0.8 V. R_FB_L should be a maximum of 10 kΩ to
prevent VOUT from drifting at no load.
Switching Frequency Selection
The following equation illustrates the relationship between
frequency, VIN, VOUT, and Rfsw value:
V OUT
R fsw = --------------------------------------------------– 12
f sw x ( 190 x 10 )
Inductor Selection
In order to determine the inductance, the ripple current must
first be defined. Low inductor values allow for the use of
smaller package sizes but create higher ripple current which
can reduce efficiency. Higher inductor values will reduce the
ripple current and, for a given DC resistance, are more
efficient. However, larger inductance translates directly into
larger packages and higher cost. Cost, size, output ripple,
and efficiency are all used in the selection process.
The ripple current will also set the boundary for power save
operation. The SiC46x will typically enter power save mode
when the load current decreases to 1/2 of the ripple current.
For example, if ripple current is 1.8 A, power save operation
will be active for loads less than 0.9 A. If ripple current is set
at 30 % of maximum load current, power save will typically
start at a load which is 15 % of maximum current.
The inductor value is typically selected to provide ripple
current of 25 % to 50 % of the maximum load current. This
provides an optimal trade-off between cost, efficiency, and
transient performance. During the on-time, voltage across
the inductor is (VIN - VOUT). The equations for determining
inductance are shown below.
V OUT
t ON = -----------------------V IN x f sw
and
( V IN - V OUT ) x t ON
L = -------------------------------------------------I OUT_MAX. x K
where, K is the maximum percentage of ripple current. The
designer can quickly make a choice of inductor if the ripple
percentage is decided, usually no more than 30 % however
S21-1142-Rev. P, 29-Nov-2021
higher or lower percentages of IOUT can be acceptable
depending on application. This device allows choices larger
than 30 %.
Other than the inductance the DCR and saturation current
parameters are key values. The DCR causes an I2R loss
which will decrease the system efficiency and generate
heat. The saturation current has to be higher than the
maximum output current plus ½ of the ripple current. In an
over current condition the inductor current may be very high.
All this needs to be considered when selecting the inductor.
Output Capacitor Selection
The SiC46x is stable with any type of output capacitors by
choosing the appropriate VRAMP components. This allows
the user to choose the output capacitance based on the
best trade off of board space, cost and application
requirements.
The output capacitors are chosen based upon required ESR
and capacitance. The maximum ESR requirement is
controlled by the output ripple voltage requirement and the
DC tolerance. The output voltage has a DC value that is
equal to the valley of the output ripple plus half of the
peak-to-peak ripple. A change in the output ripple voltage
will lead to a change in DC voltage at the output. The
relationship between output voltage ripple, output
capacitance and ESR of the output capacitor is shown by
the following equation:
1
V RIPPLE = I RIPPLE ( MAX. ) x --------------------------------- + ESR
8 x C o x f sw
(1)
Where VRIPPLE is the maximum allowed output ripple
voltage; IRIPPLE(MAX.) is the maximum inductor ripple current;
fsw is the switching frequency of the converter; Co is the total
output capacitance; ESR is the equivalent series resistance
of the total output capacitors.
In addition to the output ripple voltage requirement, the
output capacitors need to meet transient requirements. A
worst case load release condition (from maximum load to no
load at the exact moment when inductor current is at the
peak) determines the required capacitance. If the load
release is instantaneous (load changes from maximum to
zero within 1 μs), the output capacitor must absorb all the
energy stored in the inductor. The peak voltage on the
capacitor, VPK, under this worst case condition can be
calculated by following equation:
C OUT_MIN.
2
1
L x I OUT + --- x I RIPPLE(MAX.)
2
= ------------------------------------------------------------------------------2
2
( V PK ) - ( V OUT )
(2)
During the load release time, the voltage across the inductor
is approximately -VOUT. This causes a down-slope or falling
di/dt in the inductor. If the load di/dt is not much faster than
the di/dt of the inductor, then the inductor current will tend
to track the falling load current. This will reduce the excess
inductive energy that must be absorbed by the output
capacitor; therefore a smaller capacitance can be used. The
following can be used to calculate the required capacitance
for a given diLOAD/dt.
Document Number: 65124
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Peak inductor current, ILPK, is shown by the next equation:
1
I LPK = I MAX. + --- x I RIPPLE(MAX.)
2
I VCIN ( RMS ) =
di LOAD
The slew rate of load current = ------------------dt
C OUT_MIN. = I LPK
final application specification. The input current needs to be
determined for the lowest operating input voltage,
IO x
I LPK
I MAX.
L x -------------- - ------------------- x dt
V OUT dI LOAD
x --------------------------------------------------------------2 ( V PK - V OUT )
(3)
Based on application requirement, either equation (2) or
equation (3) can be used to calculate the ideal output
capacitance to meet transition requirement. Compare this
calculated capacitance with the result from equation (1) and
choose the larger value to meet both ripple and transition
requirement.
Enable Pin Voltage
The EN pin has an internal 5 MΩ pull down resistor
connected to AGND. In order to enable the device, an
external signal greater than 1.4 V is required. The enable can
also be used to set the minimum VCIN, VIN startup voltage by
connecting a voltage divider between VIN, EN, and PGND. An
automated calculator is available to assist in component
selection.
Current Limit Resistor
The current limit is set by placing a resistor between ILIM and
AGND. The values can be found using the following equation:
2
V OUT
1
2
D x ( 1 – D ) + ------ × ------------------------------------- × ( 1 – D ) × D
12 L × ƒ sw × I OUT
The minimum input capacitance can then be found,
D x (1 - D)
C VIN_MIN. = I OUT x ----------------------------------------V IN_PK-PK x f sw
If high ESR capacitors are used, it is good practice to also
add low ESR ceramic capacitance. A 4.7 μF ceramic input
capacitance is a suitable starting point.
Note, account for voltage derating of capacitance when
using all ceramic input capacitors.
Efficiency Measurement
Fig. 11 to 39 in the following pages are the efficiency data
for the SiC461, SiC462, SiC463, and SiC464.
The measurements are taken based on the Vishay 6 layers,
2 ounce copper evaluation board.
The inductors used in the measurement are tabulated
below.
TABLE 3 - INDUCTOR VALUES
INDUCTANCE
(μH)
INDUCTOR PART
NUMBER
DCR
(mΩ)
3.3
IHLP6767GZER3R3M11
2.79
4.7
IHLP6767GZER4R7M11
3.98
6.8
IHLP6767GZER6R8M11
5.86
8.2
IHLP6767GZER8R2M11
7.71
Where
10
IHLP6767GZER100M11
8.89
• IOUT_MAX. is desired DC current limit level
5.6
IHLP5050FDER5R6M51
8.51
6.8
IHLP5050FDER6R8M51
11.30
8.2
IHLP5050FDER8R2M51
13.20
10
IHLP5050FDER100M51
16.60
15
IHLP5050FDER150M51
24.00
10
IHLP5050FDER100M51
16.60
15
IHLP5050FDER150M51
24.00
22
IHLP5050FDER220M51
31.30
10
IHLP5050FDER100M51
16.60
15
IHLP5050FDER150M51
24.00
22
IHLP5050FDER220M51
31.30
R LIM
K LIM
(kΩ ) = ---------------------------------------------------------------------------------------( V IN – V OUT ) × V OUT
I OUT_MAX. – -----------------------------------------------------2 × f sw × V IN × L
• KLIM is determined by Table 2
DEVICE
PART
SiC461
SiC462
TABLE 2 - KLIM VALUE
PART NUMBER
KLIM
SiC461
780K
SiC462
480K
SiC463
240K
SiC464
240K
Note
• It is suggested that the current limit setting not be higher than
2 times the rated current of the part. Be sure max. current limit
is within the saturation current of the inductor
SiC463
SiC464
Input Capacitance
In order to determine the minimum capacitance the input
voltage ripple needs to be specified; VIN_PK-PK ≤ 500 mV is a
suitable starting point. This magnitude is determined by the
S21-1142-Rev. P, 29-Nov-2021
Document Number: 65124
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ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC461 (10 A), unless otherwise noted)
100
100
VIN = 12 V, L = 3.3 μH
96
94
94
91
92
88
90
VIN = 36 V, L = 4.7 μH
88
VIN = 12 V, L = 3.3 μH
97
VIN = 24 V, L = 4.7 μH
Efficiency (%)
Efficiency (%)
98
86
VIN = 24 V, L = 4.7 μH
85
82
VIN = 36 V, L = 4.7 μH
79
VIN = 48 V, L = 4.7 μH
84
VIN = 48 V, L = 4.7 μH
76
82
73
80
70
0
1
2
3
4
5
6
7
8
9
0.01
10
0.1
1
Output Current, IOUT (A)
Output Current, IOUT (A)
Fig. 11 - SiC461 Efficiency vs. Output Current,
VOUT = 5 V
Fig. 14 - SiC461 Efficiency vs. Output Current - Light Load,
VOUT = 5 V
100
100
VIN = 24 V, L = 6.8 μH
98
97
96
94
94
VIN = 24 V, L = 6.8 μH
91
92
90
Efficiency (%)
Efficiency (%)
VIN = 36 V, L = 8.2 μH
VIN = 48 V, L = 10 μH
88
82
79
84
76
82
73
70
0
1
2
3
4
5
6
7
8
9
10
0.01
0.1
1
Output Current, IOUT (A)
Output Current, IOUT (A)
Fig. 12 - SiC461 Efficiency vs. Output Current,
VOUT = 12 V
Fig. 15 - SiC461 Efficiency vs. Output Current - Light Load,
VOUT = 12 V
100
100
90
90
80
80
Case Temperature (°C)
Case Temperature(°C)
VIN = 48 V, L = 10 μH
85
86
80
VIN = 36 V, L = 8.2 μH
88
70
60
50
40
30
70
60
50
40
30
20
20
0
1
2
3
4
5
6
7
8
9
10
Output Current (A)
Fig. 13 - SiC461 Load Current vs. Case Temperature,
VIN = 48 V, VOUT = 5 V
S21-1142-Rev. P, 29-Nov-2021
0
1
2
3
4
5
6
7
Output Current (A)
8
9
10
Fig. 16 - SiC461 Load Current vs. Case Temperature,
VIN = 48 V, VOUT = 12 V
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ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC462 (6 A), unless otherwise noted)
100
100
VIN = 12 V, L = 5.6 μH
VIN = 24 V, L = 6.8 μH
96
94
94
91
92
88
90
VIN = 36 V, L = 8.2 μH
88
VIN = 48 V, L = 8.2 μH
VIN = 12 V, L = 5.6 μH
97
Efficiency (%)
Efficiency (%)
98
85
82
86
79
84
76
82
73
80
VIN = 24 V, L = 6.8 μH
VIN = 36 V, L = 8.2 μH
VIN = 48 V, L = 8.2 μH
70
0.0
1.0
2.0
3.0
4.0
5.0
0.0
6.0
0.1
Output Current, IOUT (A)
Fig. 17 - SiC462 Efficiency vs. Output Current,
VOUT = 5 V
Fig. 20 - SiC462 Efficiency vs. Output Current - Light Load,
VOUT = 5 V
100
100
VIN = 24 V, L = 10 μH
98
97
96
94
VIN = 24 V , L = 10 μH
91
VIN = 36 V, L = 15 μH
92
Efficiency (%)
Efficiency (%)
94
90
VIN = 48 V, L = 15 μH
88
88
VIN = 36 V, L = 15 μH
85
82
86
79
84
76
82
73
80
VIN = 48 V, L = 15 μH
70
0.0
1.0
2.0
3.0
4.0
5.0
0.01
6.0
0.1
1
Output Current, IOUT (A)
Output Current, IOUT (A)
Fig. 18 - SiC462 Efficiency vs. Output Current,
VOUT = 12 V
Fig. 21 - SiC462 Efficiency vs. Output Current - Light Load,
VOUT = 12 V
100
100
90
90
80
80
Case Temperature (°C)
Case Temperature (°C)
1.0
Output Current, IOUT (A)
70
60
50
40
30
70
60
50
40
30
20
20
0.0
0.6
1.2
1.8
2.4
3.0
3.6
4.2
4.8
5.4
6.0
Output Current (A)
Fig. 19 - SiC462 Load Current vs. Case Temperature,
VIN = 48 V, VOUT = 5 V
S21-1142-Rev. P, 29-Nov-2021
0.0
0.6
1.2
1.8
2.4 3.0 3.6 4.2
Output Current (A)
4.8
5.4
6.0
Fig. 22 - SiC462 Load Current vs. Case Temperature,
VIN = 48 V, VOUT = 12 V
Document Number: 65124
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SiC461, SiC462, SiC463, SiC464
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Vishay Siliconix
ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC463 (4 A), unless otherwise noted)
100
100
VIN = 24 V, L = 15 μH
VIN = 12 V, L = 10 μH
96
94
94
91
92
90
VIN = 36 V, L = 15 μH
88
VIN = 48 V, L = 15 μH
86
VIN = 12 V, L = 10 μH
VIN = 24 V, L = 15 μH
97
Efficiency (%)
Efficiency (%)
98
88
85
82
VIN = 36 V, L = 15 μH
79
84
76
82
73
80
VIN = 48 V, L = 15 μH
70
0.0
1.0
2.0
3.0
0.01
4.0
0.1
Output Current, IOUT (A)
1
Output Current, IOUT (A)
Fig. 23 - SiC463 Efficiency vs. Output Current,
VOUT = 5 V
Fig. 26 - SiC463 Efficiency vs. Output Current - Light Load,
VOUT = 5 V
100
100
VIN = 24 V, L = 15 μH
98
97
96
94
91
VIN = 36 V, L = 22 μH
92
Efficiency (%)
Efficiency (%)
94
90
VIN = 48 V, L = 22 mH
88
88
VIN = 36 V, L = 22 μH
85
VIN = 48 V, L = 22 μH
82
86
79
84
76
82
73
80
70
0.0
1.0
2.0
3.0
0.01
4.0
0.1
1
Output Current, IOUT (A)
Output Current, IOUT (A)
Fig. 24 - SiC463 Efficiency vs. Output Current,
VOUT = 12 V
Fig. 27 - SiC463 Efficiency vs. Output Current - Light Load,
VOUT = 12 V
100
100
90
90
80
80
Case Temperature (°C)
Case Temperature (°C)
VIN = 24 V, L = 15 μH
70
60
50
40
70
60
50
40
30
30
20
20
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
Output Current (A)
Output Current (A)
Fig. 25 - SiC463 Load Current vs. Case Temperature,
VIN = 48 V, VOUT = 5 V
Fig. 28 - SiC463 Load Current vs. Case Temperature,
VIN = 48 V, VOUT = 12 V
S21-1142-Rev. P, 29-Nov-2021
Document Number: 65124
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ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC464 (2 A), unless otherwise noted)
100
100
VIN = 12 V, L = 10 μH
VIN = 12 V, L = 10 μH
97
VIN = 24 V, L = 15 μH
96
94
94
91
92
88
90
Efficiency (%)
Efficiency (%)
98
VIN = 36 V, L = 15 μH
88
86
VIN = 24 V, L = 15 μH
85
82
VIN = 36 V, L = 15 μH
79
VIN = 48 V, L = 15 μH
VIN = 48 V, L = 15 μH
84
76
82
73
80
70
0.0
0.5
1.0
1.5
2.0
0.01
0.1
Output Current, IOUT (A)
Fig. 29 - SiC464 Efficiency vs. Output Current,
VOUT = 5 V
Fig. 32 - SiC464 Efficiency vs. Output Current - Light Load,
VOUT = 5 V
100
100
97
96
94
94
91
92
Efficiency (%)
Efficiency (%)
VIN = 24 V, L = 15 μH
VIN = 24 V, L = 15 μH
98
VIN = 36 V, L = 22 μH
90
88
VIN = 48 V, L = 22 μH
88
VIN = 36 V, L = 22 μH
85
VIN = 48 V, L = 22 μH
82
86
79
84
76
82
73
70
80
0.0
0.3
0.5
0.8
1.0
1.3
1.5
1.8
2.0
0.01
0.1
1
Output Current, IOUT (A)
Output Current, IOUT (A)
Fig. 30 - SiC464 Efficiency vs. Output Current,
VOUT = 12 V
Fig. 33 - SiC464 Efficiency vs. Output Current - Light Load,
VOUT = 12 V
100
100
90
90
80
80
Case Temperature (°C)
Case Temperature (°C)
1
Output Current, IOUT (A)
70
60
50
40
30
70
60
50
40
30
20
20
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Output Current (A)
Fig. 31 - SiC464 Load Current vs. Case Temperature,
VIN = 48 V, VOUT = 5 V
S21-1142-Rev. P, 29-Nov-2021
0.0
0.2
0.4
0.6 0.8 1.0 1.2 1.4
Output Current (A)
1.6
1.8
2.0
Fig. 34 - SiC464 Load Current vs. Case Temperature,
VIN = 48 V, VOUT = 12 V
Document Number: 65124
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1.04
1.04
1.03
1.03
1.02
1.02
Normalized Efficiency
Normalized Efficiency
ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC462 (6 A), unless otherwise noted)
1.01
1
0.99
1.01
1
0.99
0.98
0.98
0.97
0.97
0.96
0.96
200 250 300 350 400 450 500 550 600 650 700
0
Switching Frequency (kHz)
Fig. 38 - SiC462 Efficiency vs. Switching Frequency
1.04
1.04
1.03
1.03
1.02
1.02
Normalized Efficiency
Normalized Efficiency
Fig. 35 - SiC461 Efficiency vs. Switching Frequency
1.01
1
0.99
100 200 300 400 500 600 700 800 900 1000
Switching Frequency (kHz)
1.01
1
0.99
0.98
0.98
0.97
0.97
0.96
0.96
0
0
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
Switching Frequency (kHz)
Switching Frequency (kHz)
Fig. 39 - SiC464 Efficiency vs. Switching Frequency
2.00
808
1.75
806
Voltage Reference, VFB (mv)
Normalized On-State Resistance, RDSON
Fig. 36 - SiC463 Efficiency vs. Switching Frequency
1.50
1.25
1.00
0.75
0.50
0.25
804
802
800
798
796
794
0.00
-60 -40 -20
792
0
20
40
60
80
100 120 140
-60 -40 -20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
Fig. 37 - RDS(ON) vs. Temperature
Fig. 40 - Voltage Reference vs. Temperature
S21-1142-Rev. P, 29-Nov-2021
Document Number: 65124
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0.8
0.8
0.6
0.6
0.4
0.4
Load Regulation (%)
Line Regulation (%)
ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC462 (6 A), unless otherwise noted)
0.2
0.0
-0.2
-0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
0
6
12
18
24 30 36 42
Input Voltage (V)
48
54
0.0
60
1.8
2.4
3.0
3.6
4.2
4.8
5.4
6.0
Fig. 44 - Load Regulation
8.0
8.0
Shutdown Current, IVCIN_SHDN + IVIN_SHDN (uA)
Shutdown Current, IVCIN_SHDN + IVIN_SHDN (uA)
1.2
Output Current (A)
Fig. 41 - Line Regulation
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
0
6
12
18
24
30
36
42
48
54
60
-60 -40 -20
0
20
40
60
80
100 120 140
Input Voltage, VCIN / VIN (V)
Temperature (°C)
Fig. 42 - Shutdown Current vs. Input Voltage
Fig. 45 - Shutdown Current vs. Junction Temperature
300
300
280
280
Input Current, IVCIN + IVIN (uA)
Input Current, IVCIN + IVIN (uA)
0.6
260
240
220
200
180
160
260
240
220
200
180
160
140
140
0
6
12
18
24
30
36
42
48
54
Input Voltage, VCIN / VIN (V)
Fig. 43 - Input Current vs. Input Voltage
S21-1142-Rev. P, 29-Nov-2021
60
-60 -40 -20
0
20 40 60 80
Temperature (°C)
100 120 140
Fig. 46 - Input Current vs. Junction Temperature
Document Number: 65124
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ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC462 (6 A), unless otherwise noted)
1.5
1.4
VEN = 5.0 V
1.3
1.4
VIH_EN
1.2
1.4
EN Current, IEN (uA)
EN Logic Threshold, VEN (V)
1.5
1.3
1.3
VIL_EN
1.2
1.2
1.1
1.0
0.9
0.8
1.1
0.7
1.1
1.0
-60 -40 -20
0
20
40
60
80
100 120 140
Temperature (°C)
0.6
-60 -40 -20
0
20
40
60
80
100 120 140
Temperature (°C)
Fig. 47 - EN Logic Threshold vs. Junction Temperature
Fig. 50 - EN Current vs. Junction Temperature
Fig. 48 - Load Transient (3 A to 6 A), Time = 100 μs/div
Fig. 51 - Line Transient (8 V to 48 V), Time = 10 ms/div
Fig. 49 - Start-Up with EN, Time = 1 ms/div
Fig. 52 - Start-up with VIN, Time = 5 ms/div
S21-1142-Rev. P, 29-Nov-2021
Document Number: 65124
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ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC462 (6 A), unless otherwise noted)
Fig. 53 - Output Ripple 2 A, Time = 5 μs/div
Fig. 55 - Output Ripple 300 mA, Time = 5 μs/div
Fig. 54 - Output Ripple PSM, Time = 10 ms/div
S21-1142-Rev. P, 29-Nov-2021
Document Number: 65124
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PCB LAYOUT RECOMMENDATIONS
VIN Plane
PGND Plane
VIN
Snubber
Step 3: SW Plane
Step 1: VIN/GND Planes and Decoupling
VSWH
PGND Plane
VSWH
Fig. 58
Fig. 56
5. Layout VIN and PGND planes as shown above
6. Ceramic capacitors should be placed between VIN and
PGND, and very close to the device for best decoupling
effect
7. Various ceramic capacitor values and package sizes
should be used to cover entire coupling spectrum
e.g. 1210 and 0603
1. Connect output inductor to device with large plane to
lower resistance
2. If any snubber network is required, place the
components on the bottom side as shown above
Step 4: VDD/VDRV Input Filter
8. Smaller capacitance values, closer to VIN pin(s), provide
better high frequency response
Step 2: VCIN Pin
AGND
Vcin decouple cap
P
G
N
D
AGND Plane
Fig. 59
Fig. 57
1. VCIN is the input pin for both internal LDO and tON block.
tON varies with input voltage and it is necessary to put a
decoupling capacitor close to this pin
2. The connection can be made through a via and the
capacitor can be placed at bottom layer
S21-1142-Rev. P, 29-Nov-2021
1. CVDD cap should be placed between VDD and AGND to
achieve best noise filtering
2. CVDRV cap should be placed close to VDRV and PGND pins
to reduce effects of trace impedance and provide
maximum instantaneous driver current for low side
MOSFET during switching cycle
Document Number: 65124
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Step 5: BOOT Resistor and Capacitor Placement
Vishay Siliconix
Step 6: Signal Routing
AGND
plane
PGND
F
B
s
i
g
Ripple n
injection a
l
circuit
Fig. 60
1. CBOOT and RBOOT need to be placed very close to the
device, between PHASE and BOOT pins
2. In order to reduce parasitic inductance, it is
recommended to use 0402 chip size for the resistor and
the capacitor
Fig. 61
1. Separate the small analog signal from high current path.
As shown above, the high current paths with high dv/dt,
di/dt are placed on the left side of the IC, while the small
control signals are placed on the right side of the IC. All
the components for small analog signal should be
placed closer to IC with minimum trace length
2. IC analog ground (AGND), pin 23, should have a single
connection to PGND. The AGND ground plane connected
to pin 23 helps to keep AGND quiet and improves noise
immunity
3. Feedback signal can be routed through inner layer. Make
sure this signal is far from SW node and shielded by
inner ground layer
4. Ripple injection circuit can be placed next to inductor.
Kelvin connection as shown above is recommended
S21-1142-Rev. P, 29-Nov-2021
Document Number: 65124
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Step 7: Adding Thermal Relief Vias and Duplicate Power
Path Plane
VIN Plane
Vishay Siliconix
Step 8: Ground Layer
AGND Plane
PGND Plane
PGND Plane
VSWH
Fig. 63
Fig. 62
1. Thermal relief vias can be added on the VIN and PGND
pads to utilize inner layers for high current and thermal
dissipation
2. To achieve better thermal performance, additional vias
can be placed on VIN and PGND planes. It is also
necessary to duplicate the VIN and ground plane at
bottom layer to maximize the power dissipation
capability of the PCB
1. It is recommended to make the entire inner layer (next to
top layer) ground plane
2. This ground plane provides shielding between noise
source on top layer and signal trace within inner layer
3. The ground plane can be broken into two sections, PGND
and AGND
3. SW pad is a noise source and it is not recommended to
place vias on this pad
4. 8 mil vias on pads and 10 mil vias on planes are ideal via
sizes. The vias on pad may drain solder during assembly
and cause assembly issues. Please consult with the
assembly house for guideline
S21-1142-Rev. P, 29-Nov-2021
Document Number: 65124
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Vishay Siliconix
PRODUCT SUMMARY
Part number
SiC461
SiC462
SiC463
SiC464
Description
10 A, 4.5 V to 60 V input,
100 kHz to 2 MHz,
synchronous buck
regulator
6 A, 4.5 V to 60 V input,
100 kHz to 2 MHz,
synchronous buck
regulator
4 A, 4.5 V to 60 V input,
100 kHz to 2 MHz,
synchronous buck
regulator
2 A, 4.5 V to 60 V input,
100 kHz to 2 MHz,
synchronous buck
regulator
Input voltage min. (V)
4.5
4.5
4.5
4.5
Input voltage max. (V)
60
60
60
60
Output voltage min. (V)
0.8
0.8
0.8
0.8
0.92 x VIN
Output voltage max. (V)
0.92 x VIN
0.92 x VIN
0.92 x VIN
Continuous current (A)
10
6
4
2
Switch frequency min. (kHz)
100
100
100
100
Switch frequency max. (kHz)
2000
2000
2000
2000
Pre-bias operation (yes / no)
Yes
Yes
Yes
Yes
Internal bias reg. (yes / no)
Yes
Yes
Yes
Yes
External
External
External
External
Enable (yes / no)
Yes
Yes
Yes
Yes
PGOOD (yes / no)
Yes
Yes
Yes
Yes
Overcurrent protection
Yes
Yes
Yes
Yes
Protection
OVP, OCP, UVP/SCP,
OTP, UVLO
OVP, OCP, UVP/SCP,
OTP, UVLO
OVP, OCP, UVP/SCP,
OTP, UVLO
OVP, OCP, UVP/SCP,
OTP, UVLO
Light load mode
Selectable powersave /
ultrasonic
Selectable powersave /
ultrasonic
Selectable powersave /
ultrasonic
Selectable powersave /
ultrasonic
Compensation
Peak efficiency (%)
Package type
Package size (W, L, H) (mm)
98
98
98
98
PowerPAK MLP55-27L
PowerPAK MLP55-27L
PowerPAK MLP55-27L
PowerPAK MLP55-27L
5 x 5 x 0.75
5 x 5 x 0.75
5 x 5 x 0.75
5 x 5 x 0.75
Status code
2
2
2
2
Product type
microBUCK
(step down regulator)
microBUCK
(step down regulator)
microBUCK
(step down regulator)
microBUCK
(step down regulator)
Applications
Computing, consumer,
industrial, healthcare,
networking
Computing, consumer,
industrial, healthcare,
networking
Computing, consumer,
industrial, healthcare,
networking
Computing, consumer,
industrial, healthcare,
networking
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?65124.
S21-1142-Rev. P, 29-Nov-2021
Document Number: 65124
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Package Information
www.vishay.com
Vishay Siliconix
PowerPAK® MLP55-27 Case Outline
27
L
F2
e1 x 3
e2
6
12
K4
e
E2-2
K2
D2-2
D2-3
7
K6
C
K3
11
11
12
E2-3
E2-4
ex2
6
7
B
e1
D2-4
b
b1
E
MLP55-27L
(5 mm x 5 mm)
1
D2-1
K E2-1
(4)
19
K1
19
1
K4
ex7
20
K4
A1
A2
K5
0.08 C
K4
A
20
27
0.10 C A
ex4
2x
D
A
0.10 M C A B
Pin 1 dot
by marking
F1
K7
Top view
ex2
e3
Side view
e1
K8
Bottom view
DIM.
A
(8)
A1
MILLIMETERS
INCHES
MIN.
NOM.
MAX.
MIN.
NOM.
0.70
0.75
0.80
0.027
0.029
0.031
0.00
-
0.05
0.000
-
0.002
A2
0.20 ref.
MAX.
0.008 ref.
b (4)
0.20
0.25
0.30
0.008
0.010
0.012
b1
0.15
0.20
0.25
0.006
0.008
0.010
D
5.00 BSC
0.197 BSC
e
0.50 BSC
0.020 BSC
e1
0.65 BSC
0.026 BSC
e2
1.00 BSC
0.039 BSC
e3
1.13 BSC
0.044 BSC
E
5.00 BSC
0.197 BSC
L
0.35
N (3)
0.40
0.45
0.014
28
0.016
0.018
28
D2-1
3.25
3.30
3.35
0.128
0.130
0.132
D2-2
0.95
1.00
1.05
0.037
0.039
0.041
D2-3
1.95
2.00
2.05
0.077
0.079
0.081
D2-4
1.37
1.42
1.47
0.054
0.056
0.058
E2-1
0.95
1.00
1.05
0.037
0.039
0.041
E2-2
2.55
2.60
2.65
0.100
0.102
0.104
E2-3
2.55
2.60
2.65
0.100
0.102
0.104
E2-4
1.58
1.63
1.68
0.062
0.064
0.066
F1
0.20
-
0.25
0.008
-
0.010
F2
Revision: 03-Dec-2018
min. 0.20
min. 0.008
Document Number: 69722
1
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Package Information
www.vishay.com
DIM.
Vishay Siliconix
MILLIMETERS
MIN.
NOM.
INCHES
MAX.
MIN.
NOM.
K
0.40 BSC
0.016 BSC
K1
0.70 BSC
0.028 BSC
K2
0.70 BSC
0.028 BSC
K3
0.30 BSC
0.012 BSC
K4
0.75 BSC
0.030 BSC
K5
0.80 BSC
0.0315 BSC
K6
0.60 BSC
0.024 BSC
K7
1.25 BSC
0.049 BSC
K8
0.975 BSC
0.038 BSC
MAX.
ECN: T18-0594-Rev. C, 03-Dec-2018
DWG: 6056
Notes
(1) Use millimeters as the primary measurement
(2) Dimensioning and tolerances conform to ASME Y14.5M. - 1994
(3) N is the number of terminals
Nd is the number of terminals in x-direction
Ne is the number of terminals in y-direction
(4) Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip
(5) The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
(6) Exact shape and size of this feature is optional
(7) Package warpage max. 0.08 mm
(8) Applied only for terminals
Revision: 03-Dec-2018
Document Number: 69722
2
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PAD Pattern
www.vishay.com
Vishay Siliconix
Recommended Land Pattern
PowerPAK® MLP55-27L
1.25
1.25
0.5 x 7 = 3.5
0.35
0.35
3.4
20
0.5
0.35
27
0.3
0.35
19
0.5 x 4 = 2
0.3
0.65 x 3 = 1.95
1.1
1
0.88
5
0.58
0.97
1.52
0.5
1.73
0.5 x 2 = 1
2.7
1
1.02
6
0.98
0.65
0.5
0.5
12
0.6
0.75
1.13
0.65
0.8
0.5
0.95
0.75
0.95
0.15
0.95
11
0.5
7
0.5
0.5
1.1
0.3
0.95
2.1
0.3
0.3
5
All dimensions in millimeters
Component for MLP55-27L
Land pattern for MLP55-27L
Revision: 24-Jan-18
Document Number: 74550
1
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Vishay
Disclaimer
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Revision: 09-Jul-2021
1
Document Number: 91000
