SiC531, SiC531A
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Vishay Siliconix
30 A VRPower® Integrated Power Stage
DESCRIPTION
FEATURES
The SiC531 and SiC531A are integrated power stage
solutions optimized for synchronous buck applications
to offer high current, high efficiency, and high power
density performance. Packaged in Vishay’s proprietary
4.5 mm x 3.5 mm MLP package, SiC531 and SiC531A
enable voltage regulator designs to deliver up to 30 A
continuous current per phase.
• Thermally enhanced PowerPAK® MLP4535-22L
package
The
internal
power
MOSFETs
utilize
Vishay’s
state-of-the-art Gen IV TrenchFET® technology that delivers
industry benchmark performance to significantly reduce
switching and conduction losses.
The SiC531 and SiC531A incorporate an advanced
MOSFET gate driver IC that features high current driving
capability, adaptive dead-time control, an integrated
bootstrap Schottky diode, and zero current detection to
improve light load efficiency. The drivers are also
compatible with a wide range of PWM controllers, support
tri-state PWM, and 3.3 V (SiC531A) / 5 V (SiC531) PWM
logic.
• Vishay’s Gen IV MOSFET technology and a
low-side MOSFET with integrated Schottky
diode
• Delivers up to 30 A continuous current, 35 A at 10 ms peak
current
• High efficiency performance
• High frequency operation up to 1.5 MHz
• Power MOSFETs optimized for 19 V input stage
• 3.3 V (SiC531A) / 5 V (SiC531) PWM logic with tri-state and
hold-off
• Zero current detect control for light load efficiency
improvement
• Low PWM propagation delay (< 20 ns)
• Under voltage lockout for VCIN
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
• Multi-phase VRDs for computing, graphics card and
memory
• Intel IMVP-8 VRPower delivery
- VCORE, VGRAPHICS, VSYSTEM
platforms
AGENT
Skylake, Kabylake
- VCCGI for Apollo Lake platforms
• Up to 18 V rail input DC/DC VR modules
TYPICAL APPLICATION DIAGRAM
5V
VIN
V IN
VDRV
BOOT
PHASE
VCIN
ZCD_EN#
PWM
controller
PWM
VSWH
VOUT
Gate
driver
PGND
GL
C GND
Fig. 1 - SiC531 and SiC531A Typical Application Diagram
S20-0486-Rev. B, 29-Jun-2020
Document Number: 65999
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PGND
PGND
PGND
VIN
VIN
VIN
PINOUT CONFIGURATION
11
10
9
8
7
6
25
VIN
VSWH 12
26
PGND
VSWH 13
VSWH 14
23
CGND
VSWH 15
24
GL
18
19
20
21
22
GL
PGND
VDRV
PWM
PGND
17
PGND
VSWH 16
5
PHASE
4
BOOT
3
CGND
2
VCIN
1
ZCD_EN#
Fig. 2 - SiC531 and SiC531A Pin Configuration
PIN DESCRIPTION
PIN NUMBER
NAME
FUNCTION
1
ZCD_EN#
The ZCD_EN# pin enables or disables Diode Emulation. When ZCD_EN# is low, diode
emulation is allowed. When ZCD_EN# is high, continuous conduction mode is forced.
ZCD_EN# can also be put in a high impedance mode by floating the pin. If both
ZCD_EN# and PWM are floating, the device shuts down and consumes typically 3 μA
(9 μA max.) current
2
VCIN
Supply voltage for internal logic circuitry
3, 23
CGND
Signal ground
4
BOOT
High-side driver bootstrap voltage
5
PHASE
6 to 8, 25
VIN
Return path of high-side gate driver
Power stage input voltage. Drain of high-side MOSFET
9 to 11, 17, 18, 20, 26
PGND
Power ground
12 to 16
VSWH
Phase node of the power stage
19, 24
GL
21
VDRV
Supply voltage for internal gate driver
22
PWM
PWM input logic
Low-side MOSFET gate signal
ORDERING INFORMATION
PART NUMBER
SiC531CD-T1-GE3
SiC531ACD-T1-GE3
SiC531ADB and SiC531DB
PACKAGE
PowerPAK® MLP4535-22L
MARKING CODE
SiC531
5 V PWM optimized
SiC531A
3.3 V PWM optimized
Reference board
S20-0486-Rev. B, 29-Jun-2020
Document Number: 65999
2
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PART MARKING INFORMATION
=
pin 1 indicator
P/N =
P/N
part number code
=
Siliconix logo
=
ESD symbol
F
=
assembly factory code
Y
=
year code
WW
=
week code
LL
=
lot code
LL
FYWW
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL PARAMETER
CONDITIONS
LIMIT
VIN
-0.3 to 28
Control logic supply voltage
VCIN
-0.3 to 7
Drive supply voltage
VDRV
Input voltage
Switch node (DC voltage)
BOOT voltage (DC voltage)
BOOT voltage (AC voltage)
-0.3 to 7
-0.3 to 28
VSWH
Switch node (AC voltage) (1)
-8 to 35
BOOT to PHASE (DC voltage)
40
-0.3 to 7
VBOOT- PHASE
BOOT to PHASE (AC voltage) (3)
-0.3 to 8
All logic inputs and outputs
(PWM and ZCD_EN#)
-0.3 to VCIN +0.3
Max. operating junction temperature
TJ
150
Ambient temperature
TA
-40 to 125
Storage temperature
Tstg
-65 to 150
Human body model, JESD22-A114
3000
Charged device model, JESD22-C101
1000
Electrostatic discharge protection
V
33
VBOOT
(2)
UNIT
°C
V
Note
(1) The specification values indicated “AC” is V
SWH to PGND, -8 V (< 20 ns, 10 μJ), min. and 30 V (< 50 ns), max.
(2) The specification value indicates “AC voltage” is V
BOOT to PGND, 36 V (< 50 ns) max.
(3) The specification value indicates “AC voltage” is V
BOOT to VPHASE, 8 V (< 20 ns) max.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
ELECTRICAL PARAMETER
MINIMUM
TYPICAL
MAXIMUM
Input voltage (VIN)
4.5
-
24
Drive supply voltage (VDRV)
4.5
5
5.5
Control logic supply voltage (VCIN)
4.5
5
5.5
BOOT to PHASE (VBOOT-PHASE, DC voltage)
4
4.5
5.5
Thermal resistance from junction to PCB
-
5
-
Thermal resistance from junction to case
-
2.5
-
S20-0486-Rev. B, 29-Jun-2020
UNIT
V
°C/W
Document Number: 65999
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ELECTRICAL SPECIFICATIONS
(ZCD_EN# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 °C)
PARAMETER
SYMBOL
TEST CONDITION
MIN.
LIMITS
TYP.
MAX.
UNIT
POWER SUPPLY
Control logic supply current
IVCIN
Drive supply current
IVDRV
No switching, VPWM = FLOAT
-
300
-
fS = 300 kHz, D = 0.1
-
300
-
fS = 300 kHz, D = 0.1
-
8
15
fS = 1 MHz, D = 0.1
-
30
-
No switching, VPWM = FLOAT
-
50
-
μA
IF = 2 mA
-
-
0.4
V
μA
mA
BOOTSTRAP SUPPLY
Bootstrap diode forward voltage
VF
PWM CONTROL INPUT (SiC531)
Rising threshold
VTH_PWM_R
3.4
3.7
4.0
Falling threshold
VTH_PWM_F
0.72
0.9
1.1
Tri-state voltage
VTRI
-
2.3
-
Tri-state rising threshold
VTRI_TH_R
0.9
1.15
1.38
Tri-state falling threshold
VTRI_TH_F
3.1
3.35
3.6
Tri-state rising threshold hysteresis
VHYS_TRI_R
-
225
-
Tri-state falling threshold hysteresis
VHYS_TRI_F
-
325
-
VPWM = 5 V
-
-
350
VPWM = 0 V
-
-
-350
PWM input current
IPWM
VPWM = FLOAT
V
mV
μA
PWM CONTROL INPUT (SiC531A)
Rising threshold
VTH_PWM_R
2.2
2.45
2.7
Falling threshold
VTH_PWM_F
0.72
0.9
1.1
Tri-state voltage
VTRI
-
1.8
-
VPWM = FLOAT
Tri-state rising threshold
VTRI_TH_R
0.9
1.15
1.38
Tri-state falling threshold
VTRI_TH_F
1.95
2.2
2.45
Tri-state rising threshold hysteresis
VHYS_TRI_R
-
225
-
Tri-state falling threshold hysteresis
VHYS_TRI_F
-
275
-
PWM input current
VPWM = 3.3 V
-
-
225
VPWM = 0 V
-
-
-225
tPD_TRI_R
-
20
-
IPWM
V
mV
μA
TIMING SPECIFICATIONS
Tri-state to GH/GL rising
propagation delay
tTSHO
-
150
-
GH - turn off propagation delay
tPD_OFF_GH
-
20
-
GH - turn on propagation delay
(dead time rising)
tPD_ON_GH
-
10
-
GL - turn off propagation delay
tPD_OFF_GL
-
20
-
GL - turn on propagation delay
(dead time falling)
tPD_ON_GL
-
10
-
tPWM_ON_MIN
30
-
-
Tri-state hold-off time
PWM minimum on-time
No load, see fig. 4
ns
ZCD_EN# INPUT
ZCD_EN# logic input voltage
VIH_ZCD_EN#
Input logic high
2
-
-
VIL_ZCD_EN#
Input logic low
-
-
0.8
VCIN rising, on threshold
-
3.7
4.1
VCIN falling, off threshold
2.7
3.1
-
-
575
-
V
PROTECTION
Under voltage lockout
Under voltage lockout hysteresis
VUVLO
VUVLO_HYST
V
mV
Notes
(1) Typical limits are established by characterization and are not production tested
(2) Guaranteed by design
S20-0486-Rev. B, 29-Jun-2020
Document Number: 65999
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Vishay Siliconix
DETAILED OPERATIONAL DESCRIPTION
PWM Input with Tri-state Function
Ground Connections (CGND and PGND)
The PWM input receives the PWM control signal from the VR
controller IC. The PWM input is designed to be compatible
with standard controllers using two state logic (H and L) and
advanced controllers that incorporate tri-state logic (H, L,
and tri-state) on the PWM output. For two state logic, the
PWM input operates as follows. When PWM is driven above
VPWM_TH_R the low-side is turned off and the high-side is
turned on. When PWM input is driven below VPWM_TH_F the
high-side is turned off and the low-side is turned on. For
tri-state logic, the PWM input operates as previously stated
for driving the MOSFETs when PWM is logic high and logic
low. However, there is a third state that is entered as the
PWM output of tri-state compatible controller enters its high
impedance state during shut-down. The high impedance
state of the controller’s PWM output allows the SiC531 and
SiC531A to pull the PWM input into the tri-state region (see
definition of PWM logic and tri-state, fig. 4). If the PWM input
stays in this region for the tri-state hold-off period, tTSHO,
both high-side and low-side MOSFETs are turned off. The
function allows the VR phase to be disabled without
negative output voltage swing caused by inductor ringing
and saves a Schottky diode clamp. The PWM and tri-state
regions are separated by hysteresis to prevent false
triggering. The SiC531A incorporates PWM voltage
thresholds that are compatible with 3.3 V logic and the
SiC531 thresholds are compatible with 5 V logic.
PGND (power ground) should be externally connected to
CGND (signal ground). The layout of the printed circuit board
should be such that the inductance separating CGND and
PGND is minimized. Transient differences due to inductance
effects between these two pins should not exceed 0.5 V.
Diode Emulation Mode (ZCD_EN#)
When ZCD_EN# pin is logic low and PWM signal switches
low, GL is forced ON (after normal BBM time). During this
time, it is under control of the ZCD (zero crossing detect)
comparator. If, after the internal blanking delay, the inductor
current becomes zero, the low-side is turned OFF. This
improves light load efficiency by avoiding discharge of
output capacitors. If PWM enters tri-state, then device will
go into normal tri-state mode after tri-state delay. The GL
output will be turned OFF regardless of Inductor current, this
is an alternative method of improving light load efficiency by
reducing switching losses.
Voltage Input (VIN)
This is the power input to the drain of the high-side power
MOSFET. This pin is connected to the high power
intermediate BUS rail.
Control and Drive Supply Voltage Input (VDRV, VCIN)
VCIN is the bias supply for the gate drive control IC. VDRV is
the bias supply for the gate drivers. It is recommended to
separate these pins through a resistor. This creates a low
pass filtering effect to avoid coupling of high frequency gate
drive noise into the IC.
Bootstrap Circuit (BOOT)
The internal bootstrap diode and an external bootstrap
capacitor form a charge pump that supplies voltage to the
BOOT pin. An integrated bootstrap diode is incorporated so
that only an external capacitor is necessary to complete the
bootstrap circuit. Connect a boot strap capacitor with one
leg tied to BOOT pin and the other tied to PHASE pin.
Shoot-Through Protection and Adaptive Dead Time
The SiC531 and SiC531A have an internal adaptive logic to
avoid shoot through and optimize dead time. The shoot
through protection ensures that both high-side and low-side
MOSFETs are not turned on at the same time. The adaptive
dead time control operates as follows. The high-side and
low-side gate voltages are monitored to prevent the
MOSFET turning on from tuning on until the other
MOSFET’s gate voltage is sufficiently low (< 1 V). Built in
delays also ensure that one power MOSFET is completely
off, before the other can be turned on. This feature helps to
adjust dead time as gate transitions change with respect to
output current and temperature.
Under Voltage Lockout (UVLO)
During the start up cycle, the UVLO disables the gate
drive, holding high-side and low-side MOSFET gates low,
until the supply voltage rail has reached a point at which
the logic circuitry can be safely activated. The SiC531 and
SiC531A also incorporate logic to clamp the gate drive
signals to zero when the UVLO falling edge triggers the
shutdown of the device. As an added precaution, a 20 k
resistor is connected between GH and PHASE to provide a
discharge path for the HS MOSFET.
Switch Node (VSWH and PHASE)
The switch node, VSWH, is the circuit power stage output.
This is the output applied to the power inductor and output
filter to deliver the output for the buck converter. The PHASE
pin is internally connected to the switch node, VSWH. This pin
is to be used exclusively as the return pin for the BOOT
capacitor. A 20 k resistor is connected between GH and
PHASE to provide a discharge path for the HS MOSFET in
the event that VCIN goes to zero while VIN is still applied.
S20-0486-Rev. B, 29-Jun-2020
Document Number: 65999
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FUNCTIONAL BLOCK DIAGRAM
V IN
BOOT
VDRV
UVLO
VCIN
VCIN
20K
Anti-cross
conduction
control
logic
PWM logic
control &
state
machine
PWM
GL
PHASE
Vref = 1 V
VSWH
Vref = 1 V
VDRV
C GND
SW
PGND
PGND
ZCD_EN#
Fig. 3 - SiC531 and SiC531A Functional Block Diagram
DEVICE TRUTH TABLE
ZCD_EN#
PWM
GH
GL
L
L
L
H, IL > 0A
L, IL < 0A
L
H
H
L
L
Tri-state
L
L
H
L
L
H
H
H
H
L
H
Tri-state
L
L
PWM TIMING DIAGRAM
VTH_PWM_R
VTH_TRI_F
VTH_TRI_R
VTH_PWM_F
PWM
t PD_OFF_GL
t TSHO
GL
t PD_ON_GL
t PD_TRI_R
t TSHO
t PD_ON_GH
t PD_OFF_GH
t PD_TRI_R
GH
Fig. 4 - Definition of PWM Logic and Tri-State
S20-0486-Rev. B, 29-Jun-2020
Document Number: 65999
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ELECTRICAL CHARACTERISTICS
Test condition: VIN = 13 V, VDRV = VCIN = 5 V, ZCD_EN# = 5 V, VOUT = 1 V, LOUT = 250 nH, (DCR = 0.32 m), TA = 25 °C
(All power loss and normalized power loss curves show SiC531 and SiC531A losses only unless otherwise stated)
94
40
500 kHz
90
35
30
750 kHz
Output Current, IOUT (A)
Efficiency (%)
86
1 MHz
82
78
74
70
Complete converter efficiency
PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)]
POUT = VOUT x IOUT, measured at output capacitor
66
25
500 kHz
20
1 MHz
15
10
5
0
62
0
5
10
15
20
Output Current, IOUT (A)
25
30
0
15
30
45 60 75 90 105 120 135 150
PCB Temperature, TPCB (°C)
Fig. 8 - Safe Operating Area (VIN = 12.6 V)
Fig. 5 - Efficiency vs. Output Current (VIN = 12.6 V)
6.0
12.0
5.5
10.5
5.0
9.0
Power Loss, PL (W)
Power Loss, PL (W)
IOUT = 25A
4.5
4.0
3.5
7.5
4.5
3.0
3.0
2.5
1.5
2.0
0.0
200
300
400
500
600
700
800
1 MHz
6.0
900 1000 1100
750 kHz
500 kHz
0
5
Switching Frequency, fS (kHz)
Fig. 6 - Power Loss vs. Switching Frequency (VIN = 12.6 V)
25
30
Fig. 9 - Power Loss vs. Output Current (VIN = 12.6 V)
94
94
500 kHz
500 kHz
90
90
750 kHz
86
86
750 kHz
1 MHz
82
Efficiency (%)
Efficiency (%)
10
15
20
Output Current, IOUT (A)
78
74
70
1MHz
78
74
70
Complete converter efficiency
PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)]
POUT = VOUT x IOUT, measured at output
capacitor
66
82
Complete converter efficiency
PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)]
POUT = VOUT x IOUT, measured at output capacitor
66
62
62
0
5
10
15
20
Output Current, IOUT (A)
25
30
Fig. 7 - Efficiency vs. Output Current (VIN = 9 V)
S20-0486-Rev. B, 29-Jun-2020
0
5
10
15
20
25
30
Output Current, IOUT (A)
Fig. 10 - Efficiency vs. Output Current (VIN = 19 V)
Document Number: 65999
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ELECTRICAL CHARACTERISTICS
4.2
0.40
4.0
0.35
BOOT Diode Forward Voltage, VF (V)
Control Logic Supply Voltage, VCIN (V)
Test condition: VIN = 13 V, VDRV = VCIN = 5 V, ZCD_EN# = 5 V, VOUT = 1 V, LOUT = 250 nH, (DCR = 0.32 m), TA = 25 °C
(All power loss and normalized power loss curves show SiC531 and SiC531A losses only unless otherwise stated)
VUVLO_RISING
3.8
3.6
3.4
3.2
3.0
VUVLO_FALLING
2.8
2.6
-60 -40 -20
0
20
40
60
80
IF = 2 mA
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-60 -40 -20
100 120 140
0
60
80
100 120 140
3.2
4.2
VTH_PWM_R
3.6
VTRI_TH_F
3.0
2.4
VTRI
1.8
VTRI_TH_R
1.2
0.6
PWM Threshold Voltage, VPWM (V)
4.8
PWM Threshold Voltage, VPWM (V)
40
Fig. 14 - BOOT Diode Forward Voltage vs. Temperature
Fig. 11 - UVLO Threshold vs. Temperature
2.8
VTH_PWM_R
2.4
VTRI_TH_F
2.0
VTRI
1.6
VTRI_TH_R
1.2
0.8
VTH_PWM_F
0.4
VTH_PWM_F
0.0
0.0
-60 -40 -20
0
20
40
60
80
4.5
100 120 140
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
Temperature (°C)
Control Logic Supply Voltage, VCIN (V)
Fig. 12 - PWM Threshold vs. Temperature (SiC531)
Fig. 15 - PWM Threshold vs. Driver Supply Voltage (SiC531A)
3.4
4.8
3.0
2.6
2.2
VTH_PWM_R
4.2
VTH_PWM_R
VTRI_TH_F
1.8
VTRI
1.4
VTRI_TH_R
1.0
VTH_PWM_F
0.6
0.2
PWM Threshold Voltage, VPWM (V)
PWM Threshold Voltage, VPWM (V)
20
Temperature (°C)
Temperature (°C)
3.6
VTRI_TH_F
3.0
2.4
VTRI
1.8
VTRI_TH_R
1.2
0.6
VTH_PWM_F
0.0
-60 -40 -20
0
20
40
60
80
100 120 140
Temperature (°C)
Fig. 13 - PWM Threshold vs. Temperature (SiC531A)
S20-0486-Rev. B, 29-Jun-2020
4.5
4.6
4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4
Control Logic Supply Voltage, VCIN (V)
5.5
Fig. 16 - PWM Threshold vs. Driver Supply Voltage (SiC531)
Document Number: 65999
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ELECTRICAL CHARACTERISTICS
Test condition: VIN = 13 V, VDRV = VCIN = 5 V, ZCD_EN# = 5 V, VOUT = 1 V, LOUT = 250 nH, (DCR = 0.32 m), TA = 25 °C
(All power loss and normalized power loss curves show SiC531 and SiC531A losses only unless otherwise stated)
2.2
ZCD_EN# Threshold Voltage, VZCD_EN# (V)
ZCD_EN# Threshold Voltage, VZCD_EN# (V)
2.2
2.0
1.8
VIH_ZCD_EN#
1.6
1.4
1.2
1.0
VIL_ZCD_EN#
0.8
0.6
1.8
VIH_ZCD_EN#
1.6
1.4
VIL_ZCD_EN#
1.2
1.0
0.8
0.6
-60 -40 -20
0
20
40
60
80
4.5
100 120 140
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
Temperature (°C)
Control Logic Supply Voltage, VCIN (V)
Fig. 17 - ZCD_EN# Threshold vs. Temperature
Fig. 19 - ZCD_EN# Threshold vs. Driver Supply Voltage
-9.0
430
-9.5
VZCD_EN# = 0 V
-10.0
-10.5
-11.0
-11.5
-12.0
-12.5
-13.0
-60 -40 -20
Driver Supply Current, IVDVR & IVCIN (μA)
ZCD_EN# Pull-Up Current, IZCD_EN# (uA)
2.0
410
VPWM = FLOAT
390
370
350
330
310
290
270
0
20
40
60
80
100 120 140
-60 -40 -20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
Fig. 18 - ZCD_EN# Pull-Up Current vs. Temperature
Fig. 20 - Driver Quiescent Current vs. Temperature
S20-0486-Rev. B, 29-Jun-2020
Document Number: 65999
9
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC531, SiC531A
www.vishay.com
Vishay Siliconix
PCB LAYOUT RECOMMENDATIONS
Step 1: VIN / PGND Planes and Decoupling
Step 3: VCIN / VDRV Input Filter
Cvdrv
VIN Plane
VIN
PGND
VSWH
Cvcin
AGND
PGND
PGND Plane
1. Layout VIN and PGND planes as shown above.
2. Ceramic capacitors should be placed directly between
VIN and PGND, and very close to the device for best
decoupling effect.
3. Different values / packages of ceramic capacitors should
be used to cover entire decoupling spectrum e.g. 1210,
0805, 0603, 0402.
4. Smaller capacitance values, placed closer to the devices,
VIN pin(s), results in better high frequency noise
absorbing.
Step 2: VSWH Plane
1. The VCIN / VDRV input filter ceramic cap should be placed
as close as possible to the IC. It is recommended to
connect two capacitors separately.
2. VCIN capacitor should be placed between pin 2 and pin 3
(AGND of driver IC) to achieve best noise filtering.
3. VDRV capacitor should be placed between pin 20
(PGND of driver IC) and pin 21 to provide maximum
instantaneous driver current for low side MOSFET during
switching cycle.
4. For connecting VCIN to AGND, it is recommended to use
a large plane to reduce parasitic inductance.
Step 4: BOOT Resistor and Capacitor Placement
VSWH
Cboot
Snubber
PGND Plane
1. Connect output inductor to IC with large plane to lower
resistance.
2. VSWH plane also serves as a heat-sink for low-side
MOSFET. Make the plane wide and short to achieve the
best thermal path.
Rboot
1. The components need to be placed as close as possible
to IC, directly between PHASE (pin 5) and BOOT (pin 4).
2. To reduce parasitic inductance, chip size 0402 can be
used.
3. If any snubber network is required, place the
components as shown above and the network can be
placed at bottom.
S20-0486-Rev. B, 29-Jun-2020
Document Number: 65999
10
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC531, SiC531A
www.vishay.com
Vishay Siliconix
Step 5: Signal Routing
Step 7: Ground Connection
AGND
AGND
AGND
VSWH
PGND
PGND
1. Route the PWM and ZCD_EN# signal traces out of the
top left corner next to pin 1.
1. It is recommended to make a single connection between
AGND and PGND which can be made on the top layer.
2. The PWM signal is an important signal, both signal and
return traces should not cross any power nodes on any
layer.
2. It is recommended to make the entire first inner layer
(below top layer) the ground plane and separate them
into AGND and PGND planes.
3. It is best to “shield” these traces from power switching
nodes, e.g. VSWH, with a GND island to improve signal
integrity.
3. These ground planes provide shielding between noise
sources on top layer and signal traces on bottom layer.
4. GL (pin 19) has been connected with GL pad (pin 24)
internally.
Step 6: Adding Thermal Relief Vias
VSWH
AGND
PGND
VIN
PGND Plane
VIN Plane
1. Thermal relief vias can be added on the VIN and AGND
pads to utilize inner layers for high-current and thermal
dissipation.
2. To achieve better thermal performance, additional vias
can be placed on VIN plane and PGND plane.
3. VSWH pad is a noise source, it is not recommended to
place vias on this pad.
4. 8 mil vias for pads and 10 mils vias for planes are the
optimal via sizes. Vias on pad may drain solder during
assembly and cause assembly issues. Consult with the
assembly house for guidelines.
S20-0486-Rev. B, 29-Jun-2020
Document Number: 65999
11
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC531, SiC531A
www.vishay.com
Vishay Siliconix
PRODUCT SUMMARY
Part number
SiC531
SiC531A
Description
30 A power stage, 4.5 VIN to 24 VIN, 5 V PWM
with ZCD mode
30 A power stage, 4.5 VIN to 24 VIN, 3.3 V
PWM with ZCD mode
Input voltage min. (V)
4.5
4.5
Input voltage max. (V)
24
24
Continuous current rating max. (A)
30
30
1500
1500
No
No
-
-
UVLO, THDN
UVLO, THDN
ZCD
ZCD
Switch frequency max. (kHz)
Enable (yes / no)
Monitoring features
Protection
Light load mode
Pulse-width modulation (V)
Package type
Package size (W, L, H) (mm)
5
3.3
PowerPAK MLP4535-22L
PowerPAK MLP4535-22L
4.5 x 3.5 x 0.75
4.5 x 3.5 x 0.75
Status code
2
2
Product type
VRPower (DrMOS)
VRPower (DrMOS)
Applications
Computer, industrial, networking
Computer, industrial, networking
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?65999.
S20-0486-Rev. B, 29-Jun-2020
Document Number: 65999
12
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
MLP 4.5 x 3.5-22L BWL Case Outline
2x
D
A
5 6
Pin 1 dot
by marking
A
0.08 C
K1
0.1 C A
D1-2
D1-1
A1
22 21 20 19
A2
18 17
D2-1
K4
D2-4
17 18
19
20 21
22
2x
12
E2-2
2
3
e
K2
4
5
B
6
7
8
9
11 10 9
10 11
C
DIM.
8
D2-3
MILLIMETERS
E1-2
13
12
K3
E2-3
E1-1
13
5
b
4
E1-5
15
14
E1-3
E2-4
14
E2-1
15
3
E
2
1
16
16
E1-4
0.1 C B 1
7
D2-2
6
L
INCHES
MIN.
NOM.
MAX.
MIN.
NOM.
A (8)
0.70
0.75
0.80
0.027
0.0029
0.031
A1
0.00
-
0.05
0.000
-
0.002
0.30
0.0078
A2
b (4)
0.20 ref.
0.20
0.25
0.008 ref.
0.0098
D
4.50 BSC
0.177 BSC
e
0.50 BSC
0.019 BSC
E
L
3.50 BSC
0.35
0.40
MAX.
0.0110
0.137 BSC
0.45
0.013
0.015
N (3)
22
22
Nd (3)
6
6
Ne (3)
5
5
0.017
D1-1
0.35
0.40
0.45
0.013
0.015
0.017
D1-2
0.15
0.20
0.25
0.005
0.007
0.009
D2-1
1.02
1.07
1.12
0.040
0.042
0.044
D2-2
1.02
1.07
1.12
0.040
0.042
0.044
D2-3
1.47
1.52
1.57
0.057
0.059
0.061
D2-4
0.25
0.30
0.35
0.009
0.011
0.013
E1-1
1.095
1.145
1.195
0.043
0.045
0.047
E1-2
2.67
2.72
2.77
0.105
0.107
0.109
E1-3
0.35
0.40
0.45
0.013
0.015
0.017
E1-4
1.85
1.90
1.95
0.072
0.074
0.076
E1-5
0.095
0.145
0.195
0.0037
0.0057
0.0076
E2-1
3.05
3.10
3.15
0.120
0.122
0.124
E2-2
1.065
1.115
1.165
0.0419
0.0438
0.0458
E2-3
0.695
0.745
0.795
0.027
0.029
0.031
E2-4
0.40
0.45
0.50
0.015
0.017
0.019
K1
0.40 BSC
0.015 BSC
K2
0.07 BSC
0.002 BSC
K3
0.05 BSC
0.001 BSC
K4
0.40 BSC
0.015 BSC
Document Number: 67234
1
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Revision: 20-Oct-14
Package Information
www.vishay.com
Vishay Siliconix
Notes
1. Use millimeters as the primary measurement
2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994
3. N is the number of terminals,
Nd is the number of terminals in X-direction and
Ne is the number of terminals in Y-direction.
4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
6. Exact shape and size of this feature is optional
7. Package warpage max. 0.08 mm
8. Applied only for terminals
T14-0626-Rev. A, 20-Oct-14
DWG: 6028
Document Number: 67234
2
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Revision: 20-Oct-14
PAD Pattern
www.vishay.com
Vishay Siliconix
Recommended Land Pattern PowerPAK® MLP4535-22L
Land pattern
0.74
0.3
0.75
1.2
2
0.29
0.25
1.16
4
0.31
0.8
0.3
16
0.14
15
14
1.61
13
2.05
0.37
3
5
12
22
10
11
21 20 19
18
16
2
15
3
14
4
13
5
12
Revision: 05-Nov-14
7
8
9
10
0.75
7
8
0.5 x 2
=1
9
1
10
0.5 x 2
=1
11
0.75
17
1
6
6
3
9
(D2-3)
1.52
0.
8
0.1
7
(D2-2)
1.07
0.37
0.3
0.3
6
(L)
0.4
0.59
0.75
12
0.4 0.3
0.3
17 0.45
0.9
13
3.5
14
0.36
18
0.75
0.75
0.3
(E2-3)
0.75
(e)
0.5
5
15
0.5
21 20 19
1
0.5 x 4 = 2
3.05
0.29
0.21
(K2)
0.07
16
(b)
0.25
(E2-1)
3.1
3.5
(D1-5)
0.14
3
4
(E1-1)
1.15
(K3)
0.05
(E1-4)
1.9
(E1-2)
2.72
(E2-2)
1.11
1
2
0.45 22
18 17
(E2-4)
0.45
21 20 19
(E1-3)
0.4
22
1
0.5 x 4 = 2
4.5
0.75 0.5 x 3 = 1.5
0.3
0.55 0.5
(D1-2)
0.2
(D1-1)
0.4
0.29
4.5
(K4)
(D2-4)
0.3
0.4
(D2-1) (K1)
1.07 0.4
0.75
Package outline top view, transparent
(not bottom view)
All dimensions in millimeters
11
Document Number: 66914
1
For technical questions, contact: powerictechsupport@vishay.com
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Legal Disclaimer Notice
www.vishay.com
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay's knowledge of typical
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements
about the suitability of products for a particular application. It is the customer's responsibility to validate that a particular product
with the properties described in the product specification is suitable for use in a particular application. Parameters provided in
datasheets and / or specifications may vary in different applications and performance may vary over time. All operating
parameters, including typical parameters, must be validated for each customer application by the customer's technical experts.
Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited
to the warranty expressed therein.
Hyperlinks included in this datasheet may direct users to third-party websites. These links are provided as a convenience and
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any of the products, services or opinions of the corporation, organization or individual associated with the third-party website.
Vishay disclaims any and all liability and bears no responsibility for the accuracy, legality or content of the third-party website
or for that of subsequent links.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please
contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.
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any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
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Revision: 01-Jan-2022
1
Document Number: 91000
