SIC639ACD-T1-GE3

SiC639, SiC639A www.vishay.com Vishay Siliconix 50 A VRPower® Integrated Power Stage DESCRIPTION FEATURES The SiC639 are integrated power stage solutions optimized for synchronous buck applications to offer high current, high efficiency, and high power density performance. Packaged in Vishay’s proprietary 5 mm x 5 mm MLP package, SiC639 enables voltage regulator designs to deliver up to 50 A continuous current per phase. • Thermally enhanced PowerPAK® MLP55-31L package • Vishay’s Gen IV MOSFET technology and a low side MOSFET with integrated Schottky diode • Delivers up to 50 A continuous current • High efficiency performance The internal power MOSFETs utilizes Vishay’s state-of-the-art Gen IV TrenchFET® technology that delivers industry benchmark performance to significantly reduce switching and conduction losses. • High frequency operation up to 1.5 MHz • Power MOSFETs optimized for 19 V input stage • 3.3 V, 5 V PWM logic with tri-state and hold-off • Zero current detect control for light load efficiency improvement The SiC639 incorporate an advanced MOSFET gate driver IC that features high current driving capability, adaptive dead-time control, an integrated bootstrap Schottky diode, a thermal warning (THWn) that alerts the system of excessive junction temperature, and zero current detection to improve light load efficiency. The drivers are also compatible with a wide range of PWM controllers and supports tri-state PWM, 3.3 V, 5 V PWM logic. • Low PWM propagation delay (< 20 ns) • Faster disable • Thermal monitor flag • Under voltage lockout for VCIN • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 APPLICATIONS • Multi-phase VRDs for computing, graphics card and memory • Intel IMVP-8/9 VRPower delivery - VCORE, VGRAPHICS, VSYSTEM platforms AGENT Skylake, Kabylake - VCCGI for Apollo Lake platforms • Up to 24 V rail input DC/DC VR modules  TYPICAL APPLICATION DIAGRAM 5V Input V IN NC VDRV BOOT PHASE VCIN ZCD_EN# PWM controller DSBL# PWM SW Output Gate driver THWn PGND GL C GND Fig. 1 - SiC639 and SiC639A Typical Application Diagram S20-0485-Rev. B, 29-Jun-2020 Document Number: 76585 1 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC639, SiC639A www.vishay.com Vishay Siliconix GL CGND CGND 4 BOOT 5 PGND N.C. 6 VIN VSWH 22 21 VSWH VSWH 21 20 VSWH VSWH 20 VSWH 19 18 VSWH VSWH 18 17 VSWH VSWH 17 16 VSWH VSWH 16 THWn VDRV PGND SW GL DSBL# 3 VCIN 4 CGND 35 PGND 5 BOOT 6 N.C. 34 VIN 7 PHASE 8 VIN Top view VIN PGND PGND PGND 11 10 PGND 15 14 13 12 PGND 12 13 14 15 VIN VIN 10 11 VIN 19 VSWH 2 ZCD_EN# 32 CGND VIN 9 22 VSWH 1 PWM GL PGND VIN 8 VSWH 23 PGND PHASE 7 23 VSWH PGND VCIN 3 24 25 26 27 28 29 30 31 9 VIN PWM 1 SW SW SW GL SW PGND VDRV THWn DSBL# 33 GL 31 30 29 28 27 26 25 24 ZCD_EN# 2 SW PINOUT CONFIGURATION Bottom view Fig. 2 - SiC639 Pin Configuration PIN CONFIGURATION PIN NUMBER NAME 1 PWM 2 ZCD_EN# FUNCTION PWM input logic The ZCD_EN# pin enables or disables zero cross detection on inductor current when it detects PWM = mid. When ZCD_EN# is LOW, GL stays on until ZCD detected when it detects PWM = mid. When ZCD_EN# is HIGH, GL turns off when it detects PWM = mid.or PWM = 1 3 VCIN 4, 32 CGND Signal ground 5 BOOT High side driver bootstrap voltage 6 N.C. 7 PHASE 8 to 11, 34 VIN Supply voltage for internal logic circuitry Not connected internally, can be left floating or connected to ground Return path of high side gate driver Power stage input voltage. Drain of high side MOSFET 12 to 15, 28, 35 PGND Power ground 16 to 26 VSWH Phase node of the power stage 27, 33 GL 29 VDRV Low side MOSFET gate signal Supply voltage for internal gate driver 30 THWn Thermal warning open drain output 31 DSBL# Disable pin. Active low ORDERING INFORMATION PART NUMBER PACKAGE MARKING CODE OPTION SiC639CD-T1-GE3 PowerPAK MLP55-31L SiC639 5 V PWM optimized SiC639ACD-T1-GE3 PowerPAK MLP55-31L SiC639A 3.3 V PWM optimized SiC639DB S20-0485-Rev. B, 29-Jun-2020 Reference board Document Number: 76585 2 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC639, SiC639A www.vishay.com Vishay Siliconix PART MARKING INFORMATION = pin 1 indicator P/N = P/N part number code = Siliconix logo = ESD symbol F = assembly factory code Y = year code WW = week code LL = lot code LL FYWW ABSOLUTE MAXIMUM RATINGS ELECTRICAL PARAMETER CONDITIONS LIMIT VIN -0.3 to +30 Control logic supply voltage VCIN -0.3 to +7 Drive supply voltage VDRV Input voltage Switch node (DC voltage) BOOT voltage (DC voltage) BOOT voltage (AC -0.3 to +7 -0.3 to +30 VSWH Switch node (AC voltage) (1) -7 to +35 BOOT to PHASE (DC voltage) 40 -0.3 to +7 VBOOT-PHASE BOOT to PHASE (AC voltage) (3) -0.3 to +8 All logic inputs and outputs (PWM, DSBL#, and THWn) -0.3 to VCIN + 0.3 Max. operating junction temperature TJ 150 Ambient temperature TA -40 to +125 Storage temperature Tstg -65 to +150 Human body model, JESD22-A114 3000 Charged device model, JESD22-C101 1000 Electrostatic discharge protection V 35 VBOOT voltage) (2) UNIT °C V Notes • Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability (1) The specification values indicated “AC” is V SWH to PGND -8 V (< 20 ns, 10 μJ), min. and 35 V (< 50 ns), max. (2) The specification value indicates “AC voltage” is V BOOT to PGND, 40 V (< 50 ns) max. (3) The specification value indicates “AC voltage” is V BOOT to VPHASE, 8 V (< 20 ns) max. RECOMMENDED OPERATING RANGE ELECTRICAL PARAMETER MINIMUM TYPICAL MAXIMUM Input voltage (VIN) 2.7 - 24 Drive supply voltage (VDRV) 4.5 5 5.5 Control logic supply voltage (VCIN) 4.5 5 5.5 5.5 BOOT to PHASE (VBOOT-PHASE, DC voltage) 4 4.5 Thermal resistance from junction to ambient - 10.6 - Thermal resistance from junction to case - 1.6 - S20-0485-Rev. B, 29-Jun-2020 UNIT V °C/W Document Number: 76585 3 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC639, SiC639A www.vishay.com Vishay Siliconix ELECTRICAL SPECIFICATIONS (DSBL# = ZCD_EN# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 °C) PARAMETER SYMBOL TEST CONDITION LIMITS MIN. TYP. MAX. VDSBL# = 0 V, no switching, VPWM = FLOAT - 5 - VDSBL# = 5 V, no switching, VPWM = FLOAT - 300 - VDSBL# = 5 V, fS = 300 kHz, D = 0.1 - 350 - fS = 300 kHz, D = 0.1 - 9 14 fS = 1 MHz, D = 0.1 - 30 - VDSBL# = 0 V, no switching - 15 - VDSBL# = 5 V, no switching - 55 - UNIT POWER SUPPLY Control logic supply current Drive supply current IVCIN IVDRV μA mA μA BOOTSTRAP SUPPLY Bootstrap diode forward voltage VF IF = 2 mA 0.4 V PWM CONTROL INPUT (SiC639) Rising threshold VTH_PWM_R - - Falling threshold VTH_PWM_F 0.72 - - Tri-state voltage VTRI_FLOAT - 2.3 - Tri-state window 3 VPWM = FLOAT 4.2 VTRI_WINDOW 1.38 - Tri-state rising threshold hysteresis VHYS_TRI_R - 225 - Tri-state falling threshold hysteresis VHYS_TRI_F - 325 - VPWM = 5 V, DSBL# = high - - 350 PWM input current IPWM VPWM = 5 V, DSBL# = low - - 1 VPWM = 0 V, DSBL# = high - - -350 VPWM = 0 V, DSBL# = low - - -1 2.7 V mV μA PWM CONTROL INPUT (SiC639A) Rising threshold VTH_PWM_R - - Falling threshold VTH_PWM_F 0.72 - - Tri-state voltage VTRI_FLOT - 1.8 - Tri-state window VTRI_WINDOW 1.38 - 1.95 Tri-state rising threshold hysteresis VHYS_TRI_R - 250 - Tri-state falling threshold hysteresis VHYS_TRI_F - 300 - VPWM = 3.3 V, DSBL# = high - - 225 VPWM = 3.3 V, DSBL# = low - - 1 VPWM = 0 V, DSBL# = high - - -225 VPWM = 0 V, DSBL# = low - - -1 30 - PWM input current IPWM VPWM = FLOAT V mV μA TIMING SPECIFICATIONS Tri-state to GH/GL rising propagation delay tPD_TRI_R - Tri-state GH hold-off time tTSHO_GH - 35 Tri-state GL hold-off time tTSHO_GL - 130 - GH - turn off propagation delay tPD_OFF_GH - 15 - GH - turn on propagation delay (dead time rising) tPD_ON_GH - 10 - GL - turn off propagation delay tPD_OFF_GL - 13 - GL - turn on propagation delay (dead time falling) tPD_ON_GL - 10 - - 15 - 30 - - DSBL# Lo to GH/GL falling propagation delay tPD_DSBL#_F PWM minimum on-time tPWM_ON_MIN S20-0485-Rev. B, 29-Jun-2020 No load, see Fig. 4 Fig. 5 ns Document Number: 76585 4 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC639, SiC639A www.vishay.com Vishay Siliconix ELECTRICAL SPECIFICATIONS (DSBL# = ZCD_EN# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 °C) PARAMETER SYMBOL TEST CONDITION VIH_DSBL# VIL_DSBL# VIH_ZCD_EN# VIL_ZCD_EN# VUVLO LIMITS MIN. TYP. MAX. Input logic high Input logic low Input logic high Input logic low 2 2 - - 0.8 0.8 VCIN rising, on threshold VCIN falling, off threshold 2.7 - 3.7 3.1 575 160 135 25 0.02 4.1 - UNIT DSBL# ZCD_EN# INPUT DSBL# logic input voltage ZCD_EN# logic input voltage V PROTECTION Under voltage lockout Under voltage lockout hysteresis THWn flag set (2) THWn flag clear (2) THWn flag hysteresis (2) THWn output low VUVLO_HYST TTHWn_SET TTHWn_CLEAR TTHWn_HYST VOL_THWn ITHWn = 2 mA V mV °C V Notes (1) Typical limits are established by characterization and are not production tested (2) Guaranteed by design DETAILED OPERATIONAL DESCRIPTION PWM Input with Tri-State Function Diode Emulation Mode (ZCD_EN#) The PWM input receives the PWM control signal from the VR controller IC. The PWM input is designed to be compatible with standard controllers using two state logic (H and L) and advanced controllers that incorporate tri-state logic (H, L and tri-state) on the PWM output. For two state logic, the PWM input operates as follows. When PWM is driven above VPWM_TH_R the low side is turned off and the high side is turned on. When PWM input is driven below VPWM_TH_F the high side is turned off and the low side is turned on. For tri-state logic, the PWM input operates as previously stated for driving the MOSFETs when PWM is logic high and logic low. However, there is a third state that is entered as the PWM output of tri-state compatible controller enters its high impedance state during shut-down. The high impedance state of the controller’s PWM output allows the SiC639 and SiC639A to pull the PWM input into the tri-state region (see definition of PWM logic and tri-state, Fig. 4). If the PWM input stays in this region for the tri-state hold-off period, tTSHO, both high side and low side MOSFETs are turned off. The function allows the VR phase to be disabled without negative output voltage swing caused by inductor ringing and saves a Schottky diode clamp. The PWM and tri-state regions are separated by hysteresis to prevent false triggering. When ZCD_EN# pin is driven below VIL_ZCD_EN# diode emulation mode is enabled. If the PWM input is wi thin the tri-state window for longer than the tri-state hold off time, then the low side MOSFET is under control of the ZCD (zero crossing detect) comparator. In this mode, the LS MOSFET is turned off if the inductor current is < or = 0. Light load efficiency is improved by avoiding discharge of output capacitors. If ZCD_EN# is high, diode emulation mode is disabled. In this mode if PWM enters tri-state, the device will go into tri-state mode after tri-state delay and both the high side and low side MOSFETs will be turned off. Disable (DSBL#) In the low state, the DSBL# pin shuts down the driver IC and disables both high-side and low side MOSFETs. WhenDSBL# is low, the PWM resistor divider is also disconnected. In this state, standby current is minimized. If DSBL# is left unconnected, an internal pull-down resistor will pull the pin to CGND and shut down the IC.  S20-0485-Rev. B, 29-Jun-2020 Thermal Shutdown Warning (THWn) The THWn pin is an open drain signal that flags the presence of excessive junction temperature. Connect with a maximum of 20 k, to VCIN. An internal temperature sensor detects the junction temperature. The temperature threshold is 160 °C. When this junction temperature is exceeded the THWn flag is set. When the junction temperature drops below 135 °C the device will clear the THWn signal. The SiC639 and SiC639A do not stop operation when the flag is set. The decision to shutdown must be made by an external thermal control function. Voltage Input (VIN) This is the power input to the drain of the high side power MOSFET. This pin is connected to the high power intermediate BUS rail.  Document Number: 76585 5 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC639, SiC639A www.vishay.com Vishay Siliconix Switch Node (VSWH and PHASE) Bootstrap Circuit (BOOT) The switch node, VSWH, is the circuit power stage output. This is the output applied to the power inductor and output filter to deliver the output for the buck converter. The PHASE pin is internally connected to the switch node VSWH. This pin is to be used exclusively as the return pin for the BOOT capacitor. A 20 k resistor is connected between GH (the high side gate) and PHASE to provide a discharge path for the HS MOSFET in the event that VCIN goes to zero while VIN is still applied. The internal bootstrap diode and an external bootstrap capacitor form a charge pump that supplies voltage to the BOOT pin. An integrated bootstrap diode is incorporated so that only an external capacitor is necessary to complete the bootstrap circuit. Connect a boot strap capacitor with one leg tied to BOOT pin and the other tied to PHASE pin. Shoot-Through Protection and Adaptive Dead Time The SiC639 and SiC639A have an internal adaptive logic to avoid shoot through and optimize dead time. The shoot through protection ensures that both high side and low side MOSFETs are not turned on at the same time. The adaptive dead time control operates as follows. The high side and low side gate voltages are monitored to prevent the MOSFET turning on from tuning on until the other MOSFET’s gate voltage is sufficiently low (< 1 V). Built in delays also ensure that one power MOSFET is completely off, before the other can be turned on. This feature helps to adjust dead time as gate transitions change with respect to output current and temperature. Ground Connections (CGND and PGND) PGND (power ground) should be externally connected to CGND (signal ground). The layout of the printed circuit board should be such that the inductance separating CGND and PGND is minimized. Transient differences due to inductance effects between these two pins should not exceed 0.5 V Control and Drive Supply Voltage Input (VDRV, VCIN) VCIN is the bias supply for the gate drive control IC. VDRV is the bias supply for the gate drivers. It is recommended to separate these pins through a resistor. This creates a low pass filtering effect to avoid coupling of high frequency gate drive noise into the IC. Under Voltage Lockout (UVLO) During the start up cycle, the UVLO disables the gate drive holding high side and low side MOSFET gates low until the supply voltage rail has reached a point at which the logic circuitry can be safely activated. The SiC639, SiC639A also incorporates logic to clamp the gate drive signals to zero when the UVLO falling edge triggers the shutdown of the device. As an added precaution, a 20 k resistor is connected between GH (the high side gate) and PHASE to provide a discharge path for the HS MOSFET.  FUNCTIONAL BLOCK DIAGRAM THWn BOOT V IN VDRV Thermal monitor & warning VCIN UVLO DISB# VCIN DISB PWM logic control & state machine Anti-cross conduction control logic + GL 20K Vref = 1 V PHASE SW + Vref = 1 V PWM VDRV DISB CGND SW PGND ZCD_EN# GL PGND Fig. 3 - SiC639 Functional Block Diagram S20-0485-Rev. B, 29-Jun-2020 Document Number: 76585 6 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC639, SiC639A www.vishay.com Vishay Siliconix DEVICE TRUTH TABLE DSBL# ZCD_EN# PWM GH GL H L H H L H L H to mid L H, IL > 0 A L, IL < 0 A H L L to mid L L H L L L H L X X L L H H L L H H H H H L H H mid L L   PWM TIMING DIAGRAM Fig. 4 - Timing Diagram  DSBL# PROPAGATION DELAY PWM PWM Disable DSBL# DSBL# GH GH GL GL t t DSBL#Low to GH Falling Propagation Delay DSBL# Low to GL Falling Propagation Delay Fig. 5 - DSBL# Falling Propagation Delay S20-0485-Rev. B, 29-Jun-2020 Document Number: 76585 7 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC639, SiC639A www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS Test condition: VIN = 13 V, DSBL# = VDRV = VCIN = 5 V, ZCD_EN# = 5 V, VOUT = 1 V, LOUT = 250 nH (DCR = 0.32 m), TA = 25 °C, natural convection cooling (All power loss and normalized power loss curves show SiC639 and SiC639A losses only unless otherwise stated) 94 55 90 50 45 500 kHz 750 kHz 82 500 kHz Output Current, IOUT (A) Efficiency (%) 86 1 MHz 78 74 70 40 1 MHz 35 30 25 Complete converter efficiency PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)] POUT = VOUT x IOUT, measured at output capacitor 66 20 15 62 0 5 10 15 20 25 30 35 Output Current, IOUT (A) 40 45 0 50 15 16.0 5.0 IOUT = 25A 4.5 14.0 12.0 4.0 Power Loss, PL (W) Power Loss, PL (W) 45 60 75 90 105 120 135 150 PCB Temperature, TPCB (°C) Fig. 9 - Safe Operating Area Fig. 6 - Efficiency vs. Output Current (VIN = 12.6 V) 3.5 3.0 2.5 10.0 1 MHz 8.0 750 kHz 6.0 2.0 4.0 1.5 2.0 500 kHz 0.0 1.0 200 300 0 400 500 600 700 800 900 1000 1100 Switching Frequency, fs (KHz) Fig. 7 - Power Loss vs. Switching Frequency (VIN = 12.6 V) 5 10 15 20 25 30 35 Output Current, IOUT (A) 40 45 Fig. 10 - Power Loss vs. Output Current (VIN = 12.6 V) 94 98 500 kHz 500 kHz 94 90 90 Efficiency (%) 86 86 Efficiency (%) 30 750 kHz 82 1 MHz 78 82 750 kHz 78 1 MHz 74 74 70 70 Complete converter efficiency PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)] POUT = VOUT x IOUT, measured at output capacitor 66 Complete converter efficiency PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)] POUT = VOUT x IOUT, measured at output capacitor 66 62 62 0 5 10 15 20 25 30 35 Output Current, IOUT (A) 40 45 50 Fig. 8 - Efficiency vs. Output Current (VIN = 9 V) S20-0485-Rev. B, 29-Jun-2020 0 5 10 15 20 25 30 35 Output Current, IOUT (A) 40 45 50 Fig. 11 - Efficiency vs. Output Current (VIN = 19 V) Document Number: 76585 8 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC639, SiC639A www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS 4.2 0.40 4.0 0.35 BOOT Diode Forward Voltage, VF (V) Control Logic Supply Voltage, VCIN (V) Test condition: VIN = 13 V, DSBL# = VDRV = VCIN = 5 V, ZCD_EN# = 5 V, VOUT = 1 V, LOUT = 250 nH (DCR = 0.32 m), TA = 25 °C, natural convection cooling (All power loss and normalized power loss curves show SiC639 and SiC639A losses only unless otherwise stated) VUVLO_RISING 3.8 3.6 3.4 3.2 3.0 VUVLO_FALLING 2.8 -60 -40 -20 0 20 40 60 80 Temperature (°C) VTH_PWM_R 2.50 VTRI_TH_F 2.15 1.80 VTRI VTRI_TH_R 1.10 PWM Threshold Voltage, VPWM (V) Control Logic Supply Voltage, VPWM (V) 0.05 0 20 40 60 80 Temperature (°C) 100 120 140 Fig. 15 - Boot Diode Forward Voltage vs. Temperature 2.85 VTH_PWM_R 2.50 VTRI_TH_F 2.15 1.80 VTRI 1.45 VTRI_TH_R 1.10 0.75 VTH_PWM_F VTH_PWM_F 0.40 0.40 -60 -40 -20 0 20 40 60 80 Temperature (°C) 4.5 100 120 140 Fig. 13 - PWM Threshold vs. Temperature (SiC639A) 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 Driver Supply Voltage, VCIN (V) 5.4 5.5 Fig. 16 - PWM Threshold vs. Driver Supply Voltage (SiC639A) 5.00 5.0 4.50 VTH_PWM_R 4.0 3.5 VTRI_TH_F 3.0 VTRI 2.5 2.0 VTRI_TH_R 1.0 VTH_PWM_F PWM Threshold Voltage, VPWM (V) 4.5 Control Logic Supply Voltage, VPWM (V) 0.10 3.20 2.85 0.5 0.15 -60 -40 -20 3.20 1.5 0.20 100 120 140 Fig. 12 - UVLO Threshold vs. Temperature 0.75 0.25 0.00 2.6 1.45 IF = 2 mA 0.30 VTH_PWM_R 4.00 3.50 VTRI_TH_F 3.00 VTRI 2.50 2.00 1.50 VTRI_TH_R 1.00 VTH_PWM_F 0.50 0 0.0 -60 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 140 Fig. 14 - PWM Threshold vs. Temperature (SiC639) S20-0485-Rev. B, 29-Jun-2020 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 Driver Supply Voltage, VCIN (V) 5.4 5.5 Fig. 17 - PWM Threshold vs. Driver Supply Voltage (SiC639) Document Number: 76585 9 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC639, SiC639A www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS Test condition: VIN = 13 V, DSBL# = VDRV = VCIN = 5 V, ZCD_EN# = 5 V, VOUT = 1 V, LOUT = 250 nH (DCR = 0.32 m), TA = 25 °C, natural convection cooling (All power loss and normalized power loss curves show SiC639 and SiC639A losses only unless otherwise stated) 2.20 VIH_DSBL# 1.6 1.5 1.4 1.3 1.2 1.1 VIL_DSBL# 1.0 0.9 -60 -40 -20 0 20 40 60 80 Temperature (°C) 2.00 ZCD_EN# Threshold Voltage, VZCD_EN# (V) DSBL# Threshold Voltage, VDSBL# (V) 1.7 1.80 1.40 1.20 0.80 0.60 4.5 100 120 140 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 Driver Supply Voltage, VCIN (V) 5.4 5.5 Fig. 21 - ZCD_EN# Threshold vs. Driver Supply Voltage 1.7 8 VDSBL# = 0 V VIH_DSBL# 1.6 Driver Supply Current, IVDVR & IVCIN (V) DSBL# Threshold Voltage, VDSBL# (V) VIL_ZCD_EN#_F 1.00 Fig. 18 - DSBL# Threshold vs. Temperature 1.5 1.4 1.3 1.2 1.1 VIL_DSBL# 1.0 0.9 7 6 5 4 3 2 1 0 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 Driver Supply Voltage, VCIN (V) 5.4 5.5 -60 -40 -20 Fig. 19 - DSBL# vs. Driver Input Voltage 0 20 40 60 80 Temperature (°C) 100 120 140 Fig. 22 - Driver Shutdown Current vs. Temperature 10.8 340 Driver Supply Current, IVDVR & IVCIN (V) DSBL# Pull-Down Current, IDSBL# (uA) VIH_ZCD_EN#_R 1.60 10.7 10.6 10.5 10.4 10.3 10.2 10.1 10.0 330 VPWM = FLOAT 320 310 300 290 280 270 260 -60 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 140 Fig. 20 - DSBL# Pull-Down Current vs. Temperature S20-0485-Rev. B, 29-Jun-2020 -60 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 140 Fig. 23 - Driver Supply Current vs. Temperature Document Number: 76585 10 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC639, SiC639A www.vishay.com Vishay Siliconix PCB LAYOUT RECOMMENDATIONS Step 1: VIN/GND Planes and Decoupling Step 3: VCIN/VDRV Input Filter VSWH P G N D CVDRV PGND CVCIN VIN CGND VIN plane PGND plane 1. Layout VIN and PGND planes as shown above 2. Ceramic capacitors should be placed right between VIN and PGND, and very close to the device for best decoupling effect 3. Difference values / packages of ceramic capacitors should be used to cover entire decoupling spectrum e.g. 1210, 0805, 0603, and 0402 4. Smaller capacitance value, closer to device VIN pin(s) - better high frequency noise absorbing 1. The VCIN/VDRV input filter ceramic cap should be placed very close to IC. It is recommended to connect two caps separately 2. CVCIN cap should be placed between pin 3 and pin 4 (CGND of driver IC) to achieve best noise filtering 3. CVDRV cap should be placed between pin 28 (PGND of driver IC) and pin 29 to provide maximum instantaneous driver current for low side MOSFET during switching cycle 4. For connecting CVCIN analog ground, it is recommended to use large plane to reduce parasitic inductance Step 2: VSWH Plane Step 4: BOOT Resistor and Capacitor Placement VSWH VSWH Snubber CBOOT RBOOT PGNDPlane plane PGND 1. Connect output inductor to DrMOS with large plane to lower the resistance 2. If any snubber network is required, place the components as shown above and the network can be placed at bottom S20-0485-Rev. B, 29-Jun-2020 1. These components need to be placed very close to IC, right between PHASE (pin 7) and BOOT (pin 5) 2. To reduce parasitic inductance, chip size 0402 can be used Document Number: 76585 11 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC639, SiC639A www.vishay.com Vishay Siliconix 1. Thermal relief vias can be added on the VIN and PGND pads to utilize inner layers for high current and thermal dissipation Step 5: Signal Routing CGND 2. To achieve better thermal performance, additional vias can be put on VIN plane and PGND plane. CGND 3. VSWH pad is a noise source and not recommended to put vias on this plane 4. 8 mil drill for pads and 10 mils drill for plane can be the optional via size. Vias on pad may drain solder during assembly and cause assembly issue. Please consult with the assembly house for guideline  Step 7: Ground Connection CGND PGND VSWH 1. Route the PWM / ZCD_EN# / DSBL# / THWn signal traces out of the top left corner next DrMOS pin 1 PGND 2. PWM signal is very important signal, both signal and return traces need to pay special attention of not letting this trace cross any power nodes on any layer 3. It is best to “shield” traces form power switching nodes, e.g. VSWH, to improve signal integrity 4. GL (pin 27) has been connected with GL pad internally and does not need to connect externally 1. It is recommended to make single connection between CGND and PGND and this connection can be done on top layer  Step 6: Adding Thermal Relief Vias 2. It is recommended to make the whole inner 1 layer (next to top layer) ground plane and separate them into CGND and PGND plane VSWH 3. These ground planes provide shielding between noise source on top layer and signal trace on bottom layer CGND PGND VIN PGND plane VIN plane      S20-0485-Rev. B, 29-Jun-2020 Document Number: 76585 12 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC639, SiC639A www.vishay.com Vishay Siliconix Multi-Phases VRPower PCB Layout Following is an example for 6 phase layout. As can be seen, all the VRPower stages are lined in X-direction compactly with decoupling caps next to them. The inductors are placed as close as possible to the SiC639 and SiC639A to minimize the PCB copper loss. Vias are applied on all PADs (VIN, PGND, CGND) of the SiC639 and SiC639A to ensure that both electrical and thermal performance are excellent. Large copper planes are used for all the high current loops, such as VIN, VSWH, VOUT and PGND. These copper planes are duplicated in other layers to minimize the inductance and resistance. All the control signals are routed from the SiC639 and SiC639A to a controller placed to the north of the power stage through inner layers to avoid the overlap of high current loops. This achieves a compact design with the output from the inductors feeding a load located to the south of the design as shown in the figure. VIN PGND VOUT Fig. 24 - Multi-Phase VRPower Layout Top View VIN PGND VOUT Fig. 25 - Multi-Phase VRPower Layout Bottom View S20-0485-Rev. B, 29-Jun-2020 Document Number: 76585 13 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC639, SiC639A www.vishay.com Vishay Siliconix PRODUCT SUMMARY Part number SiC639 SiC639A Description 50 A power stage, 2.7 VIN to 24 VIN, 5 V PWM with ZCD mode 50 A power stage, 2.7 VIN to 24 VIN, 3.3 V PWM with ZCD mode Input voltage min. (V) 2.7 2.7 Input voltage max. (V) 24 24 Continuous current rating max. (A) 50 50 Switch frequency max. (kHz) 1500 1500 Enable (yes / no) Yes Yes Monitoring features Protection Light load mode Pulse-width modulation (V) Package type Package size (W, L, H) (mm) - - UVLO, THDN UVLO, THDN ZCD ZCD 5 3.3 PowerPAK MLP55-31L PowerPAK MLP55-31L 5.0 x 5.0 x 0.75 5.0 x 5.0 x 0.75 Status code 2 2 Product type VRPower (DrMOS) VRPower (DrMOS) Applications Computer, industrial, networking Computer, industrial, networking Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see www.vishay.com/ppg?76585. S20-0485-Rev. B, 29-Jun-2020 Document Number: 76585 14 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix PowerPAK® MLP55-31L Case Outline K12 K1 D2- 1 E2- 2 L 15 C 9 K2 D2- 3 D2- 2 e2 Top view DIM. e1/3x 8 16 b1 31x K6 K10 K3 E2- 3 0.10 M C A B 0.05 M C 1 e/25x 3 E 31 F3 b 31x B K8 K4 D2-4 23 MLP55-31L (5 mm x 5 mm) K13 8x K5 E2- 1 24 E2-4 A2 0.10 C B F2 F1 D 2x D2-5 A1 0.10 C A A K7 A 2x K11 0.08 C 0.10 C 5 6 Pin 1 dot by marking K9 e3 Bottom view Side view MILLIMETERS INCHES MIN. NOM. MAX. MIN. NOM. MAX. A 0.70 0.75 0.80 0.027 0.029 0.031 A1 0.00 - 0.05 0.000 - 0.002 A2 0.20 ref. 0.008 ref. b 0.20 0.25 0.30 0.078 0.098 0.011 b1 0.15 0.20 0.25 0.006 0.008 0.010 D 4.90 5.00 5.10 0.193 0.196 0.200 e 0.50 BSC 0.019 BSC e1 3.50 BSC 0.138 BSC e2 1.50 BSC 0.060 BSC e3 1.00 BSC 0.040 BSC E 4.90 5.00 5.10 0.193 0.196 0.200 L 0.35 0.40 0.45 0.013 0.015 0.017 D2-1 0.98 1.03 1.08 0.039 0.041 0.043 D2-2 0.98 1.03 1.08 0.039 0.041 0.043 D2-3 1.87 1.92 1.97 0.074 0.076 0.078 D2-4 0.30 BSC 0.012 BSC D2-5 1.05 1.10 1.15 0.041 0.043 0.045 E2-1 1.27 1.32 1.37 0.050 0.052 0.054 E2-2 1.93 1.98 2.03 0.076 0.078 0.080 E2-3 3.75 3.80 3.85 0.148 0.150 0.152 E2-4 F1 0.45 BSC 0.15 0.20 0.018 BSC 0.25 0.006 0.008 F2 0.20 ref. 0.008 ref. F3 0.15 ref. 0.006 ref. Revision: 21-Aug-17 0.010 Document Number: 64909 1 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com DIM. Vishay Siliconix MILLIMETERS MIN. NOM. INCHES MAX. MIN. NOM. K1 0.67 BSC 0.026 BSC K2 0.22 BSC 0.008 BSC K3 1.25 BSC 0.049 BSC K4 0.10 BSC 0.004 BSC K5 0.38 BSC 0.015 BSC K6 0.12 BSC 0.005 BSC K7 0.40 BSC 0.016 BSC K8 0.40 BSC 0.016 BSC K9 0.40 BSC 0.016 BSC K10 0.85 BSC 0.033 BSC K11 0.40 BSC 0.016 BSC K12 0.40 BSC 0.016 BSC K13 0.75 BSC 0.030 BSC MAX. ECN: T17-0423-Rev. F, 21-Aug-17 DWG: 6025 Notes 1. Use millimeters as the primary measurement 2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994 3. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip 4. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body 5. Exact shape and size of this feature is optional 6. Package warpage max. 0.08 mm 7. Applied only for terminals Revision: 21-Aug-17 Document Number: 64909 2 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 PAD Pattern www.vishay.com Vishay Siliconix Recommended Land Pattern PowerPAK® MLP55-31L Top side transparent view (not bottom view) Land pattern for MLP55-31L 5 (D2-5) 1.05 24 1.35 0.57 1 24 0.5 31 0.3 0.33 0.75 (D2-1) 31 1.03 (D2-4) 3.4 0.33 1.42 0.35 (D2-2) 1.03 (D2-3) 1.92 15 (L) 0.4 3.05 0.07 2.15 2.08 8 16 0.18 0.65 9 (L) 0.4 0.3 3.5 0.4 2.02 1.75 0.58 16 23 1.15 0.3 0.35 9 0.5 0.35 0.65 0.5 15 0.75 0.3 8 0.5 (E2-3) 1.98 (b) 0.25 5 (E2-1) 4.2 (K2) 0.22 (K1) 0.67 1.13 0.3 1 0.35 0.15 (E3) 0.45 (E2-2) 1.32 0.5 (e) 23 1.6 0.85 0.75 (D3) 0.3 1 All dimensions in millimeters 24 31 1 23 33 Component for MLP55-31L 32 Land pattern for MLP55-31L 35 33 8 16 9 Revision: 18-Oct-2019 15 Document Number: 66944 1 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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