SiC645, SiC645A
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Vishay Siliconix
60 A VRPower® Smart Power Stage (SPS) Module with Integrated
High Accuracy Current and Temperature Monitors
FEATURES
• Input range: 4.5 V to 18 V
• Supports 60 A DC current
• Compatible with 3.3 V (SiC645A) and 5 V
(SiC645) tri-state PWM
• Down slope current sensing
• ± 3 % accuracy current monitor (IMON) with REFIN input
• 8 mV/°C temperature monitor with OT flag
• Dedicated low side FET control input
DESCRIPTION
VRPower®
The SiC645 is a smart
device that integrates a
high side and low side MOSFET, a high performance driver
with integrated bootstrap FET. The SiC645 offers high
accuracy current and temperature monitors that can be fed
back to the controller and doubler to complete a multiphase
DC/DC system. They simplify design and increase
performance by eliminating the DCR sensing network and
associated thermal compensation. Light-load efficiency is
supported via a dedicated left control pin. An industry
leading thermally enhanced dual cooled, 5 mm x 5 mm
PowerPAK® MLP package allows minimal overall PCB real
estate and low profile construction.
The devices feature a 3.3 V (SiC645A) or 5 V (SiC645)
compatible tri-state PWM input that, working together with
multiphase PWM controllers, will provide a robustsolution in
the event of abnormal operating conditions. The SiC645
also improves system performance and reliability with
integrated fault protection of UVLO, over-temperature and
over-current. An open-drain fault reporting pin simplifies the
handshake between the smart VRPower device and
multiphase controllers and can be used to disable the
controller during start-up and fault conditions.
• Fault protection
- High side FET short and over-current protection
- Over-temperature protection
- VCC and VIN under voltage lockout (UVLO)
• Open drain fault reporting output
• Up to 2 MHz switching frequency
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
•
•
•
•
High frequency and high efficiency VRM and VRD
Core, graphic, and memory regulators for microprocessors
High density VR for server, networking, and cloud computing
POL DC/DC converters and video gaming consoles
TYPICAL APPLICATION DIAGRAM
+12 V
Multiphase
controller
TEMP
EN
GND
TMON
FAULT#
VIN
LOUT
VOUT
SW
PVCC
Smart
control
COUT
SiC645
GND
CSRTN#n
Shootthrough
protection
GND
PWM
CS#n
BOOT
LGCTRL
PWM
IMON
REFIN
PHASE
VCC
VCC
PVCC
+5 V
Fig. 1 - Typical Application Block Diagram
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TYPICAL APPLICATION CIRCUIT WITH SiC645
+3.3 V
VCCS
VCCS
VCC
VSENVCORE
PGVCORE
VCC
5V
LGCTRL
VIN
FAULT#
BOOT
TMON
TEMPVCORE
PWM1
PWM
CS1
IMON
CSRTN1
REFIN
RGNDVCORE
ENVCORE
SiC645
PVCC
5V
Multiphase
controller
VCC
5V
LGCTRL
VIN
PHASE
SW
GND
SiC645
PVCC
5V
5V
VIN
5V
VIN
FAULT# BOOT
TMON PHASE
SVDATA
SVCLK
nSVALERT
nVRHOT
PWM2
CS2
PWM
CSRTN2
REFIN
VCORE
SW
IMON
GND
nPINALERT
PWM3-5
PMSDA
N phases
CS3-5
PMSCL
CSRTN3-5
nPMALERT
SiC645
PVCC
5V
VCC
5V
LGCTRL
CFP
VIN
5V
VIN
FAULT# BOOT
TMON PHASE
VIN
PWM
PWM6
CS6
IMON
CSRTN6
REFIN
SW
GND
VINSEN
SiC645
PVCC
5V
VCC
5V
LGCTRL
VIN
PGVSA
TEMPVSA
FAULT# BOOT
TMON PHASE
ENVSA
PWMVSA
CSVSA
IMON
CSRTNVSA
REFIN
RGNDVSA
VSENVSA
PWM
5V
VIN
SW
GND
VSA
VCCS
GND
ADDRESS
CONFIG
Fig. 2 - Typical Application Circuit
S20-0486-Rev. C, 29-Jun-2020
Document Number: 65424
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+3.3 V
VCCS
VCCS
VCC
5V
LGCTRL
BOOT
IMON
PHASE
SW
5V
VIN
TMON
FAULT#
GND
CSENA
CSRTNA
PWM1
PWM
RGNDVCORE
CSRTNB
CSENB
PWMB
Digital
multiphase
VIN
PWM
REFIN
VCC
Phase doubler
PWMA
VSENVCORE
SiC645
PVCC
5V
SiC645
PVCC
5V
VCC
5V
LGCTRL
CS1
PWM
BOOT
IMON
PHASE
SW
REFIN
CSRTN1
VIN
5V
VIN
TMON
FAULT#
GND
Load
PWM2-5
CS2-5
N Phases
CSRTN2-5
TEMPVCORE
ENVCORE
SiC645
PVCC
5V
VCC
5V
LGCTRL
PWM
BOOT
IMON
PHASE
SW
REFIN
Phase doubler
5V
VIN
TMON
FAULT#
PWMA
PWM6
VIN
GND
CSENA
CSRTNA
PWM
CSRTNB
CSENB
PWMB
5V
ISL99227B
VCC
PVCC
5V
5V
LGCTRL
VIN
CS6
CSRTN6
VIN
PWM
BOOT
IMON
PHASE
SW
REFIN
TMON
VCCS
FAULT#
GND
Fig. 3 - Typical Application Circuit
S20-0486-Rev. C, 29-Jun-2020
Document Number: 65424
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FUNCTIONAL BLOCK DIAGRAM
PVCC
PHASE
VIN
BOOT
VIN
UVLO
BOOT
switch
control
2.5 V
LDO
HFET
CSH
2.5 V
VCC-BOOT level
shifter
VCCPOR
VUGH
33.5K (for 3.3 V)
16.5K (for 5.0 V)
PWMH
90 A
GH
Dead time and
shoot-through
logic
AGND-PGND
level shifter
100 mV
+
-
PHASE
GL
OCH
FAULT#
OT
OR function
VCCPOR
OCH
GH_BLANK
control
V(TJ)
CAL
and
level
shift
LFET
PVCC
CSL
LS
driver
GL
REFIN
IMON
GL_BLANK
control
+
-
HFET
short
PWML
+
-
VLGH
+
SW
PWM
logic
PWM
16.5K
HS
driver
20K
+
-
VCC
UVLO
VCC
VINPOR
2.5 V
V(TJ) = 0.6 V + 8 mV x TJ
OT + V(Tmax.) V(TJ) Temp.
sense
+
-
OCH
1 μs
pulse
REFIN +1.2 V
TJ
VINPOR
NC
LGCTRL TMON
GND
Fig. 4 - Functional Block Diagram
ORDERING INFORMATION
PART NUMBER
SiC645ADR-T1-GE3
MARKING CODE
TEMPERATURE
RANGE (°C)
PWM INPUT
(V)
PACKAGE (RoHS-compliant)
45D
-40 to +85
3.3
Dual cooled PowerPAK MLP55-32L
Dual cooled PowerPAK MLP55-32L
SiC645ALR-T1-GE3
45L
-10 to +100
3.3
SiC645AER-T1-GE3
45E
-40 to +125
3.3
Dual cooled PowerPAK MLP55-32L
SiC645ER-T1-GE3
45E
-40 to +125
5
Dual cooled PowerPAK MLP55-32L
S20-0486-Rev. C, 29-Jun-2020
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PINOUT CONFIGURATION
TMON
IMON
REFIN
GND
PWM
VIN
FAULT#
BOOT
PHASE
32
31
30
29
28
27
26
25
24
LGCTRL 1
23
VCC 2
VIN
22
VIN
21
VIN
20
GND
19
GND
GND 7
18
GND
GND 8
17
GND
VIN
34
GND
33
PVCC 3
GND 4
GL 5
GND
GND
35
6
10
11
12
13
14
15
SW
SW
SW
SW
SW
SW
SW
16
SW
9
Fig. 5 - Pinout Configuration
PIN CONFIGURATION
PIN NUMBER
NAME
FUNCTION
1
LGCTRL
Lower gate control signal input. LO = GL LO (LFET off). HI = normal operation (GL and GH strictly obey
PWM). This pin should be driven with a logic signal, or externally tied high if not required; it should not
be left floating
2
VCC
+5 V logic bias supply. Place a high quality low ESR ceramic capacitor (~1 μF/X7R) in close proximity
from this pin to GND
3
PVCC
+5 V gate drive bias supply. Place a high quality low ESR ceramic capacitor (~1 μF/X7R) in close
proximity from this pin to GND
4, 6, 7, 8, 17, 18,
19, 20, 29, 33, 35
GND
GND pins are internally connected. Pins 4 and 29 should be connected directly to the nearby GND
paddles on package bottom. Fig. 15 shows GND paddles should be connected to the system GND
plane with as many vias as possible to maximize thermal and electrical performance.
5
NC
No connect (This is a low side gate driver output (GL), optional to monitor for system debugging)
9, 10, 11, 12,
13, 14, 15, 16
SW
Switching junction node between HFET source and LFET drain. Connect directly to output inductor
21, 22, 23, 27,
34
VIN
Input of power stage (to drain of HFET). Place at least 2 ceramic capacitors (10 μF or higher, X5R or
X7R) in close proximity across VIN and GND. Pin 27 should not be used for decoupling. For optimal
performance, place as many vias as possible in the bottom side VIN paddle
24
PHASE
Return of boot capacitor. Internally connected to SW node so no external routing required for SW
connection
25
BOOT
Floating bootstrap supply pin for the upper gate drive. Place a high quality low ESR ceramic capacitor
(0.1 μF/X7R to 0.22 μF/X7R)i n close proximity across BOOT and PHASE pins
26
FAULT#
Open drain output pin. Any fault (over-current, over-temperature, shorted HFET, or POR / UVLO) will
pull this pin to ground. This pin may be connected to the controller enable pin or used to signal a fault
at the system level
28
PWM
PWM input of gate driver, compatible with 3.3 V and 5 V tri-state PWM signal
30
REFIN
Input for external reference voltage for IMON signal. This voltage should be between 0.8 V and 1.6 V.
Connect REFIN to the appropriate current sense input of the controller. Place a high quality low ESR
ceramic capacitor (~ 0.1 μF) in close proximity from this pin to GND
31
IMON
Current monitor output, referenced to REFIN. IMON will be pulled high (to REFIN +1.2 V) to indicate an
HFET shorted or over-current fault. Connect the IMON output to the appropriate current sense input of
the controller. No more than 56 pF capacitance can be directly connected across IMON and REFIN pins.
With a 100 series resistor, up to 470 pF may be used
TMON
Temperature monitor output. For multiphase, the TMON pins can be connected together as a common
bus; the highest voltage (representing the highest temperature) will be sent to the PWM controller. TMON
will be pulled high (to 2.5 V) to indicate an over-temperature fault. No more than 250 pF total
capacitance can be directly connected across TMON and GND pins; with a series resistor, a higher
capacitance load is allowed, such as 1 k for 100 nF load
32
S20-0486-Rev. C, 29-Jun-2020
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ABSOLUTE MAXIMUM RATINGS
ELECTRICAL PARAMETER
SYMBOL
Supply voltage
VCC, PVCC
Input supply voltage
PHASE, SW voltage
BOOT voltage
CONDITIONS
LIMIT
UNIT
-0.3 to +6
VIN
-0.3 to +25
VPH-GND, VSW-GND GND - 10 V, < 20 ns pulse width, 10 μJ
V
-0.3 to +25
VBOOT_GND
-0.3 to +36
Other I/O pin voltage
-0.3 to VCC + 0.3
Maximum junction temperature
(plastic package)
150
Maximum storage temperature range
°C
-65 to +150
Lead (Pb)-free reflow profile
-
-
Note
• Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
RECOMMENDED OPERATING RANGE
ELECTRICAL PARAMETER
Operating junction temperature range
Supply voltage (VCC, PVCC)
Input supply voltage (VIN)
MINIMUM
TYPICAL
MAXIMUM
UNIT
-40
-
125
°C
-
5±5%
-
4.5
-
18
V
THERMAL INFORMATION
THERMAL RESISTANCE
Dual cooled PowerPAK MLP55-32L (1)(2)(3)
JA (°C/W)
JC (°C/W)
10.7
1.6
Notes
JA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features
(2) For , the case temperature location is the center of the exposed metal pad on the package underside
JC
(3) These ratings vary with PCB layout and operating condition, and limited by device temperature and thermal shutdown trip point
(1)
S20-0486-Rev. C, 29-Jun-2020
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ELECTRICAL SPECIFICATIONS
(recommended operating conditions, unless otherwise noted. TJ = -40 °C to +125 °C)
PARAMETER
SYMBOL
LIMITS
TEST CONDITIONS
MIN. (1)
TYP.
MAX. (1)
-
100
-
-
12.5
-
UNIT
POWER RATING
TA = 25 °C, 150 A (2)
Maximum instant power dissipation
TA = 25 °C, JA = 10 °C/W, TJ = 150 °C
Maximum continuous power dissipation
(2)
W
THERMAL RESISTANCE
JB
Thermal resistance junction to PCB
JA
Thermal resistance junction to ambient
(2)
-
5.2
-
0 LFM (2)
-
10.7
-
400 LFM (2)
-
9.3
-
°C/W
VCC SUPPLY CURRENT
Logic standby current
Gate drive standby current
IVCC
PWM = open
-
4.75
-
mA
IPVCC
PWM = open
-
100
-
μA
IVCC
PWM = 300 kHz
-
4.75
-
IPVCC
PWM = 300 kHz
-
15
-
3.86
4.20 (3)
3.58
-
Logic operational current
Gate drive operational current
mA
POWER-ON RESET AND ENABLE
VCC rising POR threshold
-
VCC falling POR threshold
3.20
(3)
V
VCC POR hysteresis
-
280
-
mV
VCC POR delay to operation
-
125
197 (3)
μs
VIN rising POR threshold
-
4
4.2 (3)
VIN falling POR threshold
3.4 (3)
3.5
-
-
445
-
VIN POR hysteresis
V
mV
3.3 V PWM INPUT (see “Timing Diagram”)
Sink impedance
-
33.5
-
Source impedance
-
16.5
-
Tri-state lower gate falling threshold
-
1.11
-
Tri-state lower gate rising threshold
-
0.87
-
-
2.13
-
-
1.95
-
1.3 (3)
-
1.8 (3)
VCC = 5 V
Tri-state upper gate rising threshold
Tri-state upper gate falling threshold
Tri-state shutdown window
k
V
5 V PWM INPUT (see “Timing Diagram”)
Sink impedance
-
16.5
-
Source impedance
-
16.5
-
Tri-state lower gate falling threshold
-
1.51
-
Tri-state lower gate rising threshold
-
1.14
-
-
3.24
-
-
3.02
-
1.6 (3)
-
2.8 (3)
-
Tri-state upper gate rising threshold
VCC = 5 V
Tri-state upper gate falling threshold
Tri-state shutdown window
k
V
SWITCHING TIME
GH turn-on propagation delay
tPDHU
GL low to GH high, see Fig. 6
-
8
GH turn-off propagation delay
tPDLU
PWM low to GH low, see Fig. 6
-
40
-
GL turn-on propagation delay
tPDHL
GH low to GL high, see Fig. 6
-
8
-
GL turn-off propagation delay
tPDLL
PWM high to GL low, see Fig. 6
-
23
-
GL exit tri-state propagation delay
tPDTSL
Tri-state to GL high), see Fig. 6
-
25
-
GH exit tri-state propagation delay
tPDTSU
Tri-state to GH high, see Fig. 6
-
35
PWML tri-state shutdown hold-off time
tTSSHDL
PWM low to GL low, see Fig. 6
-
40
-
PWMH tri-state shutdown hold-off time
tTSSHDU
PWM low to GH low, see Fig. 6
-
50
-
S20-0486-Rev. C, 29-Jun-2020
ns
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ELECTRICAL SPECIFICATIONS
(recommended operating conditions, unless otherwise noted. TJ = -40 °C to +125 °C)
PARAMETER
SYMBOL
LIMITS
TEST CONDITIONS
MIN. (1)
TYP.
MAX. (1)
0.8 (3)
1.2
1.6 (3)
UNIT
CURRENT MONITOR
IREFIN voltage range
IMON current gain accuracy (VCC = 5 V)
10 A, TJ = 90 °C
-
±2
-
10 A, TJ = 40 °C to 25 °C
-
±3
-
10 A, TJ = 20 °C to 125 °C
-
±4
-
10 A, TJ = 0 °C to 125 °C
V
%
-
±5
-
Downslope blanking time
-
160
-
ns
HFET over-current trip
-
90
-
A
IMON to IREFIN at OCP
1.1 (3)
1.2
1.3 (3)
V
TEMPERATURE MONITOR
Over-temperature rising threshold
-
140
-
Over-temperature falling threshold
-
125
-
Over-temperature hysteresis
-
15
-
Temperature coefficient
TMON voltage at 25 °C temperature
TJ = 25 °C to 125 °C
-
8
-
TJ = -40 °C to +25 °C
-
8
-
V (TJ) = 0.6 V + (8 mV x TJ)
TMONhigh at over-temperature
-
0.80
-
2.3 (3)
2.5
2.7 (3)
°C
mV/
K
V
FAULT PIN
Output low voltage
5 mA
Leakage current
-
0.18
0.26
V
-
16
-
nA
-
0.09
-
V
-
16
-
BOOTSTRAP DIODE
Forward voltage drop
5 mA
On-resistance
RF
LGCTRL PIN
Rising threshold
Logic high, (normal: obeys PWM)
-
1.29
1.6
Falling threshold
Logic low, (forces GL low; left off)
0,70 c
1.01
-
V
MOSFETs
High side MOSFET (HFET) RDS(on)
-
3.6
-
Low side MOSFET (LFET) RDS(on)
-
0.76
-
m
Notes
(1) Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design
(2) These ratings vary with PCB layout and operating condition, and limited by SPS temperature and thermal shutdown trip point
(3) Limits apply across the operating temperature range
TIMING DIAGRAM
PWM
tPDLU
tPDHU
tPDTSU
tSSHDU
tPDTS
GH
tFU
tRU
tPDHL
GL
tRL
tFL
tTSSHDL
tPDLL
tPDLFUR
tPDUFLR
Fig. 6 - Timing Diagram
S20-0486-Rev. C, 29-Jun-2020
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TYPICAL CHARACTERISTICS (PVCC = 5 V, TA = 25 °C, unless otherwise stated)
98
98
Exclude 5 V losses
96
96
Efficiency (%)
Efficiency (%)
Include 5 V losses
92
90
88
86
86
82
80
0
30
60
90
120 150
Load (A)
180 210
96
240
0
90
86
90
120 150
Load (A)
180 210
94
240
400 kHz
500 kHz
92
1.20 V
1.00 V
0.90 V
0.80 V
88
60
96
Efficiency (%)
92
30
Fig. 10 - 1.2 V Power Stage Efficiency (VIN = 12 V,
fSW = 500 kHz; LOUT = 0.18 μH/0.17m/FP1008-180-R;
Auto-Phase Enabled in 6-Phase Operation)
2.50 V
1.80 V
1.50 V
1.35 V
94
Efficiency (%)
88
82
88
86
84
82
82
80
600 kHz
700 kHz
800 kHz
90
84
80
0
10
20
30
40
Load (A)
50
60
Fig. 8 - Power Stage Efficiency (VIN = 12 V, fSW = 500 kHz;
LOUT = 0.18 μH/0.17m/FP1008-180-R
0
10
20
30
Load (A)
16
2.50 V
1.80 V
1.50 V
1.35 V
1.20 V
1.00 V
10
8
6
0.90 V
0.80 V
4
60
12
10
8
6
400 kHz
500 kHz
600 kHz
4
2
50
700 kHz
800 kHz
14
Power Losses (W)
12
40
Fig. 11 - Power Stage Efficiency (VIN = 12 V, fSW = 500 kHz;
LOUT = 0.18 μH/0.17m/FP1008-180-R
14
0
Include 5 V losses
90
84
Fig. 7 - 1.8 V VOUT Power Stage Efficiency (VIN = 12 V,
fSW = 500 kHz; LOUT = 0.18 μH/0.17m/FP1008-180-R;
Auto-Phase Enabled in 6-Phase Operation)
Power Losses (W)
92
84
80
Exclude 5 V losses
94
94
2
0
0
10
20
30
40
Load (A)
50
60
Fig. 9 - Power Dissipation (VIN = 12 V, fSW = 500 kHz;
LOUT = 0.18 μH/0.17m/FP1008-180-R
S20-0486-Rev. C, 29-Jun-2020
0
10
20
30
Load (A)
40
50
60
Fig. 12 - Power Dissipation (VIN = 12 V, fSW = 500 kHz;
LOUT = 0.18 μH/0.17m/FP1008-180-R
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DETAILED OPERATIONAL DESCRIPTION
The SiC645 is an optimized driver and power stage solution
for high density synchronous DC/DC power conversion. It
includes high performance GH and GL drivers, a NFET
controlled to function as a bootstrap diode, and MOSFET
pair optimized for high switching frequency buck voltage
regulators. It also includes advanced power management
features.
1. Accurate current and thermal reporting outputs
2. Fault protections of HFET over-current, HFET short,
over-temperature, VCC UVLO, and VIN UVLO
Power-On Reset (POR)
During initial start-up, the VCC voltage rise is monitored.
Once the rising VCC voltage exceeds 3.86 V (typical) for
125 μs, then normal operation of the driver is enabled. The
PWM signals are passed through to the gate drivers, the
TMON output is valid, and the IMON output starts at zero, and
becomes valid on the first GL signal. If VCC drops below the
falling threshold of 3.58 V (typical), operation of the driver is
disabled. The PVCC voltage is not monitored as it should to
be from the same supply as VCC.
VIN POR is also monitored. When both VCC and VIN reach
above their POR trip points, it enables HFET over-current
protection.
Both VCC and VIN POR are gated to the FAULT# pin, which
goes high once both VCC and VIN are above their POR levels
and no other faults occur.
Shoot-Through Protection
Prior to POR, the undervoltage protection function is
activated and both GH and GL are held active low (HFET
and LFET off). After POR (the rising thresholds; see electrical
specifications), and 125 μs delay, the PWM and LGCTRL
signals are used to control both high side and low-side
MOSFETs, as shown in Table 1.
SiC645’s dead time control is optimized for high efficiency
and guarantees that simultaneous conduction of both FETs
cannot occur.
Should the driver have no bias voltage applied (either VCC or
PVCC missing) and be unable to actively hold the MOSFETs
off, an integrated 20 k resistor from the upper MOSFET
gate to source will aid in keeping the HFET device in its off
state. This can be especially critical in applications where
the input voltage rises prior to the SiC645 VCC and PVCC
supplies.
Tri-State PWM Input
The SiC645A supports a 3.3 V PWM tri-level input,
compatible with Vishay’s digital multiphase controllers as
well as other control IC’s utilizing 3.3 V PWM logic. Use the
SiC645 for 5 V PWM logic. Should the pin be pulled into and
remain in the tri-state window for a set hold off time
( 25 ns), the driver will force both MOSFETs to their off
states. When the PWM signal moves outside the shutdown
window, the driver immediately resumes driving the
MOSFETs according to the PWM commands.
This feature is utilized by Vishay PWM controllers as a
method of forcing both MOSFETs off. Should the PWM
input be left floating, the pin will be pulled into the tri-state
window internally and thus force both MOSFETs to a safe off
state.
Although the PWM input can sustain a voltage as high as
VCC, the SiC645 is not compatible with a controller that
actively drives its mid-level in tri-state higher than 1.7 V.
Bootstrap Function
The SiC645 features an internal NFET that is controlled to
function as a bootstrap diode. A high quality ceramic
capacitor should be placed in close proximity across the
BOOT and PHASE pins. The bootstrap capacitor can range
between 0.1 μF to 0.22 μF (0402 to 0603 and X5R to X7R)
for normal buck switching applications.
Current Monitoring
LFET current is monitored and a signal proportional to that
current is output on the IMON pin (relative to the REFIN pin).
The IMON and REFIN pins should be connected to the
appropriate current sense input pin of the controller. This
method does not require external RSENSE or DCR sensing of
inductor current.
Fig. 13 depicts the low side current sense concept and
demonstrates how the accuracy will be defined. After the
falling edge of PWM, there are two delays; one that
represents the expected propagation delay from PWM to
GH/SW, and a second blanking delay to allow time for the
transition to settle; typical total time is ~ 350 ns. The IMON
output approximates the actual IL waveform shown within
the tolerance band.
IL x IMONGain
IMON
TABLE 1 -
GH AND GL OPERATION TRUTH TABLE
SW
PWM
LGCTRL
GH
GL
Tri-state
X
0
0
0
1
0
1
1
1
0
0
0
0
LFET off
GL low
1
0
1
0
HFET on
Normal
S20-0486-Rev. C, 29-Jun-2020
Toleran
c
Band e
HFET, LFET COMMENT
Both off
-
1
LFET on
Normal
0
HFET on
Normal
GL
GH
PWM
Off dly
On dly
Fig. 13 - LFET Current Sample Diagram
Document Number: 65424
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The HFET current is not monitored in the same way, so no
valid measured current is available while PWM is high (and
the short delays before and after). During this time, the IMON
will output the last valid LFET current before the sampling
stopped. On start-up after POR, the IMON will output zero
(relative to REFIN, which represents zero current) until the
switching begins, and then the current can be properly
measured.
Thermal Monitoring
The SiC645 monitors its internal temperature and provides
a signal proportional to that temperature on the TMON pin.
TMON has a voltage of 600 mV at 0 °C and reflects
temperature at 8 mV/°C. The TMON output is valid 125 μs
after VCC POR.
The high side FET current is separately monitored for OC
conditions; see the “over-current protection” section.
TMON pin
600 mV + 8 mV/°C x temperature
Over-Current Protection
Fig. 14 shows the timing diagram of an over-current fault.
There is a comparator monitoring the HFET current while it
is on (GH high; also requires VIN POR above its trip point).
If the current is higher than 90 A (typical; not
user-programmable), then an OC fault is detected. The GH
will be forced low, even if PWM is still high; this effectively
shortens the PWM (and GH) pulse width, to limit the current.
The IMON pin is pulled up to REFIN +1.2 V, which will be
detected by the controller as an over-current fault. The
controller is then expected to force PWM to tri-state (which
gates off both FETs) or low state (turns on LFET), either of
which signals the SPS that the fault has been
acknowledged. This starts a ~ 1 μs fault clear delay. The
IMON flag is released after the delay. The driver will then
respond to PWM inputs normally.
Note that if the controller does NOT acknowledge, the IMON
flag will stay high indefinitely, which will also hold GH low.
If OC is detected, the FAULT# pin is also pulled low; the
timing on the FAULT# pin will follow that of the IMON pin.
ILIM
HFET
current
Fault
reporting
configuration
Fig. 15 - Over-Temperature Fault
Fig. 15 shows a simplified functional representation. The top
section includes the sensor and the output buffer. The
bottom section includes the protection sensing, that will pull
the output high. The TMON pin is configured internally such
that a user can tie multiple pins together externally and the
resulting TMON bus will assume the voltage of the highest
contributor (representing the highest temperature).
Thermal Protection
If the internal temperature exceeds the over-temperature
trip point (+140 °C typical), the TMON pin is pulled high (to
~2.5 V), and the FAULT# pin is pulled low. No other action is
taken on-chip. Both the TMON and FAULT# pins will remain
in the fault mode, until the junction temperature drops below
+125 °C typical; at that point, the TMON and FAULT# pins
resume normal operation; the DMP can detect that the fault
condition has gone away, and decide what to do next.
FAULT Reporting
0
No GH allowed
GH
FollowPWM low to
support OV following OC
GL
DMP enters PWM mid-state
or low to acknowledge fault
PWM
IMON-REFIN
Over-temperature
1.2 V
Fault#
Fault
clear
delay
1 μs
Resume
normal OP
(if recovers)
Fig. 14 - Over-current Fault Timing Diagram
Shorted HFET Protection
In the case of a shorted HFET, the SW node will have
excessive positive voltage present even when the LFET is
turned on. The SiC645 monitors the SW node during periods
when the LFET is on (GL is high), and should that voltage
exceed 100 mV (typical), the HFET short fault is declared.
The SiC645 will pull the IMON pin high, and the FAULT# will
be pulled low. But the fault will be latched; VCC POR is
needed to reset it. GH will be gated low (ignore PWM = high),
but the SiC645 will still respond to PWM tri-state and logic
low.
S20-0486-Rev. C, 29-Jun-2020
Over-current and shorted HFET detections will pull the IMON
pin to a high (fault) level, such that the DMP should quickly
recognize it as out of the normal range. Over-temperature
detection will pull the TMON pin to a high (fault) level, such
that the PWM controller should quickly recognize it as out of
the normal range.
All of the above faults, plus the VCC and VIN POR (UVLO)
conditions, will also pull down the FAULT# pin. This can be
used by the controller (or system) as fault detection, and can
also be used to disable the controller, through its enable pin.
The fault reporting and respective SPS response are
summarized in Table 2.
Document Number: 65424
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SiC645, SiC645A
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TABLE 2 - FAULT REPORTING SUMMARY
FAULT EVENT
IMON
TMON
FAULT#
RESPONSE
OC
High
n/a
Low
GH gated off. The controller should acknowledge and
force its PWM to tri-state to keep both HFET and LFET
off. The fault is cleared 1 μs after PWM enters
tri-state, otherwise, it stays asserted. (if system OVP
occurs, the controller may sen PWM to turn on LEFT)
Shorted HFET
IMON latched high
n/a
FAULT# latched low
GH gated off, until fault latch is cleared by VCC POR. GL
follows PWM.
OT
n/a
High
Low
GH and GL follow PWM.
VCC UVLO
IMON - REFIN = 0 V
TMON not valid
Low
Switching stops while in UVLO. Once above VCC POR
after 125 μs: GH and GL follow PWM; the FAULT# is
released; TMON is valid; IMON - REFIN is valid after GL
first goes low.
VIN UVLO
OC not valid
n/a
Low
GH and GL follow PWM.
PCB LAYOUT CONSIDERATIONS
Proper PCB layout will reduce noise coupling to other
circuits, improve thermal performance, and maximize the
efficiency. The following is meant to lead to an optimized
layout:
• Place multiple 10 μF or greater ceramic capacitors directly
at device between VIN and PGND as indicated in Fig. 16
This is the most critical decoupling and reduced parasitic
inductance in the power switching loop. This will reduce
overall electrical stress on the device as well as reduce
coupling to other circuits. Best practice is to place the
decoupling capacitors on the same PCB side as the
device.
For a design with tight space requirements, these
decoupling capacitors can be placed under the device,
i.e., bottom layer, as shown in Fig. 18
• Connect GND to the system GND plane with a large via
array as close to the GND pins as design rules allow. This
improves thermal and electrical performance.
• Place PVCC, VCC and BOOT-PHASE decoupling
capacitors at the IC pins as shown in Fig. 16.
S20-0486-Rev. C, 29-Jun-2020
• Note that the SW plane connecting the SiC645 and
inductor must carry full load current and will create
resistive loss if not sized properly. However, it is also a
very noisy node that should not be oversized or routed
close to any sensitive signals. Best practice is to place the
inductor as close to the device as possible and thus
minimizing the required area for the SW connection. If one
must choose a long route of either the VOUT side of the
inductor or the SW side, choose the quiet VOUT side. Best
practice is to locate the SiC645 as close to the final load
as possible and thus avoid noisy or lossy routes to the
load.
• The IMON and IREF network and their vias should not sit on
the top of the VIN plane, a keep out area is recommended,
as shown in Fig. 18.
• The PCB is the best thermal heatsink material than any top
side cooling materials. The PCB always has enough vias
to connect VIN and GND planes. Insufficient vias will yield
lower efficiency and very poor thermal performance.
Fig. 17 and Fig. 18 show a multiphase PCB layout example.
Document Number: 65424
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SiC645, SiC645A
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PCB LAYOUT FOR MINIMIZING CURRENT LOOPS
27
26
PHASE
28
BOOT
FAULT#
GND
29
VIN
+5 V PVCC
30
PWM
LGCTRL 1
VCC
2
GND
IMON
31
REFIN
TMON
32
25
24
VIN (34)
GND(33)
3
23
VIN
22
VIN
21
VIN
4
NC 5
GND (35)
20
GND
19
GND
GND
6
GND
7
18
GND
8
17
ND
GN
ND
D
GND
10
11
12
13
14
15
SW
SW
SW
SW
SW
SW
SW
16
SW
9
Inductor
Fig. 16 - Single-Phase PCB Layout for Minimizing Current Loops
Fig. 17 - Multi-Phase PCB Layout Example Top Layer
S20-0486-Rev. C, 29-Jun-2020
Document Number: 65424
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SiC645, SiC645A
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Keep out area
VIN decoupling
capacitors
Fig. 18 - Multi-Phase PCB Layout Example Bottom Layer
S20-0486-Rev. C, 29-Jun-2020
Document Number: 65424
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SiC645, SiC645A
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Vishay Siliconix
PRODUCT SUMMARY
Part number
SiC645
SiC645A
Description
60 A smart power stage, 4.5 VIN to 18 VIN, 5 V
PWM with diode emulation mode
60 A smart power stage, 4.5 VIN to 18 VIN, 3.3 V
PWM with diode emulation mode
Input voltage min. (V)
4.5
4.5
Input voltage max. (V)
18
18
Continuous current rating max. (A)
Switch frequency max. (kHz)
Enable (yes / no)
Monitoring features
Protection
Light load mode
Pulse-width modulation (V)
Package type
Package size (W, L, H) (mm)
60
60
2000
2000
No
No
IMON, TMON
IMON, TMON
UVLO, OCP, OTP, HS-short
UVLO, OCP, OTP, HS-short
Diode emulation
Diode emulation
5
3.3
PowerPAK MLP55-32L double cooling
PowerPAK MLP55-32L double cooling
5.0 x 5.0 x 0.60
5.0 x 5.0 x 0.60
Status code
2
2
Product type
VRPower (DrMOS)
VRPower (DrMOS)
Applications
Computer, industrial, networking
Computer, industrial, networking
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?65424.
S20-0486-Rev. C, 29-Jun-2020
Document Number: 65424
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Package Information
www.vishay.com
Vishay Siliconix
D2-4
0.2
D2-1
0.2
D2-2
0.08 C
L
24
A1
A2
32
D
Pin 1 dot
by marking
A
0.10
0.10 C A
4
2x
A
C A B
PowerPAK® MLP55-32 Double Cooling Case Outline
17
8
F1
L
B
E2-5
b
K2
E2-2
K1
K3
e
MLP55-32L
(5 mm x 5 mm)
K4
Q1
E
E2-4
P2
E2-1
1
E2-3
Q2
23
DIM.
A (3)
A1
A2
b (2)
D
D2-1
D2-2
D2-3
D2-4
D2-5
e
E
E2-1
E2-2
E2-3
E2-4
E2-5
F1
K1
K2
K3
K4
L
L1
P1
P2
Q1
Q2
N (1)
MIN.
0.56
0.00
0.20
1.45
1.95
4.25
1.10
1.80
1.10
0.15
0.35
0.25
3.95
0.75
2.05
1.30
Side view
MILLIMETERS
NOM.
0.61
0.20 ref.
0.25
5.00 BSC
1.50
2.00
4.30
4.00 BSC
3.50 BSC
0.50 BSC
5.00 BSC
1.15
1.85
1.15
3.50 BSC
3.50 BSC
0.20
0.55 ref.
0.15 ref.
0.75 ref.
1.00 ref.
0.40
0.30
4.00
2.10
1.35
31
D2-3
Bottom view
MAX.
0.66
0.05
MIN.
0.022
0.000
0.30
0.008
1.55
2.05
4.35
0.057
0.077
0.167
1.20
1.90
1.20
0.043
0.071
0.043
0.25
0.006
0.45
0.35
4.05
1.15
2.15
1.40
0.014
0.010
0.1555
0.030
0.081
0.051
F1
D2-5
L1
Top view
9
16
C
P1
L
INCHES
NOM.
0.024
0.008 ref.
0.010
0.196 BSC
0.059
0.079
0.169
0.157 BSC
0.138 BSC
0.020 BSC
0.197 BSC
0.045
0.073
0.045
0.138 BSC
0.138 BSC
0.008
0.022 ref.
0.006 ref.
0.030 ref.
0.039 ref.
0.016
0.012
0.1575
0.083
0.053
31
MAX.
0.026
0.002
0.012
0.061
0.081
0.171
0.047
0.075
0.047
0.010
0.018
0.014
0.1595
0.045
0.085
0.055
ECN: T20-0103-Rev. B, 23-Mar-2020
DWG: 6054
Notes
• Use millimeters as the primary measurement
• Dimensioning and tolerances conform to ASME Y14.5M-1994
• The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
• Exact shape and size of this feature is optional
• Package warpage max. 0.08 mm
(1) N is the number of terminals. Nd1 and Nd3 is the number of terminals in y-direction. Nd2 and Nd4 is the number of terminals in x-direction
(2) Dimensions b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip
(3) Applied only for terminals
Document Number: 77713
1
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Revision: 23-Mar-2020
PAD Pattern
www.vishay.com
Vishay Siliconix
Recommended Land Pattern PowerPAK® MLP55-32L
Component for MLP55-32L
Top side transparent view
(no bottom view)
16
(D2-3)
4.50
0.30
0.75
0.5 x 2
= 1.00
1.00
0.30
0.30
1.25
0.50
0.5 x 3
= 1.50
3.10
1.95
1.45
1.25
0.20
17
8
9
0.30
(K3)
2.30
23
1
0.75
0.40
9
0.30
24
0.80
5.00
(E2-2)
1.85
(P2)
1.70
17
8
0.50
0.20
0.30
0.75
(P3)
0.55
0.40
(E2-1)
1.15
(P1)
0.55
(K4) 0.75
1.35
(E2-3)
1.15
23
1
5.00
32
0.5 x 4 = 2.00
0.325
0.175
24
0.30
1.60
2.15
0.5 x 8 = 4.00
0.30
0.5 x 2 0.50
= 1.00
32
0.30
0.75
(D2-2)
2.00
(b)
(K2) 0.25
0.20
0.40
(D2-1)
1.50
(K1)
0.20
Land pattern for MLP55-32L
(L)
0.40
0.40
5.00
0.40
0.75
16
0.5 x 7= 3.50
0.75
Component and land pattern
for MLP55-32L
24
32
23
1
Component for MLP55-32L
Land pattern for MLP55-32L
17
8
9
16
All dimensions are in millimeters
Revision: 20-Sep-16
Document Number: 77768
1
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Legal Disclaimer Notice
www.vishay.com
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay's knowledge of typical
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements
about the suitability of products for a particular application. It is the customer's responsibility to validate that a particular product
with the properties described in the product specification is suitable for use in a particular application. Parameters provided in
datasheets and / or specifications may vary in different applications and performance may vary over time. All operating
parameters, including typical parameters, must be validated for each customer application by the customer's technical experts.
Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited
to the warranty expressed therein.
Hyperlinks included in this datasheet may direct users to third-party websites. These links are provided as a convenience and
for informational purposes only. Inclusion of these hyperlinks does not constitute an endorsement or an approval by Vishay of
any of the products, services or opinions of the corporation, organization or individual associated with the third-party website.
Vishay disclaims any and all liability and bears no responsibility for the accuracy, legality or content of the third-party website
or for that of subsequent links.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please
contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
© 2022 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 01-Jan-2022
1
Document Number: 91000
