SiC657
www.vishay.com
Vishay Siliconix
50 A VRPower® Integrated Power Stage
DESCRIPTION
FEATURES
The SiC657 is integrated power stage solutions optimized
for synchronous buck applications to offer high current, high
efficiency, and high power density performance. Packaged
in Vishay’s proprietary 5 mm x 5 mm MLP package, SiC657
enables voltage regulator designs to deliver up to 50 A
continuous current per phase.
• Thermally enhanced PowerPAK® MLP55-31L
package
• Vishay’s Gen IV MOSFET technology and a low
side MOSFET with integrated Schottky diode
• Delivers in excess of 50 A continuous current,
55 A at 10 ms peak current
• High efficiency performance
• High frequency operation up to 2 MHz
• Power MOSFETs optimized for 19 V input stage
• 5 V PWM logic with tri-state and hold-off
• Supports PS4 mode light load requirement for IMVP8 with
low shutdown supply current (5 V, 3 μA)
• Under voltage lockout for VCIN
The internal power MOSFETs utilizes Vishay’s
state-of-the-art Gen IV TrenchFET technology that delivers
industry benchmark performance to significantly reduce
switching and conduction losses.
The SiC657 incorporates an advanced MOSFET gate driver
IC that features high current driving capability, adaptive
dead-time control, an integrated bootstrap Schottky diode,
and zero current detection to improve light load efficiency.
The driver is also compatible with a wide range of PWM
controllers, supports tri-state PWM, and 5 V PWM logic.
A user selectable diode emulation mode (ZCD_EN#) is
included to improve the light load performance. The device
also supports PS4 mode to reduce power consumption
when system operates in standby state.
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
• Multi-phase VRDs for computing, graphics card and
memory
• Intel IMVP-8 VRPower delivery
- VCORE, VGRAPHICS, VSYSTEM AGENT Skylake, Kabylake
platforms
- VCCGI for Apollo Lake platforms
• Up to 24 V rail input DC/DC VR modules
TYPICAL APPLICATION DIAGRAM
5V
VIN
V IN
VDRV
BOOT
PHASE
VCIN
ZCD_EN#
PWM
controller
PWM
VSWH
VOUT
Gate
driver
PGND
GL
C GND
Fig. 1 - Typical Application Diagram
S19-0327-Rev. A, 08-Apr-2019
Document Number: 70090
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GL
CGND
N.C. 4
BOOT 5
PGND
N.C. 6
VIN
VSWH 21
20 VSWH
VSWH 20
19 VSWH
VSWH 19
18 VSWH
VSWH 18
17 VSWH
VSWH 17
16 VSWH
VSWH 16
N.C.
VDRV
PGND
VSWH
GL
N.C.
2 ZCD_EN#
32
CGND
3 VCIN
4 N.C.
35
PGND
5 BOOT
6 N.C.
34
VIN
7 PHASE
8 VIN
Top view
VIN
PGND
PGND
PGND
11 10
PGND
15 14 13 12
PGND
12 13 14 15
VIN
VIN
10 11
VIN
21 VSWH
1 PWM
GL
VIN
9
VSWH 22
PGND
VIN 8
VSWH 23
22 VSWH
PGND
PHASE 7
23 VSWH
PGND
VCIN 3
24 25 26 27 28 29 30 31
9
VIN
PWM 1
VSWH
VSWH
VSWH
GL
VSWH
PGND
VDRV
N.C.
N.C.
33
GL
31 30 29 28 27 26 25 24
ZCD_EN# 2
VSWH
PINOUT CONFIGURATION
Bottom view
Fig. 2 - Pin Configuration
PIN CONFIGURATION
PIN NUMBER
NAME
1
PWM
2
ZCD_EN#
3
VCIN
5
BOOT
4, 6, 30, 31
N.C.
7
PHASE
8 to 11, 34
VIN
FUNCTION
PWM input logic
The ZCD_EN# pin enables or disables diode emulation. When ZCD_EN# is LOW, diode emulation is
allowed. When ZCD_EN# is HIGH, continuous conduction mode is forced.
ZCD_EN# can also be put in a high impedance mode by floating the pin. If both ZCD_EN# and PWM
are floating, the device shuts down and consumes typically 3 μA (9 μA max.) current
Supply voltage for internal logic circuitry
High side driver bootstrap voltage
Pin 4 can be either left floating or connected to CGND. Internally it is either
connected to GND or not internally connected depending on manufacturing
location.
Factory code “G” on line 3, pin 4 = CGND
Factory code “T” on line 3, pin 4 = not internally connected
P/N
P/N
LL
LL
GYWW
TYWW
Return path of high side gate driver
Power stage input voltage. Drain of high side MOSFET
12 to 15, 28, 35
PGND
Power ground
16 to 26
VSWH
Phase node of the power stage
27, 33
GL
29
VDRV
Supply voltage for internal gate driver
32
CGND
Signal ground
Low side MOSFET gate signal
ORDERING INFORMATION
PART NUMBER
SiC657CD-T1-GE3
SiC657DB
S19-0327-Rev. A, 08-Apr-2019
PACKAGE
PowerPAK MLP55-31L
MARKING CODE
OPTION
SiC657
5 V PWM optimized
Reference board
Document Number: 70090
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SiC657
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PART MARKING INFORMATION
=
Pin 1 Indicator
=
Part Number Code
=
Siliconix Logo
=
ESD Symbol
F
=
Assembly Factory Code
Y
=
Year Code
WW
=
Week Code
LL
=
Lot Code
P/N
P/N
LL
FYWW
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL PARAMETER
CONDITIONS
LIMIT
VIN
-0.3 to +28
Control logic supply voltage
VCIN
-0.3 to +7
Drive supply voltage
VDRV
Input voltage
Switch node (DC voltage)
-0.3 to +7
-0.3 to +28
VSWH
Switch node (AC voltage) (1)
BOOT voltage (DC voltage)
-7 to +35
BOOT to PHASE (DC voltage)
40
-0.3 to +7
VBOOT-PHASE
BOOT to PHASE (AC voltage) (3)
-0.3 to +8
All logic inputs and outputs (PWM, ZCD_EN#)
-0.3 to VCIN +0.3
Max. operating junction temperature
TJ
150
Ambient temperature
TA
-40 to +125
Storage temperature
Tstg
-65 to +150
Human body model, JESD22-A114
2000
Charged device model, JESD22-C101
1000
Electrostatic discharge protection
V
33
VBOOT
BOOT voltage (AC voltage) (2)
UNIT
°C
V
Notes
• Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
(1) The specification values indicated “AC” is V
SWH to PGND -8 V (< 20 ns, 10 μJ), min. and 35 V (< 50 ns), max.
(2) The specification value indicates “AC voltage” is V
BOOT to PGND, 40 V (< 50 ns) max.
(3) The specification value indicates “AC voltage” is V
BOOT to VPHASE, 8 V (< 50 ns) max.
RECOMMENDED OPERATING RANGE
ELECTRICAL PARAMETER
Input voltage (VIN)
MINIMUM
TYPICAL
MAXIMUM
4.5
-
24
Drive supply voltage (VDRV)
4.5
5
5.5
Control logic supply voltage (VCIN)
4.5
5
5.5
5.5
BOOT to PHASE (VBOOT-PHASE, DC voltage)
4
4.5
Thermal resistance from junction to ambient
-
10.6
-
Thermal resistance from junction to case
-
1.6
-
S19-0327-Rev. A, 08-Apr-2019
UNIT
V
°C/W
Document Number: 70090
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ELECTRICAL SPECIFICATIONS
(ZCD_EN# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 °C, unless otherwise stated)
PARAMETER
SYMBOL
TEST CONDITION
LIMITS
UNIT
MIN.
TYP.
MAX.
VPWM = FLOAT
VPWM = FLOAT, VZCD_EN# = 0 V
fS = 300 kHz, D = 0.1
fS = 300 kHz, D = 0.1
fS = 1 MHz, D = 0.1
VPWM = VZCD_EN# = FLOAT,
TA = -10 °C to +100 °C
-
80
120
300
10
30
20
-
-
3
9
μA
IF = 2 mA
-
-
0.65
V
3.6
0.72
1.1
3.4
-
3.9
1
2.5
1.35
3.7
325
250
-
4.2
1.3
1.6
4
350
-350
3.6
1.4
2.5
1.8
3.15
375
450
-
3.9
1.7
2.1
3.4
100
-100
5
POWER SUPPLY
Control logic supply current
IVCIN
Drive supply current
IVDRV
PS4 mode supply current
BOOTSTRAP SUPPLY
Bootstrap diode forward voltage
PWM CONTROL INPUT
Rising threshold
Falling threshold
Tri-state voltage
Tri-state rising threshold
Tri-state falling threshold
Tri-state rising threshold hysteresis
Tri-state falling threshold hysteresis
PWM input current
IVCIN + IVDRV
VF
VTH_PWM_R
VTH_PWM_F
VTRI
VTRI_TH_R
VTRI_TH_F
VHYS_TRI_R
VHYS_TRI_F
IPWM
ZCD_EN# CONTROL INPUT
Rising threshold
VTH_ZCD_EN#_R
Falling threshold
VTH_ZCD_EN#_F
Tri-state voltage
VTRI_ZCD_EN#
Tri-state rising threshold
VTRI_ZCD_EN#_R
Tri-state falling threshold
VTRI_ZCD_EN#_F
Tri-state rising threshold hysteresis VHYS_TRI_ZCD#_R
Tri-state falling threshold hysteresis VHYS_TRI_ZCD#_F
VPWM = FLOAT
VPWM = 5 V
VPWM = 0 V
ZCD_EN# input current
IZCD_EN#
PS4 exit latency
TIMING SPECIFICATIONS
Tri-state to GH/GL rising
propagation delay
Tri-state hold-off time
GH - turn off propagation delay
GH - turn on propagation delay
(dead time rising)
GL - turn off propagation delay
GL - turn on propagation delay
(dead time falling)
PWM minimum on-time
PROTECTION
tPS4EXIT
3.3
1.1
1.5
2.9
-
tPD_TRI_R
-
20
-
tTSHO
tPD_OFF_GH
-
150
20
-
-
15
-
tPD_OFF_GL
-
20
-
tPD_ON_GL
-
20
-
tPWM_ON_MIN.
30
-
-
2.4
-
3.4
2.9
500
3.9
-
Under voltage lockout
Under voltage lockout hysteresis
tPD_ON_GH
VUVLO
VZCD_EN# = FLOAT
VZCD_EN# = 5 V
VZCD_EN# = 0 V
No load, see fig. 4
VCIN rising, on threshold
VCIN falling, off threshold
VUVLO_HYST
μA
mA
V
mV
μA
V
mV
μA
μs
ns
V
mV
Notes
(1) Typical limits are established by characterization and are not production tested
(2) Guaranteed by design
S19-0327-Rev. A, 08-Apr-2019
Document Number: 70090
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SiC657
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DETAILED OPERATIONAL DESCRIPTION
PWM Input with Tri-state Function
Switch Node (VSWH and PHASE)
The PWM input receives the PWM control signal from the
VR controller IC. The PWM input is designed to be
compatible with standard controllers using two state logic
(H and L) and advanced controllers that incorporate tri-state
logic (H, L and tri-state) on the PWM output. For two state
logic, the PWM input operates as follows. When PWM is
driven above VPWM_TH_R the low side is turned ON and the
high side is turned ON. When PWM input is driven below
VPWM_TH_F the high side is turned OFF and the low side is
turned ON. For tri-state logic, the PWM input operates as
previously stated for driving the MOSFETs when PWM is
logic high and logic low. However, there is an third state that
is entered as the PWM output of tri-state compatible
controller enters its high impedance state during shut-down.
The high impedance state of the controller’s PWM output
allows the SiC657 to pull the PWM input into the tri-state
region (see definition of PWM logic and tri-state, fig. 4). If the
PWM input stays in this region for the tri-state hold-off
period, tTSHO, both high side and low side MOSFETs are
turned OFF. The function allows the VR phase to be
disabled without negative output voltage swing caused by
inductor ringing and saves a Schottky diode clamp. The
PWM and tri-state regions are separated by hysteresis to
prevent false triggering. The SiC657 incorporates PWM
voltage thresholds that are compatible with 5 V.
The switch node, VSWH, is the circuit power stage output.
This is the output applied to the power inductor and output
filter to deliver the output for the buck converter. The PHASE
pin is internally connected to the switch node VSWH. This pin
is to be used exclusively as the return pin for the BOOT
capacitor.
Diode Emulation Mode and PS4 Mode (ZCD_EN#)
The ZCD_EN# pin enables or disables diode emulation
mode. When ZCD_EN# is driven below VTH_ZCD_EN#_F, diode
emulation is allowed. When ZCD_EN# is driven above
VTH_ZCD_EN#_R, continuous conduction mode is forced.
Diode emulation mode allows for higher converter efficiency
under light load situations. With diode emulation active, the
SiC657 will detect the zero current crossing of the output
inductor and turn off the low side MOSFET. This ensures
that discontinuous conduction mode (DCM) is achieved.
Diode emulation is asynchronous to the PWM signal,
therefore, the SiC657 will respond to the ZCD_EN# input
immediately after it changes state.
The ZCD_EN# pin can be floated resulting in a high
impedance state. High impedance on the input of ZCD_EN#
combined with a tri-stated PWM output will shut down the
SiC657, reducing current consumption to typically 5 μA.
This is an important feature in achieving the low standby
current requirements required in the PS4 state in ultrabooks
and notebooks.
Voltage Input (VIN)
This is the power input to the drain of the high side power
MOSFET. This pin is connected to the high power
intermediate BUS rail.
Ground Connections (CGND and PGND)
PGND (power ground) should be externally connected
to CGND (control signal ground). The layout of the printed
circuit board should be such that the inductance separating
CGND and PGND is minimized. Transient differences due to
inductance effects between these two pins should not
exceed 0.5 V
Control and Drive Supply Voltage Input (VDRV, VCIN)
VCIN is the bias supply for the gate drive control IC. VDRV is
the bias supply for the gate drivers. It is recommended to
separate these pins through a resistor. This creates a low
pass filtering effect to avoid coupling of high frequency gate
drive noise into the IC.
Bootstrap Circuit (BOOT)
The internal bootstrap diode and an external bootstrap
capacitor form a charge pump that supplies voltage to the
BOOT pin. An integrated bootstrap diode is incorporated so
that only an external capacitor is necessary to complete the
bootstrap circuit. Connect a boot strap capacitor with one
leg tied to BOOT pin and the other tied to PHASE pin.
Shoot-Through Protection and Adaptive Dead Time
The SiC657 has an internal adaptive logic to avoid shoot
through and optimize dead time. The shoot through
protection ensures that both high side and low side
MOSFETs are not turned ON at the same time. The adaptive
dead time control operates as follows. The high side and low
side gate voltages are monitored to prevent the one turning
ON from tuning ON until the other's gate voltage is
sufficiently low (< 1 V). Built in delays also ensure that one
power MOS is completely OFF, before the other can be
turned ON. This feature helps to adjust dead time as gate
transitions change with respect to output current and
temperature.
Under Voltage Lockout (UVLO)
During the start up cycle, the UVLO disables the gate
drive holding high side and low side MOSFET gates low
until the supply voltage rail has reached a point at which the
logic circuitry can be safely activated. The SiC657 also
incorporates logic to clamp the gate drive signals to zero
when the UVLO falling edge triggers the shutdown of the
device.
S19-0327-Rev. A, 08-Apr-2019
Document Number: 70090
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FUNCTIONAL BLOCK DIAGRAM
BOOT
V IN
VDRV
VCIN
UVLO
ZCD_EN#
VCIN
PWM
PWM logic
control &
state
machine
Anti-cross
conduction
control
logic
+
GL
PHASE
VSWH
+
VDRV
CGND
GL
PGND
Fig. 3 - Functional Block Diagram
DEVICE TRUTH TABLE
ZCD_EN#
PWM
GH
Tri-state
X
L
L
L
L
H, IL > 0 A
L, IL < 0 A
L
H
H
L
L
Tri-state
L
L
L
GL
H
L
L
H
H
H
H
L
H
Tri-state
L
L
S19-0327-Rev. A, 08-Apr-2019
Document Number: 70090
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PWM TIMING DIAGRAM
VTH_PWM_R
VTH_TRI_F
VTH_TRI_R
VTH_PWM_F
PWM
t PD_OFF_GL
t TSHO
GL
t PD_ON_GL
t PD_TRI_R
t TSHO
t PD_ON_GH
t PD_OFF_GH
t PD_TRI_R
GH
Fig. 4 - Definition of PWM Logic and Tri-state
ZCD_EN# - PS4 EXIT TIMING
5V
PWM
tPS4EXIT
VSWH
5V
ZCD_EN#
2.5 V
Fig. 5 - ZCD_EN# - PS4 Exit Timing
S19-0327-Rev. A, 08-Apr-2019
Document Number: 70090
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ELECTRICAL CHARACTERISTICS
Test condition: VIN = 13 V (unless otherwise stated), VDRV = VCIN = 5 V, ZCD_EN# = 5 V, VOUT = 1 V, LOUT = 250 nH (DCR = 0.32 m), TA = 25 °C,
natural convection cooling (All power loss and normalized power loss curves show SiC657 losses only unless otherwise stated)
94
60
90
55
50
500 kHz
750 kHz
82
Output Current, IOUT (A)
Efficiency (%)
86
1 MHz
78
74
70
500 kHz
40
1 MHz
35
30
25
Complete converter efficiency
PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)]
POUT = VOUT x IOUT, measured at output capacitor
66
45
20
15
62
0
5
10
15 20 25 30 35
Output Current, IOUT (A)
40
45
0
50
15
30
45 60 75 90 105 120 135 150
PCB Temperature, TPCB (°C)
Fig. 9 - Safe Operating Area (VIN = 12.6 V)
Fig. 6 - Efficiency vs. Output Current (VIN = 12.6 V)
16.0
5.0
4.5
14.0
4.0
12.0
Power Loss, PL (W)
Power Loss, PL (W)
IOUT = 25 A
3.5
3.0
2.5
1 MHz
10.0
8.0
750 kHz
6.0
2.0
4.0
1.5
2.0
500 kHz
0.0
1.0
200
300
0
400 500 600 700 800 900 1000 1100
Switching Frequency, fS (kHz)
Fig. 7 - Power Loss vs. Switching Frequency (VIN = 12.6 V)
10
15 20 25 30 35
Output Current, IOUT (A)
40
45
50
Fig. 10 - Power Loss vs. Output Current (VIN = 12.6 V)
98
94
500 kHz
500 kHz
94
90
90
Efficiency (%)
86
86
Efficiency (%)
5
750 kHz
82
1 MHz
78
82
750 kHz
78
1 MHz
74
74
70
70
Complete converter efficiency
PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)]
POUT = VOUT x IOUT, measured at output capacitor
66
Complete converter efficiency
PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)]
POUT = VOUT x IOUT, measured at output capacitor
66
62
62
0
5
10
15 20 25 30 35
Output Current, IOUT (A)
40
45
50
Fig. 8 - Efficiency vs. Output Current (VIN = 9 V)
S19-0327-Rev. A, 08-Apr-2019
0
5
10
15 20 25 30 35
Output Current, IOUT (A)
40
45
50
Fig. 11 - Efficiency vs. Output Current (VIN = 19 V)
Document Number: 70090
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ELECTRICAL CHARACTERISTICS
4.2
0.80
4.0
0.75
BOOT Diode Forward Voltage, VF (V)
Control Logic Supply Voltage, VCIN (V)
Test condition: VIN = 13 V (unless otherwise stated), VDRV = VCIN = 5 V, ZCD_EN# = 5 V, VOUT = 1 V, LOUT = 250 nH (DCR = 0.32 m), TA = 25 °C,
natural convection cooling (All power loss and normalized power loss curves show SiC657 losses only unless otherwise stated)
3.8
3.6
VUVLO_RISING
3.4
3.2
VUVLO_FALLING
3.0
2.8
2.6
0
20
40
60
80
0.55
0.50
0.45
-60 -40 -20
0
40
60
80
100 120 140
Temperature (°C)
Fig. 12 - UVLO Threshold vs. Temperature
Fig. 15 - BOOT Diode Forward Voltage vs. Temperature
4.8
VTH_PWM_R
3.6
VTRI_TH_F
3.0
VTRI
1.8
VTRI_TH_R
1.2
VTH_PWM_F
0.6
0.0
4.2
VTH_ZCD_EN#_R
3.6
3.0
VTRI_ZCD_EN#_F
2.4
VTRI_ZCD_EN#_R
1.8
1.2
VTH_ZCD_EN#_F
0.6
0.0
-60 -40 -20
0
20
40
60
80
100 120 140
-60 -40 -20
0
Temperature (°C)
Fig. 13 - PWM Threshold vs. Temperature
20 40 60 80
Temperature (°C)
100 120 140
Fig. 16 - ZCD_EN# Threshold vs. Temperature
1.8
6.0
5.5
1.6
PS4 Mode Current, IVDRV & IVCIN (uA)
Normalized PS4 Exit Latency, tPS4EXIT
20
Temperature (°C)
ZCD_EN# Threshold Voltage, VZCD_EN# (V)
PWM Threshold Voltage, VPWM (V)
0.60
100 120 140
4.8
2.4
0.65
0.40
-60 -40 -20
4.2
IF = 2 mA
0.70
1.4
1.2
1.0
0.8
0.6
0.4
0.2
VPWM = VZCD_EN # = FLOAT
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
-60 -40 -20
0
20
40
60
80
100 120 140
-60 -40 -20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
Fig. 14 - PS4 Exit Latency vs. Temperature
Fig. 17 - PS4 Mode Current vs. Temperature
S19-0327-Rev. A, 08-Apr-2019
Document Number: 70090
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Vishay Siliconix
PCB LAYOUT RECOMMENDATIONS
Step 1: VIN/GND Planes and Decoupling
Step 3: VCIN/VDRV Input Filter
VSWH
P
G
N
D
PGND
CVDRV
CVCIN
VIN
CGND
VIN plane
PGND plane
1. Layout VIN and PGND planes as shown above
2. Ceramic capacitors should be placed directly between
VIN and PGND, and close to the device for best
decoupling effect
3. Different values / packages of ceramic capacitors should
be used to cover entire decoupling spectrum e.g. 1210,
0805, 0603 and 0402
4. Smaller capacitance values, closer to device VIN pin(s),
- results in better high frequency noise absorbing
Step 2: VSWH Plane
1. The VCIN/VDRV input filter ceramic capacitors should be
placed close to IC. It is recommended to connect two
caps separately
2. VCIN capacitor should be placed between pin 3 (VCIN)
and pin 4 (CGND of driver IC) to achieve best noise
filtering
3. VDRV capacitor should be placed between pin 28 (PGND
of driver IC) and pin 29 (VDRV) to provide maximum
instantaneous driver current for low side MOSFET during
switching cycle
4. It is recommended to use a large plane analog ground,
CGND, plane to reduce parasitic inductance
VVSWH
SWH
Step 4: BOOT Resistor and Capacitor Placement
Snubber
Cboot
Rboot
PPGND
Plane
GND plane
1. Connect output inductor to DrMOS with large plane to
lower resistance
2. If a snubber network is required, place the components
as shown above, the network can be placed at bottom
1. The components should be placed close to IC, directly
between PHASE (pin 7) and BOOT (pin 5)
2. To reduce parasitic inductance, chip size 0402 can be
used
S19-0327-Rev. A, 08-Apr-2019
Document Number: 70090
10
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC657
www.vishay.com
Vishay Siliconix
Step 6: Adding Thermal Relief Vias
Step 5: Signal Routing
CGND
CGND
VSWH
CGND
PGND
VIN
PGND
plane
PGND
VIN plane
1. Route the PWM / ZCD_EN# signal traces out of the top
left corner, next to DrMOS pin 1
2. PWM is an important signal, both signal and return
traces should not cross any power nodes on any layer
3. It is best to “shield” traces form power switching nodes,
e.g. VSWH, to improve signal integrity
4. GL (pin 27) has been connected with GL pad internally
and does not need to connect externally
1. Thermal relief vias can be added on the VIN and PGND
pads to utilize inner layers for high current and thermal
dissipation
2. To achieve better thermal performance, additional vias
can be added to VIN and PGND planes
3. VSWH pad is a noise source and not recommended to put
vias on this plane
4. 8 mil vias for pads and 10 mils vias for planes are the
optimal via sizes. Vias on pads may drain solder during
assembly and cause assembly issue. Please consult
with the assembly house for guideline
Step 7: Ground Connection
CGND
VSWH
PGND
1. It is recommended to make a single connection between
CGND and PGND, this connection can be done on top layer
2. It is recommended to make the entire first inner layer (next to
top layer) a ground plane and separate it into CGND and PGND
plane
3. These ground planes provide shielding between noise
sources on top layer and signal traces on bottom layer
S19-0327-Rev. A, 08-Apr-2019
Document Number: 70090
11
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC657
www.vishay.com
Vishay Siliconix
Multi-Phases VRPower PCB Layout
The following is an example of 6 phase layout. As can be seen, all the VRPower stages are lined in X-direction compactly with
decoupling capacitors next to them. The inductors are placed as close as possible to the SiC657 to minimize the PCB copper
loss. Vias are applied on all PADs (VIN, PGND, CGND) of the SiC657 to ensure that both electrical and thermal performance are
optimized. Large copper planes are used for all high current loops, such as VIN, VSWH, VOUT and PGND. These copper planes are
duplicated in other layers to minimize the inductance and resistance. All the control signals are routed from the SiC657 to a
controller placed to the north of the power stage through inner layers to avoid the overlap of high current loops. This achieves
a compact design with the output from the inductors feeding a load located to the south of the design as shown in the figure.
VIN
PGND
VOUT
Fig. 18 - Multi - Phase VRPower Layout Top View
VIN
PGND
VOUT
Fig. 19 - Multi - Phase VRPower Layout Bottom View
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?70090
S19-0327-Rev. A, 08-Apr-2019
Document Number: 70090
12
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Legal Disclaimer Notice
www.vishay.com
Vishay
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Revision: 01-Jan-2023
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Document Number: 91000
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