SiC788, SiC788A
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Vishay Siliconix
50 A VRPower® Integrated Power Stage
DESCRIPTION
FEATURES
The SiC788 and SiC788A are integrated power stage
solutions optimized for synchronous buck applications to
offer high current, high efficiency, and high power
density performance. Packaged in Vishay’s proprietary
6 mm x 6 mm MLP package, SiC788 and SiC788A enable
voltage regulator designs to deliver up to 50 A continuous
current per phase.
• Thermally enhanced PowerPAK® MLP66-40L
package
• Vishay’s Gen IV MOSFET technology and a
low-side MOSFET with integrated Schottky
diode
• Delivers up to 50 A continuous current
• 95 % peak efficiency
• High frequency operation up to 1.5 MHz
• Power MOSFETs optimized for 12 V input stage
• 3.3 V (SiC788A) and 5 V (SiC788) PWM logic with tri-state
and hold-off
• SMOD# logic for light load efficiency improvement
The
internal
power
MOSFETs
utilize
Vishay’s
state-of-the-art Gen IV TrenchFET® technology that delivers
industry benchmark performance to significantly reduce
switching and conduction losses.
The SiC788 and SiC788A incorporate an advanced
MOSFET gate driver IC that features high current driving
capability, adaptive dead-time control, an integrated
bootstrap Schottky diode, a thermal warning (THWn) that
alerts the system of excessive junction temperature, and
skip mode (SMOD#) to improve light load efficiency. The
drivers are also compatible with a wide range of PWM
controllers and supports tri-state PWM, 3.3 V (SiC788A)
and5 V (SiC788) PWM logic.
• Low PWM propagation delay (< 20 ns)
• Thermal monitor flag
• Faster enable / disable
• Under voltage lockout for VCIN
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
• Multi-phase VRDs for CPU, GPU, and memory
TYPICAL APPLICATION DIAGRAM
5V
VIN
V IN
GH
VDRV
BOOT
PHASE
VCIN
SMOD#
PWM
controller
DSBL#
PWM
VSWH
VOUT
Gate
driver
THWn
PGND
GL
C GND
Fig. 1 - SiC788 and SiC788A Typical Application Diagram
S20-0486-Rev. D, 29-Jun-2020
Document Number: 62985
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39 DSBL#
40 PWM
38 THWn
37 CGND
35 VSWH
36 GL
33 VSWH
34 VSWH
31 VSWH
32 VSWH
31 VSWH
32 VSWH
33 VSWH
34 VSWH
35 VSWH
36 GL
38 THWn
37 CGND
39 DSBL#
40 PWM
PINOUT CONFIGURATION
30 VSWH
VSWH 30
29 VSWH
VSWH 29
28 PGND
PGND 28
27 PGND
PGND 27
26 PGND
PGND 26
25 PGND
PGND 25
24 PGND
PGND 24
23 PGND
PGND 23
VIN 9
22 PGND
PGND 22
9 VIN
VIN 10
21 PGND
PGND 21
10 VIN
7 PHASE
42
VIN
Top view
8 VIN
VIN 11
PGND 20
PGND 19
PGND 18
PGND 17
PGND 16
VSWH 15
VIN 14
VIN 13
VIN 11
VIN 12
42
VIN
VIN 8
6 GH
VIN 12
PHASE 7
5 CGND
43
VSWH
VIN 13
GH 6
VIN 14
43
VSWH
PGND 16
CGND 5
3 VDRV
4 BOOT
VSWH 15
BOOT 4
PGND 17
VDRV 3
2 VCIN
41
CGND
PGND 18
41
CGND
1 SMOD#
PGND 19
VCIN 2
PGND 20
SMOD# 1
Bottom view
Fig. 2 - SiC788 and SiC788A Pin Configuration
PIN DESCRIPTION
PIN NUMBER
NAME
1
SMOD#
Low-side gate turn-off logic. Active low
FUNCTION
2
VCIN
Supply voltage for internal logic circuitry
3
VDRV
Supply voltage for internal gate driver
4
BOOT
High-side driver bootstrap voltage
5, 37, 41
CGND
Analog ground for the driver IC
6
GH
7
PHASE
High-side gate signal
8 to 14, 42
VIN
15, 29 to 35, 43
VSWH
Switch node of the power stage
16 to 28
PGND
Power ground
36
GL
38
THWn
39
DSBL#
40
PWM
Return path of high-side gate driver
Power stage input voltage. Drain of high side MOSFET
Low-side gate signal
Thermal warning open drain output
Disable pin. Active low
PWM control input
ORDERING INFORMATION
PART NUMBER
SiC788ACD-T1-GE3
SiC788CD-T1-GE3
SiC788ADB and SiC788DB
S20-0486-Rev. D, 29-Jun-2020
PACKAGE
PowerPAK® MLP66-40L
MARKING CODE
OPTION
SiC788A
3.3 V PWM optimized
SiC788
5 V PWM optimized
Reference board
Document Number: 62985
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ABSOLUTE MAXIMUM RATINGS
ELECTRICAL PARAMETER
CONDITIONS
LIMIT
VIN
-0.3 to +25
Control logic supply voltage
VCIN
-0.3 to +7
Drive supply voltage
VDRV
Input voltage
Switch node (DC voltage)
-0.3 to +7
-0.3 to +25
VSWH
Switch node (AC voltage) (1)
BOOT voltage (DC voltage)
-8 to +30
BOOT to PHASE (DC voltage)
38
-0.3 to +7
VBOOT- PHASE
BOOT to PHASE (AC voltage) (3)
-0.3 to +8
All logic inputs and outputs
(PWM, DSBL#, and THWn)
-0.3 to VCIN + 0.3
fS = 300 kHz, VIN = 12 V, VOUT = 1.8 V
50
fS = 1 MHz, VIN = 12 V, VOUT = 1.8 V
40
TJ
150
Ambient temperature
TA
-40 to +125
Storage temperature
Tstg
-65 to +150
Human body model, JESD22-A114
5000
Charged device model, JESD22-C101
1000
Output current, IOUT(AV) (4)
Max. operating junction temperature
Electrostatic discharge protection
V
32
VBOOT
BOOT voltage (AC voltage) (2)
UNIT
A
°C
V
Notes
(1) The specification values indicated “AC” is V
SWH to PGND, -8 V (< 20 ns, 10 μJ), min. and 30 V (< 50 ns), max.
(2) The specification value indicates “AC voltage” is V
BOOT to PGND, 36 V (< 50 ns) max.
(3) The specification value indicates “AC voltage” is V
BOOT to VPHASE, 8 V (< 20 ns) max.
(4) Output current rated with testing evaluation board at T = 25 °C with natural convection cooling. The rating is limited by the peak evaluation
A
board temperature, TJ = 150 °C, and varies depending on the operating conditions and PCB layout. This rating may be changed with different
application settings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
ELECTRICAL PARAMETER
Input voltage (VIN)
MINIMUM
TYPICAL
MAXIMUM
4.5
-
18
Drive supply voltage (VDRV)
4.5
5
5.5
Control logic supply voltage (VCIN)
4.5
5
5.5
BOOT to PHASE (VBOOT-PHASE, DC voltage)
4
4.5
5.5
Thermal resistance from junction to PAD
-
1
-
Thermal resistance from junction to case
-
2.5
-
S20-0486-Rev. D, 29-Jun-2020
UNIT
V
°C/W
Document Number: 62985
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ELECTRICAL SPECIFICATIONS
(DSBL# = SMOD# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 °C)
PARAMETER
SYMBOL
TEST CONDITION
MIN.
LIMITS
TYP.
MAX.
-
85
290
295
9
30
30
55
15
-
UNIT
POWER SUPPLY
Control logic supply current
IVCIN
Drive supply current
IVDRV
BOOTSTRAP SUPPLY
Bootstrap diode forward voltage
PWM CONTROL INPUT (SiC788)
Rising threshold
Falling threshold
Tri-state voltage
Tri-state rising threshold
Tri-state falling threshold
Tri-state rising threshold hysteresis
Tri-state falling threshold hysteresis
PWM input current
PWM CONTROL INPUT (SiC788A)
Rising threshold
Falling threshold
Tri-state voltage
Tri-state rising threshold
Tri-state falling threshold
Tri-state rising threshold hysteresis
Tri-state falling threshold hysteresis
PWM input current
TIMING SPECIFICATIONS
Tri-State to GH/GL rising
propagation delay
Tri-state hold-off time
GH - turn off propagation delay
GH - turn on propagation delay
(dead time rising)
GL - turn off propagation delay
GL - turn on propagation delay
(dead time falling)
DSBL# low to GH/GL falling
propagation delay
DSBL# high to GH/GL rising
propagation delay
PWM minimum on-time
DSBL# SMOD# INPUT
DSBL# logic input voltage
SMOD# logic input voltage
VF
VTH_PWM_R
VTH_PWM_F
VTRI
VTRI_TH_R
VTRI_TH_F
VHYS_TRI_R
VHYS_TRI_F
VDSBL# = 0 V, no switching, VPWM = FLOAT
VDSBL# = 5 V, no switching, VPWM = FLOAT
VDSBL# = 5 V, fS = 300 kHz, D = 0.1
fS = 300 kHz, D = 0.1
fS = 1 MHz, D = 0.1
VDSBL# = 0 V, no switching
VDSBL# = 5 V, no switching
IF = 2 mA
0.4
3.4
0.72
0.9
3.1
-
3.7
0.9
2.3
1.15
3.35
225
325
-
4.0
1.1
1.38
3.6
350
-350
2.2
0.72
0.9
1.95
-
2.45
0.9
1.8
1.15
2.2
225
275
-
2.7
1.1
1.38
2.45
225
-225
tPD_TRI_R
-
30
-
tTSHO
tPD_OFF_GH
-
130
18
-
-
15
-
tPD_OFF_GL
-
12
-
tPD_ON_GL
-
8
-
IPWM
VTH_PWM_R
VTH_PWM_F
VTRI
VTRI_TH_R
VTRI_TH_F
VHYS_TRI_R
VHYS_TRI_F
IPWM
tPD_ON_GH
VPWM = FLOAT
VPWM = 5 V
VPWM = 0 V
VPWM = FLOAT
VPWM = 3.3 V
VPWM = 0 V
No load, see fig. 4
tPD_DSBL#_F
Fig. 5
-
15
-
tPD_DSBL#_R
Fig. 5
-
20
-
30
-
-
tPWM_ON_MIN
VIH_DSBL#
VIL_DSBL#
VIH_SMOD#
VIL_SMOD#
Input logic high
Input logic low
Input logic high
Input logic low
2
2
-
-
0.8
0.8
VUVLO
VCIN rising, on threshold
VCIN falling, off threshold
2.7
-
3.7
3.1
575
160
135
25
0.02
4.1
-
μA
mA
μA
V
V
mV
μA
V
mV
μA
ns
V
PROTECTION
Under voltage lockout
Under voltage lockout hysteresis
VUVLO_HYST
THWn flag set (2)
TTHWn_SET
THWn flag clear (2)
TTHWn_CLEAR
THWn flag hysteresis (2)
TTHWn_HYST
THWn output low
VOL_THWn
ITHWn = 2 mA
Notes
(1) Typical limits are established by characterization and are not production tested
(2) Guaranteed by design
S20-0486-Rev. D, 29-Jun-2020
V
mV
°C
V
Document Number: 62985
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DETAILED OPERATIONAL DESCRIPTION
PWM Input with Tri-state Function
Thermal Shutdown Warning (THWn)
The PWM input receives the PWM control signal from the VR
controller IC. The PWM input is designed to be compatible
with standard controllers using two state logic (H and L) and
advanced controllers that incorporate tri-state logic (H, L
and tri-state) on the PWM output. For two state logic, the
PWM input operates as follows. When PWM is driven above
VPWM_TH_R the low-side is turned off and the high-side is
turned on. When PWM input is driven below VPWM_TH_F the
high-side is turned off and the low-side is turned on. For
tri-state logic, the PWM input operates as previously stated
for driving the MOSFETs when PWM is logic high and logic
low. However, there is a third state that is entered as the
PWM output of tri-state compatible controller enters its high
impedance state during shutdown. The high impedance
state of the controller’s PWM output allows the SiC788 and
SiC788A to pull the PWM input into the tri-state region (see
definition of PWM logic and tri-state, Fig. 4). If the PWM
input stays in this region for the tri-state hold-off period,
tTSHO, both high-side and low-side MOSFETs are turned off.
The function allows the VR phase to be disabled without
negative output voltage swing caused by inductor ringing
and saves a Schottky diode clamp. The PWM and tri-state
regions are separated by hysteresis to prevent false
triggering. The SiC788A incorporates PWM voltage
thresholds that are compatible with 3.3 V logic and the
SiC788 thresholds are compatible with 5 V logic.
The THWn pin is an open drain signal that flags the presence
of excessive junction temperature. Connect, with a
maximum of 20 k, to VCIN. An internal temperature sensor
detects the junction temperature. The temperature
threshold is 160 °C. When this junction temperature is
exceeded the THWn flag is set. When the junction
temperature drops below 135 °C the device will clear the
THWn signal. The SiC788 and SiC788A do not stop
operation when the flag is set. The decision to shutdown
must be made by an external thermal control function.
Disable (DSBL#)
PGND (power ground) should be externally connected to
CGND (control signal ground). The layout of the printed circuit
board should be such that the inductance separating CGND
and PGND is minimized. Transient differences due to
inductance effects between these two pins should not
exceed 0.5 V
In the low state, the DSBL# pin shuts down the driver IC and
disables both high-side and low-side MOSFETs. In this
state, standby current is minimized. If DSBL# is left
unconnected, an internal pull-down resistor will pull the pin
to CGND and shut down the IC.
Pre-Charger Function
When DSBL# is driven from below VIL_DSBL# to above
VIH_DSBL# the low-side is turned on for a short duration (60
ns typical) to refresh the BOOT capacitor in case it has been
discharged due to the driver being in standby for a long
period of time.
Diode Emulation Mode (SMOD#)
When SMOD# is logic low diode emulation mode is enabled
and the low-side is turned off. This is a non-synchronous
conversion mode that improves light load efficiency by
reducing switching losses. Conducted losses that occur in
synchronous buck regulators when inductor current is
negative can also be reduced. Circuitry in the external
controller IC detects when inductor current crosses zero
and drives SMOD# below VIL_SMOD# turning the low-side
MOSFET off. The function can be also be used for a
pre-biased output voltage. If SMOD# is left unconnected, an
internal pull up resistor will pull the pin to VCIN (logic high) to
disable the SMOD# function.
S20-0486-Rev. D, 29-Jun-2020
Voltage Input (VIN)
This is the power input to the drain of the high-side power
MOSFET. This pin is connected to the high power
intermediate BUS rail.
Switch Node (VSWH and PHASE)
The switch node, VSWH, is the circuit power stage output.
This is the output applied to the power inductor and output
filter to deliver the output for the buck converter. The PHASE
pin is internally connected to the switch node, VSWH. This pin
is to be used exclusively as the return pin for the BOOT
capacitor. A 20 k resistor is connected between GH and
PHASE to provide a discharge path for the HS MOSFET in
the event that VCIN goes to zero while VIN is still applied.
Ground Connections (CGND and PGND)
Control and Drive Supply Voltage Input (VDRV, VCIN)
VCIN is the bias supply for the gate drive control IC. VDRV is
the bias supply for the gate drivers. It is recommended to
separate these pins through a resistor. This creates a low
pass filtering effect to avoid coupling of high frequency gate
drive noise into the IC.
Bootstrap Circuit (BOOT)
The internal bootstrap diode and an external bootstrap
capacitor form a charge pump that supplies voltage to the
BOOT pin. An integrated bootstrap diode is incorporated so
that only an external capacitor is necessary to complete the
bootstrap circuit. Connect a boot strap capacitor with one
leg tied to BOOT pin and the other tied to PHASE pin.
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Shoot-Through Protection and Adaptive Dead Time
Under Voltage Lockout (UVLO)
The SiC788 and SiC788A have an internal adaptive logic to
avoid shoot through and optimize dead time. The shoot
through protection ensures that both high-side and low-side
MOSFETs are not turned on at the same time. The adaptive
dead time control operates as follows. The high-side and
low-side gate voltages are monitored to prevent the
MOSFET turning on from tuning on until the other
MOSFET’s gate voltage is sufficiently low (< 1 V). Built in
delays also ensure that one power MOSFET is completely
off, before the other can be turned ON. This feature helps to
adjust dead time as gate transitions change with respect to
output current and temperature.
During the start up cycle, the UVLO disables the gate
drive, holding high-side and low-side MOSFET gates low,
until the supply voltage rail has reached a point at which
the logic circuitry can be safely activated. The SiC788 and
SiC788A also incorporate logic to clamp the gate drive
signals to zero when the UVLO falling edge triggers the
shutdown of the device. As an added precaution, a 20 k
resistor is connected between GH and PHASE to provide a
discharge path for the HS MOSFET.
FUNCTIONAL BLOCK DIAGRAM
THWn
BOOT
GH
V IN
VDRV
Thermal monitor
& warning
V CIN
UVLO
DSBL#
VCIN
PWM logic
control &
state
machine
PWM
+
GL
Anti-cross
conduction
control
logic
20K
PHASE
Vref = 1 V
VSWH
+
Vref = 1 V
VDRV
C GND
GL
SMOD#
PGND
Fig. 3 - SiC788 and SiC788A Functional Block Diagram
DEVICE TRUTH TABLE
DSBL#
SMOD#
PWM
GH
Open
X
X
L
L
L
X
X
L
L
H
L
L
L
L
H
L
H
H
L
H
L
Tri-state
L
L
H
H
L
L
H
H
H
H
H
L
H
H
Tri-state
L
L
S20-0486-Rev. D, 29-Jun-2020
GL
Document Number: 62985
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PWM TIMING DIAGRAM
VTH_PWM_R
VTH_TRI_F
VTH_TRI_R
VTH_PWM_F
PWM
t PD_OFF_GL
t TSHO
GL
t PD_ON_GL
t PD_TRI_R
t TSHO
t PD_ON_GH
t PD_OFF_GH
t PD_TRI_R
GH
Fig. 4 - Definition of PWM Logic and Tri-State
OPERATION TIMING DIAGRAM: DSBL#
PWM
PWM
Enable
DSBL #
DSBL #
GH
GH
GL
GL
t
t
DSBL# High to GH Rising Propagation Delay
DSBL# High to GL Rising Propagation Delay
PWM
PWM
Disable
DSBL #
DSBL #
GH
GH
GL
GL
t
t
DSBL# Low to GH Falling Propagation Delay
DSBL# Low to GL Falling Propagation Delay
Fig. 5 - DSBL# Propagation Delay
S20-0486-Rev. D, 29-Jun-2020
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ELECTRICAL CHARACTERISTICS
Test condition: VIN = 12 V, VDRV = VCIN = 5 V, DSBL# = SMOD# = 5 V, VOUT = 1.8 V, LOUT = 250 nH (DCR = 0.32 m), TA = 25 °C, natural
convection cooling (All power loss and normalized power loss curves show SiC788 and SiC788A losses only unless otherwise stated)
Fig. 8 - Power Loss vs. Switching Frequency
95
500 kHz
85
10.5
1 MHz
Power Loss, PL (W)
Efficiency (%)
12.0
300 kHz
90
800 kHz
80
75
70
Complete converter efficiency
PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)]
POUT = VOUT x IOUT, measured at output capacitor
65
60
9.0
1 MHz
7.5
6.0
800 kHz
4.5
3.0
500 kHz
1.5
300 kHz
55
0
4
8
12 16 20 24 28
Output Current, IOUT (A)
32
36
40
0.0
0
4
8
12
16
20
24
28
32
36
40
36
40
Output Current, IOUT (A)
Fig. 6 - Efficiency vs. Output Current
Fig. 9 - Power Loss vs. Output Current
95
12.0
VOUT = 1 V
90
VOUT = 0.9 V
10.5
fS = 500 kHz
VOUT = 0.7 V
9.0
VOUT = 0.8 V
80
Power Loss, PL (W)
Efficiency (%)
85
75
70
65
fS = 500 kHz
7.5
VOUT = 0.7 V
VOUT = 0.8 V
VOUT = 0.9 V
VOUT = 1.0 V
6.0
4.5
3.0
60
1.5
55
0
4
8
12
16 20 24 28 32
Output Current, IOUT (A)
36
40
Fig. 7 - Efficiency vs. Output Current
0.0
0
4
8
12 16 20 24 28
Output Current, IOUT (A)
32
Fig. 10 - Power Loss vs. Output Current
1.80
Normalized Power Loss
1.65
1.50
1.35
1.20
1.05
0.90
0.75
0.60
200 300 400 500 600 700 800 900 1000 1100 1200
Switching Frequency, fS (kHz)
S20-0486-Rev. D, 29-Jun-2020
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45
3.4
300 kHz
40
Output Current, IOUT (A)
PWM Threshold Voltage, VPWM (V)
3.0
35
1 MHz
30
25
20
15
10
5
0
0
15
30
VTH_PWM_R
2.6
2.2
VTRI_TH_F
1.8
VTRI
1.4
VTRI_TH_R
1.0
VTH_PWM_F
0.6
0.2
45 60 75 90 105 120 135 150
PCB Temperature, TPCB (°C)
-60 -40 -20
0
20 40 60 80
Temperature (°C)
100 120 140
Fig. 11 - Safe Operating Area
Fig. 14 - PWM Threshold vs. Temperature (SiC788A)
1.20
0.40
0.35
1.12
BOOT Diode Forward Voltage, VF (V)
Normalized Driver Supply Current
1.16
1.08
300 kHz
1.04
1.00
1 MHz
0.96
0.92
0.88
0
4
8
12 16 20 24 28
Output Current, IOUT (A)
32
36
IF = 2 mA
0.30
0.25
0.20
0.15
0.10
0.05
0.00
40
-60 -40 -20
0
20
40
60
80
100 120 140
Temperature (°C)
Fig. 12 - Driver Supply Current vs. Output Current
Fig. 15 - BOOT Diode Forward Voltage vs. Temperature
4.2
4.8
4.2
VUVLO_RISING
3.8
PWM Threshold Voltage, VPWM (V)
Control Logic Supply Voltage, VCIN (V)
4.0
3.6
3.4
3.2
3.0
VUVLO_FALLING
2.8
VTH_PWM_R
3.6
VTRI_TH_F
3.0
2.4
VTRI
1.8
VTRI_TH_R
1.2
0.6
VTH_PWM_F
2.6
-60 -40 -20
0
20 40 60 80
Temperature (°C)
100 120 140
0.0
-60 -40 -20
0
20
40
60
80
100 120 140
Temperature (°C)
Fig. 13 - UVLO Threshold vs. Temperature
Fig. 16 - PWM Threshold vs. Temperature (SiC788)
S20-0486-Rev. D, 29-Jun-2020
Document Number: 62985
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4.8
2.8
VTH_PWM_R
PWM Threshold Voltage, VPWM (V)
PWM Threshold Voltage, VPWM (V)
3.2
2.4
VTRI_TH_F
2.0
VTRI
1.6
VTRI_TH_R
1.2
0.8
VTH_PWM_F
VTRI
1.8
VTRI_TH_R
1.2
0.0
4.7 4.8 4.9 5.0 5.1 5.2 5.3
Driver Supply Voltage, VCIN (V)
5.4
2.0
2.0
1.6
1.4
1.2
1.0
VIL_DSBL#
0.8
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
Fig. 20 - PWM Threshold vs. Driver Supply Voltage (SiC788)
2.2
VIH_DSBL#
4.6
Driver Supply Voltage, VCIN (V)
2.2
1.8
VTH_PWM_F
4.5
5.5
DSBL# Threshold Voltage, VDSBL# (V)
DSBL# Threshold Voltage, VDSBL# (V)
2.4
0.0
4.6
VTRI_TH_F
3.0
0.6
Fig. 17 - PWM Threshold vs. Driver Supply Voltage (SiC788A)
0.6
1.8
VIH_DSBL#
1.6
1.4
VIL_DSBL#
1.2
1.0
0.8
0.6
-60 -40 -20
0
20
40
60
80
100 120 140
Temperature (°C)
4.5
4.7 4.8 4.9 5.0 5.1 5.2 5.3
Driver Supply Voltage, VCIN (V)
Fig. 18 - DSBL# Threshold vs. Temperature
Fig. 21 - DSBL# Threshold vs. Driver Supply Voltage
2.2
2.2
2.0
2.0
SMOD# Threshold Voltage, VSMOD# (V)
SMOD# Threshold Voltage, VSMOD# (V)
3.6
0.4
4.5
VTH_PWM_R
4.2
1.8
VIH_SMOD#
1.6
1.4
1.2
1.0
VIL_SMOD#
0.8
4.6
5.4
5.5
1.8
VIH_SMOD#
1.6
1.4
VIL_SMOD#
1.2
1.0
0.8
0.6
0.6
-60 -40 -20
0
20
40
60
80
100 120 140
Temperature (°C)
Fig. 19 - SMOD# Threshold vs. Temperature
S20-0486-Rev. D, 29-Jun-2020
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
Driver Supply Voltage, VCIN (V)
Fig. 22 - SMOD# Threshold vs. Driver Supply Voltage
Document Number: 62985
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SiC788, SiC788A
Vishay Siliconix
12.0
430
11.5
410
Driver Supply Current, IVDVR & IVCIN (V)
DSBL# Pull-Down Current, IDSBL# (uA)
www.vishay.com
11.0
10.5
10.0
9.5
9.0
8.5
8.0
-60 -40 -20
0
20 40 60 80
Temperature (°C)
100 120 140
VPWM = FLOAT
390
370
350
330
310
290
270
-60 -40 -20
0
20
40
60
80
100 120 140
Temperature (°C)
Fig. 23 - DSBL# Pull-down Current vs. Temperature
Fig. 26 - Driver Quiescent Current vs. Temperature
Driver Supply Current, IVDVR & IVCIN (V)
200
180
VDSBL# = 0 V
160
140
120
100
80
60
40
-60 -40 -20
0
20 40 60 80
Temperature (°C)
100 120 140
Fig. 24 - Driver Quiescent Current vs. Temperature
SMOD# Pull-Up Current, ISMOD# (uA)
-8.0
-8.5
VSMOD# = 0 V
-9.0
-9.5
-10.0
-10.5
-11.0
-11.5
-12.0
-60 -40 -20
0
20 40 60 80
Temperature (°C)
100 120 140
Fig. 25 - SMOD# Pull-up Current vs. Temperature
S20-0486-Rev. D, 29-Jun-2020
Document Number: 62985
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SiC788, SiC788A
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Vishay Siliconix
PCB LAYOUT RECOMMENDATIONS
Step 1: VIN / PGND Planes and Decoupling
Step 3: VCIN / VDRV Input Filter
V IN Plane
Vias for ground connection
PGND
V IN
CGND
Cvdrv
CGND
Cvcin
V SWH
PGND Plane
1. Layout VIN and PGND planes as shown above
2. Ceramic capacitors should be placed directly between
VIN and PGND, and as close as possible to IC for best
decoupling effect
3. Different ceramic capacitor values and packages should
be used to cover entire decoupling spectrum, e.g. 1210,
0805, 0603, and 0402
4. Smaller capacitance values, placed closer to the IC’s VIN
pin(s), result in better high frequency noise absorbing
Step 2: VSWH Plane
1. VCIN / VDRV input filter ceramic capacitors should be
placed as close as possible to IC. It is recommended to
connect two capacitors separately
2. VCIN capacitor should be placed between pin 2 and
pin 37 (CGND of driver IC) to achieve best noise filtering
3. VDRV capacitor should be placed between pin 3 and
PGND to provide maximum instantaneous driver current
for low-side MOSFET during switching cycle. PGND can
be connected to inner ground plane through vias, as
shown above
4. Pin 5 and pin 37 should be connected with CGND pad, as
shown above
5. For connecting VCIN to CGND, it is recommended to use
a large plane to reduce parasitic inductance
Step 4: BOOT Resistor and Capacitor Placement
CGND
Snubber
V SWH
PGND Plane
1. Connect output inductor to IC with large plane to lower
resistance
2. VSWH plane also serves as a heat-sink for low-side
MOSFET. Please make the plane wide and short to
achieve best thermal path
3. If a snubber network is required, place components as
shown above
1. The components need to be placed as close as possible
to IC, directly between PHASE (pin 7) and BOOT (pin 4)
2. To reduce parasitic inductance, 0402 package size can
be used
S20-0486-Rev. D, 29-Jun-2020
Document Number: 62985
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SiC788, SiC788A
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Vishay Siliconix
Step 5: Signal Routing
Step 7: Ground Connection
CGND
CGND
CGND
GND Plane
PGND
1. Route the PWM, SMOD#, DSBL#, and THWn signal
traces out of the top right corner, next to pin 1
1. It is recommended to make the entire first inner layer
(below top layer) the ground plane
2. The PWM signal is a very important signal, both signal
and return traces should not cross any power nodes on
any layer
2. The ground plane provides analog ground and power
ground connections
3. It is best to “shield” these traces from power switching
nodes, e.g. VSWH, with a GND island to improve signal
integrity
Step 6: Adding Thermal Relief Vias
V IN Plane
V IN
CGND
V SWH
PGND Plane
1. Thermal relief vias can be added to the VIN and CGND
pads to utilize inner layers for high-current and thermal
dissipation
2. To achieve better thermal performance, additional vias
can be added to VIN and PGND planes
3. The VSWH pad is a noise source and it is not
recommended to place vias on this pad
4. 8 mil vias for pads and 10 mils vias for planes are the
optimal sizes. Vias on pad may drain solder during
assembly and cause assembly issues. Please consult
with the assembly house for guidelines
S20-0486-Rev. D, 29-Jun-2020
3. The ground plane provides shielding between noise
source on top layer and signal traces on bottom layer
Document Number: 62985
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SiC788, SiC788A
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Vishay Siliconix
PRODUCT SUMMARY
Part number
SiC788
SiC788A
Description
50 A power stage, 4.5 VIN to 18 VIN, 5 V PWM with
diode emulation mode
50 A power stage, 4.5 VIN to 18 VIN, 3.3 V PWM
with diode emulation mode
Input voltage min. (V)
4.5
4.5
Input voltage max. (V)
18
18
Continuous current rating max. (A)
50
50
Switch frequency max. (kHz)
1000
1000
Enable (yes / no)
Yes
Yes
-
-
Monitoring features
Protection
Light load mode
Pulse-width modulation (V)
Package type
Package size (W, L, H) (mm)
UVLO, THDN
UVLO, THDN
Diode emulation
Diode emulation
5
3.3
PowerPAK MLP66-40L
PowerPAK MLP66-40L
6.0 x 6.0 x 0.75
6.0 x 6.0 x 0.75
Status code
2
2
Product type
VRPower (DrMOS)
VRPower (DrMOS)
Applications
Computer, industrial, networking
Computer, industrial, networking
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62985.
S20-0486-Rev. D, 29-Jun-2020
Document Number: 62985
14
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
PowerPAK® MLP66-40 Case Outline
2x
5 6
Pin 1 dot
by marking
K1
0.08 C
A
0.10 C A
D
A
K2
A1
D2-1
0.41
A2
31
40
2x
30
1
21
10
E2-3
E2-1
4
E
0.10 M C A B
MLP66-40
(6 mm x 6 mm)
(Nd-1)X e
ref.
E2-2
e
0.10 C B
B
20
D2-2
D2-3
11
C
(Nd-1)X e
ref.
Top View
DIM.
Bottom View
Side View
MILLIMETERS
INCHES
MIN.
NOM.
MAX.
MIN.
NOM.
A (8)
0.70
0.75
0.80
0.027
0.029
0.031
A1
0.00
-
0.05
0.000
-
0.002
0.30
0.078
A2
b (4)
0.20 ref.
0.20
0.25
0.008 ref.
0.098
D
6.00 BSC
0.236 BSC
e
0.50 BSC
0.019 BSC
E
6.00 BSC
0.236 BSC
L
0.35
0.40
MAX.
0.45
0.013
0.015
N (3)
40
40
Nd (3)
10
10
Ne (3)
10
0.011
0.017
10
D2-1
1.45
1.50
1.55
0.057
0.059
0.061
D2-2
1.45
1.50
1.55
0.057
0.059
0.061
D2-3
2.35
2.40
2.45
0.095
0.094
0.096
E2-1
4.35
4.40
4.45
0.171
0.173
0.175
E2-2
1.95
2.00
2.05
0.076
0.078
0.080
E2-3
1.95
2.00
2.05
0.076
0.078
0.080
K1
0.73 BSC
0.028 BSC
K2
0.21 BSC
0.008 BSC
ECN: T14-0826-Rev. B, 12-Jan-15
DWG: 5986
Notes
1. Use millimeters as the primary measurement
2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994
3. N is the number of terminals. Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction
4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
6. Exact shape and size of this feature is optional
7. Package warpage max. 0.08 mm
8. Applied only for terminals
Document Number: 64846
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Revision: 12-Jan-15
PAD Pattern
www.vishay.com
Vishay Siliconix
Recommended Land Pattern PowerPAK® MLP66-40L
2.200
0.100 0.100
0.200 0.276
0.025
0.025
0.100
1
1
40
40
0.100
0.100
0.310
0.320
0.100
1.700
2.600
0.100 0.100
0.600
0.276
2.200
0.100
4.600
0.100
All Dimensions are in milimeters
Revision: 28-Feb-14
Document Number: 67964
1
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Legal Disclaimer Notice
www.vishay.com
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay's knowledge of typical
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements
about the suitability of products for a particular application. It is the customer's responsibility to validate that a particular product
with the properties described in the product specification is suitable for use in a particular application. Parameters provided in
datasheets and / or specifications may vary in different applications and performance may vary over time. All operating
parameters, including typical parameters, must be validated for each customer application by the customer's technical experts.
Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited
to the warranty expressed therein.
Hyperlinks included in this datasheet may direct users to third-party websites. These links are provided as a convenience and
for informational purposes only. Inclusion of these hyperlinks does not constitute an endorsement or an approval by Vishay of
any of the products, services or opinions of the corporation, organization or individual associated with the third-party website.
Vishay disclaims any and all liability and bears no responsibility for the accuracy, legality or content of the third-party website
or for that of subsequent links.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please
contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
© 2023 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 01-Jan-2023
1
Document Number: 91000
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