SiHA24N65EF
www.vishay.com
Vishay Siliconix
E Series Power MOSFET with Fast Body Diode
FEATURES
D
• Fast body diode MOSFET using E series
technology
• Reduced trr, Qrr, and IRRM
• Low figure-of-merit (FOM) Ron x Qg
• Low input capacitance (Ciss)
• Low switching losses due to reduced Qrr
Available
• Ultra low gate charge (Qg)
• Avalanche energy rated (UIS)
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
Thin-Lead TO-220 FULLPAK
G
GD
S
S
N-Channel MOSFET
APPLICATIONS
• Telecommunications
- Server and telecom power supplies
• Lighting
- High-intensity discharge (HID)
- Fluorescent ballast lighting
• Consumer and computing
- ATX power supplies
• Industrial
- Welding
- Battery chargers
• Renewable energy
- Solar (PV inverters)
• Switch mode power supplies (SMPS)
• Applications using the following topologies
- LCC
- Phase shifted bridge (ZVS)
- 3-level inverter
- AC/DC bridge
PRODUCT SUMMARY
VDS (V) at TJ max.
RDS(on) max. () at 25 °C
700
VGS = 10 V
Qg max. (nC)
0.156
122
Qgs (nC)
17
Qgd (nC)
36
Configuration
Single
ORDERING INFORMATION
Package
Lead (Pb)-free
Lead (Pb)-free and halogen-free
Thin-Lead TO-220 FULLPAK
SiHA24N65EF-E3
SiHA24N65EF-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-source voltage
VDS
650
Gate-source voltage
VGS
± 30
Continuous drain current (TJ = 150 °C) e
Pulsed drain
VGS at 10 V
TC = 25 °C
TC = 100 °C
current a
ID
IDM
Linear derating factor
UNIT
V
10
6
A
65
0.31
W/°C
mJ
Single pulse avalanche energy b
EAS
691
Maximum power dissipation
PD
39
W
TJ, Tstg
-55 to +150
°C
Operating junction and storage temperature range
Drain-source voltage slope
TJ = 125 °C
Reverse diode dV/dt d
Soldering recommendations (peak temperature) c
for 10 s
Mounting torque
M3 screw
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature
b. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 , IAS = 7 A
c. 1.6 mm from case
d. ISD ID, dI/dt = 900 A/μs, starting TJ = 25 °C
e. Limited by maximum junction temperature
S21-0919-Rev. E, 06-Sep-2021
dV/dt
70
50
V/ns
300
°C
0.6
Nm
Document Number: 91825
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHA24N65EF
www.vishay.com
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum junction-to-ambient
RthJA
-
65
Maximum junction-to-case (drain)
RthJC
-
3.2
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
VDS temperature coefficient
Gate-source threshold voltage (N)
VDS
VGS = 0 V, ID = 250 μA
650
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.68
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2
-
4
V
VGS = ± 20 V
-
-
± 100
nA
VGS = ± 30 V
-
-
±1
μA
VDS = 520 V, VGS = 0 V
-
-
1
VDS = 520 V, VGS = 0 V, TJ = 125 °C
-
-
500
Gate-source leakage
IGSS
Zero gate voltage drain current
IDSS
μA
-
0.13
0.156
gfs
VDS = 30 V, ID = 12 A
-
7.2
-
S
Input capacitance
Ciss
2774
-
Coss
-
128
-
Reverse transfer capacitance
Crss
VGS = 0 V,
VDS = 100 V,
f = 1 MHz
-
Output capacitance
-
4
-
Effective output capacitance, energy
related a
Co(er)
-
96
-
Effective output capacitance, time
related b
Co(tr)
-
333
-
-
81
122
-
17
-
Drain-source on-state resistance
Forward transconductance
RDS(on)
VGS = 10 V
ID = 12 A
Dynamic
pF
VDS = 0 V to 520 V, VGS = 0 V
Total gate charge
Qg
Gate-source charge
Qgs
VGS = 10 V
ID = 12 A, VDS = 520 V
Gate-drain charge
Qgd
-
36
-
Turn-on delay time
td(on)
-
24
48
Rise time
Turn-off delay time
tr
td(off)
Fall time
tf
Gate input resistance
Rg
VDD = 520 V, ID = 12 A,
VGS = 10 V, Rg = 9.1
-
34
68
-
80
120
-
46
92
f = 1 MHz, open drain
0.2
0.5
1.0
-
-
24
-
-
65
nC
ns
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
IS
Pulsed diode forward current
ISM
Diode forward voltage
VSD
Reverse recovery time
trr
Reverse recovery charge
Qrr
Reverse recovery current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 12 A, VGS = 0 V
TJ = 25 °C, IF = IS = 12 A,
dI/dt = 100 A/μs, VR = 400 V
S
-
0.9
1.2
V
-
151
288
ns
-
0.9
2.1
μC
-
13
-
A
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS
S21-0919-Rev. E, 06-Sep-2021
Document Number: 91825
2
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHA24N65EF
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
60
3
TJ = 25 °C
ID = 12 A
RDS(on), Drain-to-Source
On Resistance (Normalized)
ID, Drain-to-Source Current (A)
80
40
20
6V
2.5
2
1.5
VGS = 10 V
1
0.5
5V
0
0
5
10
15
20
25
0
- 60 - 40 - 20 0
30
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 1 - Typical Output Characteristics
10 000
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
30
20
Ciss
TJ = 150 °C
ġ
Capacitance (pF)
40
7V
6V
1000
Coss
100
ġ
ġ
Crss
10
10
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds shorted
Crss = Cgd
Coss = Cds + Cgd
ġ
5V
1
0
0
10
5
20
15
25
0
30
VDS, Drain-to-Source Voltage (V)
100
200
300
400
500
600
VDS, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 2 - Typical Output Characteristics
16
14
5000
60
12
10
Coss (pF)
ID, Drain-to-Source Current (A)
80
40
TJ = 150 °C
Coss
Eoss
8
500
Eoss (μJ)
ID, Drain-to-Source Current (A)
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
VDS, Drain-to-Source Voltage (V)
6
20
4
TJ = 25 °C
2
VDS = 28.8 V
0
0
5
10
15
20
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S21-0919-Rev. E, 06-Sep-2021
25
50
0
0
100
200
300
VDS
400
500
600
Fig. 6 - Coss and Eoss vs. VDS
Document Number: 91825
3
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHA24N65EF
www.vishay.com
Vishay Siliconix
Axis Title
12
20
16
12
8
9
1000
6
100
3
4
0
60
30
120
90
25
150
50
75
100
125
150
TC - Case Temperature (°C)
Qg, Total Gate Charge (nC)
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 10 - Maximum Drain Current vs. Case Temperature
100
850
ID = 10 mA
825
TJ = 150 °C
VDS, Drain-to-Source
Breakdown Voltage (V)
ISD, Reverse Drain Current (A)
10
0
0
TJ = 25 °C
10
ġ
1
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
VSD, Source-Drain Voltage (V)
775
750
725
700
650
- 60 - 40 - 20 0
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 8 - Typical Source-Drain Diode Forward Voltage
Operation in this area
limited by R DS(on)
800
675
VGS = 0 V
0.1
Fig. 11 - Temperature vs. Drain-to-Source Voltage
IDM limited
10
ID, Drain Current (A)
10000
1 t li
VDS = 520 V
VDS = 325 V
VDS = 130 V
2nd line
ID - Drain Current (A)
VGS, Gate-to-Source Voltage (V)
24
100 μs
Limited by RDS(on)*
1
1 ms
10 ms
0.1
TC = 25 °C
TJ = 150 °C
Single pulse
BVDSS limited
0.01
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Fig. 9 - Maximum Safe Operating Area
S21-0919-Rev. E, 06-Sep-2021
Document Number: 91825
4
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHA24N65EF
www.vishay.com
Vishay Siliconix
1
Normalized Effective Transient
Thermal Impedance
Duty cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single pulse
0.01
0.0001
0.001
0.01
0.1
1
Pulse Time (s)
Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case
RD
VDS
VDS
tp
VGS
VDD
D.U.T.
RG
+
- VDD
VDS
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
IAS
Fig. 13 - Switching Time Test Circuit
Fig. 16 - Unclamped Inductive Waveforms
VDS
QG
10 V
90 %
QGS
10 %
VGS
QGD
VG
td(on)
td(off) tf
tr
Charge
Fig. 14 - Switching Time Waveforms
Fig. 17 - Basic Gate Charge Waveform
L
Vary tp to obtain
required IAS
Current regulator
Same type as D.U.T.
VDS
50 kΩ
D.U.T
RG
+
-
IAS
12 V
0.2 µF
0.3 µF
V DD
+
D.U.T.
10 V
tp
0.01 Ω
-
VDS
VGS
3 mA
Fig. 15 - Unclamped Inductive Test Circuit
IG
ID
Current sampling resistors
S21-0919-Rev. E, 06-Sep-2021
Document Number: 91825
5
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHA24N65EF
www.vishay.com
Vishay Siliconix
Fig. 18 - Gate Charge Test Circuit
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 19 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
S21-0919-Rev. E, 06-Sep-2021
Document Number: 91825
6
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHA24N65EF
www.vishay.com
Vishay Siliconix
reliability data, see www.vishay.com/ppg?91825.
S21-0919-Rev. E, 06-Sep-2021
Document Number: 91825
7
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
TO-220 FULLPAK Thin Lead
E
ØP
A
A1
d2
d3
d1
D
L1
b2 x 3
L
bx3
c
A2
e
DIMENSIONS
SYMBOL
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
4.30
4.70
0.169
0.185
A1
2.50
2.90
0.098
0.114
A2
2.40
2.80
0.094
0.110
b
0.60
0.80
0.024
0.031
b2
0.60
0.90
0.024
0.035
c
-
0.60
-
0.024
D
8.30
8.70
0.327
0.342
d1
14.70
15.30
0.579
0.602
d2
2.90
3.10
0.114
0.122
d3
3.30
3.70
0.130
0.146
E
9.70
10.30
0.382
0.406
e
2.50
2.70
0.098
0.106
L
13.40
13.80
0.528
0.543
L1
1.00
2.80
0.039
0.110
ØP
3.00
3.40
0.118
0.134
ECN: E20-0684-Rev. D, 28-Dec-2020
DWG: 6021
Revision: 28-Dec-2020
Document Number: 62649
1
For technical questions, contact:
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Legal Disclaimer Notice
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Disclaimer
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Revision: 01-Jan-2023
1
Document Number: 91000
