SIHB120N60E-T1-GE3

SiHB120N60E www.vishay.com Vishay Siliconix E Series Power MOSFET FEATURES D • 4th generation E series technology D2PAK (TO-263) • Low figure-of-merit (FOM) Ron x Qg • Low effective capacitance (Co(er)) • Reduced switching and conduction losses G • Avalanche energy rated (UIS) • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 G D S S N-Channel MOSFET APPLICATIONS • Server and telecom power supplies PRODUCT SUMMARY • Switch mode power supplies (SMPS) VDS (V) at TJ max. RDS(on) typ. () at 25 °C 650 VGS = 10 V Qg max. (nC) 45 Qgs (nC) 10 Qgd (nC) 12 Configuration • Power factor correction power supplies (PFC) 0.104 • Lighting - High-intensity discharge (HID) - Fluorescent ballast lighting • Industrial Single - Welding - Induction heating - Motor drives - Battery chargers - Solar (PV inverters) ORDERING INFORMATION Package D2PAK (TO-263) Lead (Pb)-free and halogen-free SiHB120N60E-GE3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-source voltage VDS 600 Gate-source voltage VGS ± 30 Continuous drain current (TJ = 150 °C) VGS at 10 V TC = 25 °C TC = 100 °C Pulsed drain current a ID IDM Linear derating factor UNIT V 25 16 A 66 1.4 W/°C Single pulse avalanche energy b EAS 88 mJ Maximum power dissipation PD 179 W TJ, Tstg -55 to +150 °C Operating junction and storage temperature range Drain-source voltage slope TJ = 125 °C Reverse diode dv/dt d Soldering recommendations (peak temperature) c For 10 s dv/dt 70 50 260 V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature b. VDD = 120 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 , IAS = 2.5 A c. 1.6 mm from case d. ISD  ID, di/dt = 100 A/μs, starting TJ = 25 °C S18-1109-Rev. A, 12-Nov-2018 Document Number: 92198 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB120N60E www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum junction-to-ambient RthJA - 40 Maximum junction-to-case (drain) RthJC - 0.7 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-source breakdown voltage VDS temperature coefficient Gate-source threshold voltage (N) VDS VGS = 0 V, ID = 250 μA 600 - - V VDS/TJ Reference to 25 °C, ID = 1 mA - 0.67 - V/°C VGS(th) VDS = VGS, ID = 250 μA 3.0 - 5.0 V VGS = ± 20 V - - ± 100 nA VGS = ± 30 V - - ±1 μA VDS = 600 V, VGS = 0 V - - 1 VDS = 480 V, VGS = 0 V, TJ = 125 °C - - 10 Gate-source leakage IGSS Zero gate voltage drain current IDSS μA - 0.104 0.120  gfs VDS = 20 V, ID = 12 A - 6 - S Input capacitance Ciss 1562 - Coss - 72 - Reverse transfer capacitance Crss VGS = 0 V, VDS = 100 V, f = 1 MHz - Output capacitance - 6 - Effective output capacitance, energy related a Co(er) - 56 - Effective output capacitance, time  related b Co(tr) - 357 - Drain-source on-state resistance Forward transconductance a RDS(on) VGS = 10 V ID = 12 A Dynamic pF VDS = 0 V to 480 V, VGS = 0 V Total gate charge Qg Gate-source charge Qgs VGS = 10 V ID = 12 A, VDS = 480 V - 30 45 - 10 - Gate-drain charge Qgd - 12 - Turn-on delay time td(on) - 19 38 VDD = 480 V, ID = 12 A, VGS = 10 V, Rg = 9.1  - 65 130 - 31 62 - 33 66 f = 1 MHz, open drain 0.3 0.65 1.3 - - 25 - - 66 Rise time Turn-off delay time tr td(off) Fall time tf Gate input resistance Rg nC ns  Drain-Source Body Diode Characteristics Continuous source-drain diode current IS Pulsed diode forward current ISM Diode forward voltage VSD Reverse recovery time trr Reverse recovery charge Qrr Reverse recovery current IRRM MOSFET symbol showing the  integral reverse p - n junction diode D A G TJ = 25 °C, IS = 12 A, VGS = 0 V TJ = 25 °C, IF = IS = 12 A, di/dt = 100 A/μs, VR = 400 V S - - 1.2 V - 322 870 ns - 4.9 18.4 μC - 29 - A Notes a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS S18-1109-Rev. A, 12-Nov-2018 Document Number: 92198 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB120N60E www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 3.0 TOP 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V 60 ID = 12 A TJ = 25 °C RDS(on), Drain-to-Source On-Resistance (Normalized) 40 20 0 5 10 15 VDS, Drain-to-Source Voltage (V) 1.5 1.0 VGS = 10 V 0.5 -60 -40 -20 20 Fig. 1 - Typical Output Characteristics 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 4 - Normalized On-Resistance vs. Temperature 100 000 48 TOP 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V 36 VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds shorted Crss = Cgd Coss = Cds + Cgd TJ = 150 °C 10 000 Ciss C, Capacitance (pF) ID, Drain-to-Source Current (A) 2.0 0 0 24 1000 100 Coss 10 Crss 12 1 0 0 5 10 15 VDS, Drain-to-Source Voltage (V) 0 20 Fig. 2 - Typical Output Characteristics 100 200 300 400 500 VDS, Drain-to-Source Voltage (V) 600 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 12 10 000 80 Coss, Output Capacitance (pF) TJ = 25 °C ID, Drain-to-Source Current (A) 2.5 60 40 TJ = 150 °C 20 10 1000 8 Eoss 6 100 4 Coss 2 VDS = 27.9 V 10 0 0 5 10 15 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S18-1109-Rev. A, 12-Nov-2018 20 Eoss, Output Capacitance Stored Energy (μJ) ID, Drain-to-Source Current (A) 80 0 0 100 200 300 400 500 VDS, Drain-to-Source Voltage (V) 600 Fig. 6 - Coss and Eoss vs. VDS Document Number: 92198 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB120N60E www.vishay.com Vishay Siliconix 28 VDS = 480 V VDS = 300 V VDS = 120 V 24 9 ID, Drain Current (A) VGS, Gate-to-Source Voltage (V) 12 6 3 20 16 12 8 4 0 0 0 10 20 30 Qg, Total Gate Charge (nC) 40 Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage 25 50 75 100 125 TC, Case Temperature (°C) 150 Fig. 10 - Maximum Drain Current vs. Case Temperature 750 TJ = 150 °C 10 VDS, Drain-to-Source Breakdown Voltage (V) ISD, Reverse Drain Current (A) 100 TJ = 25 °C 1 VGS = 0 V 0.1 0.2 0.4 0.6 0.8 1.0 VSD, Source-Drain Voltage (V) 1.2 1.4 Fig. 8 - Typical Source-Drain Diode Forward Voltage 725 700 675 650 625 600 ID = 250 μA 575 -60 -40 -20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 11 - Temperature vs. Drain-to-Source Voltage 1000 ID, Drain Current (A) Operation in this area 100 limited by RDS(on) IDM limited 10 100 μs Limited by RDS(on)* 1 1 ms TC = 25 °C TJ = 150 °C single pulse 0.1 10 ms BVDSS limited 0.01 1 10 100 1000 VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Fig. 9 - Maximum Safe Operating Area S18-1109-Rev. A, 12-Nov-2018 Document Number: 92198 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB120N60E www.vishay.com Vishay Siliconix 1 Normalized Effective Transient Thermal Impedance Duty cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single pulse 0.01 0.0001 0.001 0.01 Pulse Time (s) 0.1 1 Fig. 12 - Normalized Transient Thermal Impedance, Junction-to-Case RD VDS VDS tp VGS D.U.T. VDD Rg + - VDD VDS 10 V Pulse width ≤ 1 μs Duty factor ≤ 0.1 % IAS Fig. 13 - Switching Time Test Circuit Fig. 16 - Unclamped Inductive Waveforms VDS Qg 10 V 90 % Qgs 10 % VGS Qgd VG td(on) td(off) tr tf Charge Fig. 17 - Basic Gate Charge Waveform Fig. 14 - Switching Time Waveforms Current regulator Same type as D.U.T. L VDS Vary tp to obtain required IAS 50 kΩ 12 V D.U.T. Rg 0.2 μF 0.3 μF + - VDD + D.U.T. IAS - VDS 10 V tp 0.01 Ω VGS 3 mA Fig. 15 - Unclamped Inductive Test Circuit IG ID Current sampling resistors Fig. 18 - Gate Charge Test Circuit S18-1109-Rev. A, 12-Nov-2018 Document Number: 92198 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB120N60E www.vishay.com Vishay Siliconix Peak Diode Recovery dv/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer 3 + 2 - - 4 + 1 Rg • • • • 1 Driver gate drive Period P.W. + V - DD dv/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test D= P.W. Period V GS = 10 V a 2 D.U.T. ISD waveform Reverse recovery current 3 D.U.T. VDS Body diode forward current di/dt waveform Diode recovery dv/dt Re-applied voltage V DD Body diode forward drop 4 Inductor current Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 19 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?92198. S18-1109-Rev. A, 12-Nov-2018 Document Number: 92198 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 A 4 4 L1 B A E c2 H Gauge plane 4 0° to 8° 5 D B Detail A Seating plane H 1 2 C 3 C L L3 L4 Detail “A” Rotated 90° CW scale 8:1 L2 B A1 B A 2 x b2 c 2xb E 0.010 M A M B ± 0.004 M B 2xe Plating 5 b1, b3 Base metal c1 (c) D1 4 5 (b, b2) Lead tip MILLIMETERS DIM. MIN. MAX. View A - A INCHES MIN. 4 E1 Section B - B and C - C Scale: none MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 6.22 - 0.245 - b 0.51 0.99 0.020 0.039 E1 b1 0.51 0.89 0.020 0.035 e b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 2.54 BSC 0.100 BSC c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 D 8.38 9.65 0.330 0.380 L4 0.25 BSC 4.78 5.28 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 AN826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead 0.420 0.355 0.635 (16.129) (9.017) (10.668) 0.145 (3.683) 0.135 (3.429) 0.200 0.050 (5.080) (1.257) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Document Number: 73397 11-Apr-05 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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ALL RIGHTS RESERVED Revision: 01-Jan-2023 1 Document Number: 91000