SIHB30N60E-E3

SiHB30N60E www.vishay.com Vishay Siliconix E Series Power MOSFET FEATURES D • • • • • • D2PAK (TO-263) G G D S S APPLICATIONS N-Channel MOSFET • • • • Server and telecom power supplies Switch mode power supplies (SMPS) Power factor correction power supplies (PFC) Lighting - High-intensity discharge (HID) - Fluorescent ballast lighting - LED lighting • Industrial - Welding - Induction heating - Motor drives • Battery chargers • Renewable energy - Solar (PV inverters) PRODUCT SUMMARY VDS (V) at TJ max. RDS(on) max. (Ω) at 25 °C 650 VGS = 10 V Qg max. (nC) 0.125 130 Qgs (nC) 15 Qgd (nC) 39 Configuration Low figure-of-merit (FOM) Ron x Qg Low input capacitance (Ciss) Reduced switching and conduction losses Ultra low gate charge (Qg) Avalanche energy rated (UIS) Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 Single ORDERING INFORMATION D2PAK (TO-263) Package SiHB30N60E-GE3 Lead (Pb)-free and halogen-free SiHB30N60ET1-GE3 SiHB30N60ET5-GE3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-source voltage VDS 600 Gate-source voltage VGS ± 30 Continuous drain current (TJ = 150 °C) VGS at 10 V TC = 25 °C TC = 100 °C Pulsed drain current a ID UNIT V 29 18 A IDM 76 2 W/°C Single pulse avalanche energy b EAS 690 mJ Maximum power dissipation PD 250 W TJ, Tstg -55 to +150 °C Linear derating factor Operating junction and storage temperature range Drain-source voltage slope VDS = 0 V to 80 % VDS Reverse diode dV/dt d Soldering recommendations (peak temperature) c for 10 s dV/dt 70 18 300 V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature b. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 Ω, IAS = 7 A c. 1.6 mm from case d. ISD ≤ ID, dI/dt = 100 A/μs, starting TJ = 25 °C S17-0965-Rev. H, 26-Jun-17 Document Number: 91453 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB30N60E www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum junction-to-ambient RthJA - 62 Maximum junction-to-case (drain) RthJC - 0.5 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-source breakdown voltage VDS temperature coefficient Gate-source threshold voltage (N) VDS VGS = 0 V, ID = 250 μA 600 - - V ΔVDS/TJ Reference to 25 °C, ID = 250 μA - 0.64 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2 2.8 4 V VGS = ± 20 V - - ± 100 nA VGS = ± 30 V - - ±1 μA VDS = 600 V, VGS = 0 V - - 1 VDS = 600 V, VGS = 0 V, TJ = 150 °C - - 100 Gate-source leakage IGSS Zero gate voltage drain current IDSS μA - 0.104 0.125 Ω gfs VDS = 8 V, ID = 3 A - 5.4 - S Input capacitance Ciss 2600 - Coss - 138 - Reverse transfer capacitance Crss VGS = 0 V, VDS = 100 V, f = 1 MHz - Output capacitance - 3 - Effective output capacitance, energy related a Co(er) - 98 - Effective output capacitance, time related b Co(tr) - 346 - - 85 130 - 15 - Drain-source on-state resistance Forward transconductance RDS(on) VGS = 10 V ID = 15 A Dynamic pF VDS = 0 V to 480 V, VGS = 0 V Total gate charge Qg Gate-source charge Qgs VGS = 10 V ID = 15 A, VDS = 480 V Gate-drain charge Qgd - 39 - Turn-on delay time td(on) - 19 40 Rise time Turn-off delay time tr td(off) Fall time tf Gate input resistance Rg VDD = 380 V, ID = 15 A, VGS = 10 V, Rg = 4.7 Ω - 32 65 - 63 95 - 36 75 f = 1 MHz, open drain - 0.63 - - - 29 - - 65 nC ns Ω Drain-Source Body Diode Characteristics Continuous source-drain diode current IS Pulsed diode forward current ISM Diode forward voltage VSD Body diode reverse recovery time trr Body diode reverse recovery charge Qrr Reverse recovery current IRRM MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = 15 A, VGS = 0 V TJ = 25 °C, IF = IS = 15 A, dI/dt = 100 A/μs, VR = 20 V - - 1.3 V - 402 605 ns - 7 15 μC - 32 65 A Notes a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS S17-0965-Rev. H, 26-Jun-17 Document Number: 91453 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB30N60E www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 80 3.0 TOP 15 V 14 V 13 V 12 V 11 V 10 V 9.0 V 8.0 V 7.0 V 6.0 V BOTTOM 5.0 V ID - Drain Current (A) 60 TJ = 25 °C 50 40 30 20 VGS = 10 V 2.0 1.5 1.0 0.5 5V 10 ID = 15 A 2.5 RDS(on) - On-Resistance (Normalized) 70 0.0 0 0 5 10 15 20 25 - 60 - 40 - 20 30 0 20 40 60 80 100 120 140 160 TJ - Junction Temperature (°C) VDS - Drain-to-Source Voltage (V) Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 4 - Normalized On-Resistance vs. Temperature 50 10 000 Ciss TOP 15 V 14 V 13 V 12 V 11 V 10 V 9.0 V 8.0 V 7.0 V 6.0 V BOTTOM 5.0 V 30 20 VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd x Cds shorted Crss = Cgd Coss = Cds + Cgd 1000 C - Capacitance (pF) ID - Drain Current (A) 40 100 Coss 10 10 Crss TJ = 150 °C 1 0 0 5 10 15 20 25 0 30 100 200 300 400 500 600 VDS - Drain-to-Source Voltage (V) VDS - Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics, TC = 150 °C Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 80 18 16 TJ = 25 °C 14 2000 TJ = 150 °C 40 10 Coss Eoss 8 200 Eoss (μJ) 12 Coss (pF) ID, Drain Current (A) 60 6 20 4 2 0 20 0 5 10 15 20 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S17-0965-Rev. H, 26-Jun-17 25 0 0 100 200 300 400 500 600 VDS Fig. 6 - Coss and Eoss vs. VDS Document Number: 91453 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB30N60E www.vishay.com Vishay Siliconix 24 30.0 VDS = 300 V 25.0 VDS = 120 V 16 VDS = 480 V 12 8 ID, Drain Current (A) VGS - Gate-to-Source Voltage (V) ID = 15 A 20 4 20.0 15.0 10.0 5.0 0 0 0 25 50 75 100 125 150 25 50 75 Qg - Total Gate Charge (nC) 725 VDS, Drain-to-Source Breakdown Voltage (V) 100 IS - Source Current (A) 150 Fig. 10 - Maximum Drain Current vs. Case Temperature 1000 TJ = 150 °C 10 TJ = 25 °C 1 0.1 0.01 0.001 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VSD - Source-to-Drain Voltage (V) Operation in this Area Limited by RDS(on) 700 675 650 625 600 575 550 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 TJ - Temperature (°C) Fig. 8 - Typical Source-Drain Diode Forward Voltage Fig. 11 - Temperature vs. Drain-to-Source Voltage IDM Limited 10 ID, Drain Current (A) 125 TC - Temperature (°C) Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage 100 100 100 μs Limited by RDS(on)* 1 ms 1 10 ms 0.1 TC = 25 °C TJ = 150 °C Single Pulse BVDSS Limited 0.01 1 10 100 1000 VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Fig. 9 - Maximum Safe Operating Area S17-0965-Rev. H, 26-Jun-17 Document Number: 91453 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB30N60E www.vishay.com Vishay Siliconix Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 0.0001 0.001 0.01 0.1 1 Square Wave Pulse Duration (s) Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case VGS VDS RD VDS tp VDD D.U.T. RG + - VDD VDS 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % IAS Fig. 16 - Unclamped Inductive Waveforms Fig. 13 - Switching Time Test Circuit VDS 90 % QG 10 V QGS 10 % VGS QGD VG td(on) td(off) tf tr Fig. 14 - Switching Time Waveforms Charge Fig. 17 - Basic Gate Charge Waveform L Vary tp to obtain required IAS VDS Current regulator Same type as D.U.T. D.U.T RG + - IAS V DD 50 kΩ 12 V 0.2 µF 0.3 µF 10 V tp + 0.01 Ω Fig. 15 - Unclamped Inductive Test Circuit D.U.T. - VDS VGS 3 mA IG ID Current sampling resistors Fig. 18 - Gate Charge Test Circuit S17-0965-Rev. H, 26-Jun-17 Document Number: 91453 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB30N60E www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 19 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91453. S17-0965-Rev. H, 26-Jun-17 Document Number: 91453 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 A 4 4 L1 B A E c2 H Gauge plane 4 0° to 8° 5 D B Detail A Seating plane H 1 2 C 3 C L L3 L4 Detail “A” Rotated 90° CW scale 8:1 L2 B A1 B A 2 x b2 c 2xb E 0.010 M A M B ± 0.004 M B 2xe Plating 5 b1, b3 Base metal c1 (c) D1 4 5 (b, b2) Lead tip MILLIMETERS DIM. MIN. MAX. View A - A INCHES MIN. 4 E1 Section B - B and C - C Scale: none MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 6.22 - 0.245 - b 0.51 0.99 0.020 0.039 E1 b1 0.51 0.89 0.020 0.035 e b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 2.54 BSC 0.100 BSC c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 D 8.38 9.65 0.330 0.380 L4 0.25 BSC 4.78 5.28 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 AN826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead 0.420 0.355 0.635 (16.129) (9.017) (10.668) 0.145 (3.683) 0.135 (3.429) 0.200 0.050 (5.080) (1.257) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Document Number: 73397 11-Apr-05 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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ALL RIGHTS RESERVED Revision: 01-Jan-2022 1 Document Number: 91000