SiHD14N60E
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Vishay Siliconix
E Series Power MOSFET
FEATURES
D
•
•
•
•
•
•
DPAK
(TO-252)
G
D
G
S
Low figure-of-merit (FOM) Ron x Qg
Low input capacitance (Ciss)
Reduced switching and conduction losses
Ultra low gate charge (Qg)
Avalanche energy rated (UIS)
Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
S
APPLICATIONS
N-Channel MOSFET
•
•
•
•
Server and telecom power supplies
Switch mode power supplies (SMPS)
Power factor correction power supplies (PFC)
Lighting
- High-intensity discharge (HID)
- Fluorescent ballast lighting
• Industrial
- Welding
- Induction heating
- Motor drives
- Battery chargers
- Renewable energy
- Solar (PV inverters)
PRODUCT SUMMARY
VDS (V) at TJ max.
650
RDS(on) typ. () at 25 °C
VGS = 10 V
Qg max. (nC)
0.269
64
Qgs (nC)
8
Qgd (nC)
13
Configuration
Single
ORDERING INFORMATION
Package
DPAK (TO-252)
SiHD14N60E-GE3
SiHD14N60ET1-GE3
Lead (Pb)-free and halogen-free
SiHD14N60ET4-GE3
SiHD14N60ET5-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-source voltage
VDS
600
Gate-source voltage
VGS
± 30
Continuous drain current (TJ = 150 °C)
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed drain current a
ID
IDM
Linear derating factor
Single pulse avalanche
energy b
Maximum power dissipation
Operating junction and storage temperature range
Drain-source voltage slope
TJ = 125 °C
Reverse diode dV/dt d
Soldering recommendations (peak temperature) c
for 10 s
UNIT
V
13
8
A
32
1.2
W/°C
EAS
136
mJ
PD
147
W
TJ, Tstg
-55 to +150
°C
dV/dt
70
32
300
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature
b. VDD = 140 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 , IAS = 3.1 A
c. 1.6 mm from case
d. ISD ID, dI/dt = 100 A/μs, starting TJ = 25 °C
S17-1422-Rev. B, 11-Sep-17
Document Number: 91663
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For technical questions, contact: hvm@vishay.com
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum junction-to-ambient
RthJA
-
62
Maximum junction-to-case (drain)
RthJC
-
0.85
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
VDS temperature coefficient
Gate-source threshold voltage (N)
VDS
VGS = 0 V, ID = 250 μA
600
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.73
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
VGS = ± 20 V
-
-
± 100
nA
VGS = ± 30 V
-
-
±1
μA
VDS = 600 V, VGS = 0 V
-
-
1
VDS = 480 V, VGS = 0 V, TJ = 125 °C
-
-
10
Gate-source leakage
IGSS
Zero gate voltage drain current
IDSS
μA
-
0.269
0.309
gfs
VDS = 30 V, ID = 7 A
-
3.8
-
S
Input capacitance
Ciss
1205
-
Coss
-
62
-
Reverse transfer capacitance
Crss
VGS = 0 V,
VDS = 100 V,
f = 1 MHz
-
Output capacitance
-
5
-
Effective output capacitance, energy
related a
Co(er)
-
52
-
Effective output capacitance, time
related b
Co(tr)
-
177
-
-
32
64
-
8
-
Drain-source on-state resistance
Forward transconductance
RDS(on)
VGS = 10 V
ID = 7 A
Dynamic
pF
VDS = 0 V to 480 V, VGS = 0 V
Total gate charge
Qg
Gate-source charge
Qgs
VGS = 10 V
ID = 7 A, VDS = 480 V
Gate-drain charge
Qgd
-
13
-
Turn-on delay time
td(on)
-
15
30
Rise time
Turn-off delay time
tr
td(off)
Fall time
tf
Gate input resistance
Rg
nC
VDD = 480 V, ID = 7 A,
VGS = 10 V, Rg = 9.1
-
19
38
-
35
70
-
15
30
f = 1 MHz, open drain
0.38
0.75
1.5
-
-
13
-
-
32
-
-
1.2
V
-
281
-
ns
-
3.4
-
μC
-
22
-
A
ns
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
IS
Pulsed diode forward current
ISM
Diode forward voltage
VSD
Reverse recovery time
trr
Reverse recovery charge
Qrr
Reverse recovery current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 7 A, VGS = 0 V
TJ = 25 °C, IF = IS = 7 A,
dI/dt = 100 A/μs, VR = 25 V
S
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS
S17-1422-Rev. B, 11-Sep-17
Document Number: 91663
2
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHD14N60E
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
20
ID = 7 A
10
0
2.0
1.5
1.0
VGS = 10 V
0.5
0
0
5
10
15
20
25
VDS, Drain-to-Source Voltage (V)
30
-60 -40 -20
20
10 000
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
TJ = 150 °C
Ciss
1000
C, Capacitance (pF)
15
0 20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 1 - Typical Output Characteristics
ID, Drain-to-Source Current (A)
2.5
10
100
Coss
10
5
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds shorted
Crss = Cgd
Coss = Cds + Cgd
Crss
1
0
0
5
10
15
20
25
VDS, Drain-to-Source Voltage (V)
0
30
100
200
300
400
500
VDS, Drain-to-Source Voltage (V)
600
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 2 - Typical Output Characteristics
10 000
8
7
6
TJ = 25 °C
1000
20
5
Coss (pF)
ID, Drain-to-Source Current (A)
30
TJ = 150 °C
Coss
Eoss
4
3
100
10
Eoss (μJ)
ID, Drain-to-Source Current (A)
30
3.0
TJ = 25 °C
RDS(on), Drain-to-Source On-Resistance
(Normalized)
TOP
2
VDS = 30.4 V
1
0
10
0
5
10
15
20
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S17-1422-Rev. B, 11-Sep-17
25
0
0
100
200
300
VDS
400
500
600
Fig. 6 - Coss and Eoss vs. VDS
Document Number: 91663
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHD14N60E
www.vishay.com
15
VDS = 480 V
VDS = 300 V
VDS = 120 V
20
ID, Drain Current (A)
VGS, Gate-to-Source Voltage (V)
24
Vishay Siliconix
16
12
8
0
0
15
30
45
Qg, Total Gate Charge (nC)
25
60
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
50
75
100
125
TC, Case Temperature (°C)
150
Fig. 10 - Maximum Drain Current vs. Case Temperature
100
775
VDS, Drain-to-Source Breakdown Voltage (V)
ISD, Reverse Drain Current (A)
5
4
0
TJ = 150 °C
10
TJ = 25 °C
1
VGS = 0 V
0.1
0.2
0.4
0.6
0.8
1.0
VSD, Source-Drain Voltage (V)
1.2
1.4
Fig. 8 - Typical Source-Drain Diode Forward Voltage
100
ID, Drain Current (A)
10
Operation in this Area
Limited by RDS(on)
750
725
700
675
650
625
ID = 250 μA
600
-60 -40 -20
0 20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 11 - Temperature vs. Drain-to-Source Voltage
IDM Limited
10
100 μs
Limited by RDS(on)*
1
1 ms
0.1
10 ms
TC = 25 °C
TJ = 150 °C
Single Pulse
BVDSS Limited
0.01
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Fig. 9 - Maximum Safe Operating Area
S17-1422-Rev. B, 11-Sep-17
Document Number: 91663
4
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHD14N60E
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Vishay Siliconix
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.05
0.1
0.02
Single Pulse
0.01
0.0001
0.001
0.01
0.1
1
Pulse Time (s)
Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case
RD
VDS
VDS
tp
VGS
VDD
D.U.T.
RG
+
- VDD
VDS
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
IAS
Fig. 13 - Switching Time Test Circuit
Fig. 16 - Unclamped Inductive Waveforms
VDS
QG
10 V
90 %
QGS
QGD
VG
10 %
VGS
td(on)
td(off) tf
tr
Charge
Fig. 17 - Basic Gate Charge Waveform
Fig. 14 - Switching Time Waveforms
Current regulator
Same type as D.U.T.
L
VDS
Vary tp to obtain
required IAS
50 kΩ
D.U.T.
RG
12 V
+
-
0.2 µF
0.3 µF
VDD
+
IAS
D.U.T.
-
VDS
10 V
tp
0.01 Ω
VGS
3 mA
Fig. 15 - Unclamped Inductive Test Circuit
IG
ID
Current sampling resistors
Fig. 18 - Gate Charge Test Circuit
S17-1422-Rev. B, 11-Sep-17
Document Number: 91663
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For technical questions, contact: hvm@vishay.com
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHD14N60E
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Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 19 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91663.
S17-1422-Rev. B, 11-Sep-17
Document Number: 91663
6
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
TO-252AA Case Outline
VERSION 1: FACILITY CODE = Y
E
A
C2
H
D
D1
L3
b3
e
b2
e1
L
gage plane height (0.5 mm)
L4
b
L5
E1
C
A1
MILLIMETERS
DIM.
MIN.
A
2.18
MAX.
2.38
A1
-
0.127
b
0.64
0.88
b2
0.76
1.14
b3
4.95
5.46
C
0.46
0.61
C2
0.46
0.89
D
5.97
6.22
D1
4.10
-
E
6.35
6.73
E1
4.32
-
H
9.40
10.41
e
2.28 BSC
e1
4.56 BSC
L
1.40
1.78
L3
0.89
1.27
L4
-
1.02
L5
1.01
1.52
Note
• Dimension L3 is for reference only
Revision: 03-Oct-2022
Document Number: 71197
1
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
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Vishay Siliconix
VERSION 2: FACILITY CODE = N
E
e
A
b3
E1
E1/2
c2
θ
e
L4
L5
L6
H
D
L3
D1
θ
0.25
(3°)
DETAIL "B"
C A B
(3°)
DETAIL "B"
A1
C
L
(L1)
b1
SEATING
C
PLANE
θ
L2
GAUGE
PLANE
H
C
(b)
c1
3x b
2x e
c
2x b2
MILLIMETERS
MILLIMETERS
DIM.
A
MIN.
2.18
MAX.
DIM.
MIN.
2.39
L
1.50
A1
-
0.13
L1
b
0.65
0.89
L2
MAX.
1.78
2.74 ref.
0.51 BSC
b1
0.64
0.79
L3
b2
0.76
1.13
L4
-
1.02
b3
4.95
5.46
L5
1.14
1.49
c
0.46
0.61
L6
0.65
0.85
c1
0.41
0.56
0°
10°
1
0°
15°
2
25°
35°
c2
0.46
0.60
D
5.97
6.22
D1
5.21
-
E
6.35
6.73
E1
4.32
e
H
2.29 BSC
9.94
0.89
1.27
Notes
• Dimensioning and tolerance confirm to ASME Y14.5M-1994
• All dimensions are in millimeters. Angles are in degrees
• Heat sink side flash is max. 0.8 mm
• Radius on terminal is optional
10.34
ECN: E22-0399-Rev. R, 03-Oct-2022
DWG: 5347
Revision: 03-Oct-2022
Document Number: 71197
2
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TO-252AA (HIGH VOLTAGE)
E
b3
E1
L3
D1
D
H
L4
b2
b
A
c2
e
A1
L1
L
c
θ
L2
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
E
6.40
6.73
0.252
0.265
L
1.40
1.77
0.055
L1
2.743 REF
L2
0.070
0.108 REF
0.508 BSC
0.020 BSC
L3
0.89
1.27
0.035
0.050
L4
0.64
1.01
0.025
0.040
D
6.00
6.22
0.236
0.245
H
9.40
10.40
0.370
0.409
b
0.64
0.88
0.025
0.035
b2
0.77
1.14
0.030
0.045
b3
5.21
5.46
0.205
e
2.286 BSC
0.215
0.090 BSC
A
2.20
2.38
0.087
A1
0.00
0.13
0.000
0.094
0.005
c
0.45
0.60
0.018
0.024
c2
0.45
0.58
0.018
0.023
D1
5.30
-
0.209
-
E1
4.40
-
0.173
-
θ
0'
10'
0'
10'
ECN: S-81965-Rev. A, 15-Sep-08
DWG: 5973
Notes
1. Package body sizes exclude mold flash, protrusion or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side.
2. Package body sizes determined at the outermost extremes of the plastic body exclusive of mold flash, gate burrs and interlead flash, but
including any mismatch between the top and bottom of the plastic body.
3. The package top may be smaller than the package bottom.
4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10 mm total in excess of "b" dimension at maximum
material condition. The dambar cannot be located on the lower radius of the foot.
Document Number: 91344
Revision: 15-Sep-08
www.vishay.com
1
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)
0.224
0.243
0.087
(2.202)
0.090
(2.286)
(10.668)
0.420
(6.180)
(5.690)
0.180
0.055
(4.572)
(1.397)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Return to Index
APPLICATION NOTE
Document Number: 72594
Revision: 21-Jan-08
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3
Legal Disclaimer Notice
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Vishay
Disclaimer
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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with the properties described in the product specification is suitable for use in a particular application. Parameters provided in
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Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited
to the warranty expressed therein.
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Revision: 01-Jan-2022
1
Document Number: 91000