SiHD180N60E
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Vishay Siliconix
E Series Power MOSFET
FEATURES
D
• 4th generation E series technology
DPAK (TO-252)
• Low figure-of-merit (FOM) Ron x Qg
• Low effective capacitance (Co(er))
D
• Reduced switching and conduction losses
G
• Avalanche energy rated (UIS)
S
G
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
S
N-Channel MOSFET
APPLICATIONS
•
•
•
•
Server and telecom power supplies
Switch mode power supplies (SMPS)
Power factor correction power supplies (PFC)
Lighting
- High-intensity discharge (HID)
- Fluorescent ballast lighting
• Industrial
- Welding
- Induction heating
- Motor drives
- Battery chargers
- Solar (PV inverters)
PRODUCT SUMMARY
VDS (V) at TJ max.
RDS(on) typ. () at 25 °C
650
VGS = 10 V
Qg max. (nC)
0.170
32
Qgs (nC)
7
Qgd (nC)
10
Configuration
Single
ORDERING INFORMATION
Package
DPAK (TO-252)
SiHD180N60E-GE3
Lead (Pb)-free and halogen-free
SiHD180N60ET1-GE3
SiHD180N60ET4-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-source voltage
VDS
600
Gate-source voltage
VGS
± 30
Continuous drain current (TJ = 150 °C)
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed drain current a
ID
IDM
Linear derating factor
UNIT
V
19
12
A
40
1.25
W/°C
Single pulse avalanche energy b
EAS
88
mJ
Maximum power dissipation
PD
156
W
TJ, Tstg
-55 to +150
°C
Operating junction and storage temperature range
Drain-source voltage slope
TJ = 125 °C
Reverse diode dv/dt d
Soldering recommendations (peak temperature) c
For 10 s
dv/dt
100
22
260
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature
b. VDD = 120 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 , IAS = 2.5 A
c. 1.6 mm from case
d. ISD ID, di/dt = 100 A/μs, starting TJ = 25 °C
S20-0340-Rev. C, 11-May-2020
Document Number: 92132
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SiHD180N60E
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THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum junction-to-ambient
RthJA
-
62
Maximum junction-to-case (drain)
RthJC
-
0.8
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
VDS temperature coefficient
Gate-source threshold voltage (N)
VDS
VGS = 0 V, ID = 250 μA
600
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.66
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
3.0
-
5.0
V
VGS = ± 20 V
-
-
± 100
nA
VGS = ± 30 V
-
-
±1
μA
VDS = 600 V, VGS = 0 V
-
-
1
VDS = 480 V, VGS = 0 V, TJ = 125 °C
-
-
10
Gate-source leakage
IGSS
Zero gate voltage drain current
IDSS
μA
-
0.170
0.195
gfs
VDS = 20 V, ID = 9.5 A
-
6.5
-
S
Input capacitance
Ciss
1080
-
Coss
-
56
-
Reverse transfer capacitance
Crss
VGS = 0 V,
VDS = 100 V,
f = 1 MHz
-
Output capacitance
-
5
-
Effective output capacitance, energy
related a
Co(er)
-
39
-
Effective output capacitance, time
related b
Co(tr)
-
244
-
-
21
32
-
7
-
Drain-source on-state resistance
Forward transconductance a
RDS(on)
VGS = 10 V
ID = 9.5 A
Dynamic
pF
VDS = 0 V to 480 V, VGS = 0 V
Total gate charge
Qg
Gate-source charge
Qgs
VGS = 10 V
ID = 9.5 A, VDS = 480 V
Gate-drain charge
Qgd
-
11
-
Turn-on delay time
td(on)
-
15
30
VDD = 480 V, ID = 9.5 A,
VGS = 10 V, Rg = 9.1
-
22
44
-
23
46
-
9
18
f = 1 MHz, open drain
0.2
0.6
1.2
-
-
19
-
-
40
Rise time
Turn-off delay time
tr
td(off)
Fall time
tf
Gate input resistance
Rg
nC
ns
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
IS
Pulsed diode forward current
ISM
Diode forward voltage
VSD
Reverse recovery time
trr
Reverse recovery charge
Qrr
Reverse recovery current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 9.5 A, VGS = 0 V
TJ = 25 °C, IF = IS = 9.5 A,
di/dt = 100 A/μs, VR = 25 V
S
-
-
1.2
V
-
275
550
ns
-
3.6
7.2
μC
-
23
-
A
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS
S20-0340-Rev. C, 11-May-2020
Document Number: 92132
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHD180N60E
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Axis Title
Axis Title
10000
30
9V
1000
25
20
8V
15
10
100
7V
5
5V
6V
0
2.5
2.0
5
10
15
1000
1.5
VGS = 10 V
1.0
0
10
-60 -40 -20 0
20
20 40 60 80 100 120 140 160
VDS - Drain-to-Source Voltage (V)
TJ - Junction Temperature (°C)
Fig. 1 - Typical Output Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
Axis Title
15 V
14 V
13 V
12 V
11 V
10 V
9V
20
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds shorted
Crss = Cgd
Coss = Cds + Cgd
10 000
8V
1000
7V
16
12
100
6V
8
100
Coss
10
4
1000
Ciss
1000
1st line
2nd line
24
10000
TJ = 150 °C
2nd line
C - Capacitance (pF)
28
Axis Title
100 000
10000
1st line
2nd line
32
100
Crss
5V
0
1
10
0
5
10
15
20
10
0
100
200
300
400
500
600
VDS - Drain-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Axis Title
Axis Title
10000
45
10 000
9
35
TJ = 25 °C
1000
30
25
TJ = 150 °C
20
15
100
10
5
VDS = 29.7 V
0
0
5
10
15
10
20
2nd line
Coss - Output Capacitance (pF)
8
1st line
2nd line
2nd line
ID - Drain-to-Source Current (A)
40
7
1000
6
5
Coss
Eoss
3
2
1
0
10
0
100
200
300
400
500
VGS - Gate-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
Fig. 6 - Coss and Eoss vs. VDS
S20-0340-Rev. C, 11-May-2020
4
100
Eoss - Output Capacitance Stored Energy (µJ)
2nd line
2nd line
ID - Drain-to-Source Current (A)
100
0.5
10
0
10000
ID = 9.5 A
1st line
2nd line
35
1st line
2nd line
2nd line
ID - Drain-to-Source Current (A)
TJ = 25 °C
15 V
14 V
13 V
12 V
11 V
10 V
40
3.0
RDS(on) - Drain-to-Source On-Resistance
(Normalized)
45
600
Document Number: 92132
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHD180N60E
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Axis Title
Axis Title
10000
10000
20
VDS = 480 V
VDS = 300 V
VDS = 120 V
6
100
3
1000
12
1st line
2nd line
1000
2nd line
ID - Drain Current (A)
16
9
1st line
2nd line
2nd line
VGS - Gate-to-Source Voltage (V)
12
8
100
4
0
0
10
0
7
14
21
10
25
28
50
75
100
125
150
Qg - Total Gate Charge (nC)
TC - Case Temperature (°C)
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 10 - Maximum Drain Current vs. Case Temperature
Axis Title
TJ = 150 °C
10
1000
TJ = 25 °C
1st line
2nd line
2nd line
ISD - Reverse Drain Current (A)
100
100
1
VGS = 0 V
0.1
0.2
0.4
0.6
0.8
1.0
1.2
10
775
10000
750
725
1000
700
1st line
2nd line
10000
2nd line
VDS - Drain-to-Source Breakdown Voltage (V)
Axis Title
675
650
100
625
600
ID = 250 µA
575
10
-60 -40 -20 0
1.4
20 40 60 80 100 120 140 160
VSD - Source-Drain Voltage (V)
TJ - Junction Temperature (°C)
Fig. 8 - Typical Source-Drain Diode Forward Voltage
Fig. 11 - Temperature vs. Drain-to-Source Voltage
Axis Title
10000
1000
Operation in this area
limited by RDS(on)
IDM limited
1000
10
100 µs
Limited by RDS(on) a
1
1st line
2nd line
2nd line
ID - Drain Current (A)
100
100
1 ms
0.1
TC = 25 °C,
TJ = 150 °C,
single pulse
10 ms
BVDSS limited
0.01
1
10
100
10
1000
VDS - Drain-to-Source Voltage (V)
Fig. 9 - Maximum Safe Operating Area
Note
a. VGS > minimum VGS at which RDS(on) is specified
S20-0340-Rev. C, 11-May-2020
Document Number: 92132
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For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHD180N60E
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Vishay Siliconix
Axis Title
1
10000
0.2
0.1
1000
1st line
2nd line
Normalized Effective Transient
Thermal Impedance
Duty cycle = 0.5
0.05
0.1
0.02
100
Single pulse
0.01
0.0001
10
0.001
0.01
0.1
1
Pulse Time (s)
Fig. 12 - Normalized Transient Thermal Impedance, Junction-to-Case
RD
VDS
VDS
tp
VGS
D.U.T.
VDD
Rg
+
- VDD
VDS
10 V
Pulse width ≤ 1 μs
Duty factor ≤ 0.1 %
IAS
Fig. 13 - Switching Time Test Circuit
Fig. 16 - Unclamped Inductive Waveforms
VDS
Qg
10 V
90 %
Qgs
10 %
VGS
Qgd
VG
td(on)
td(off)
tr
tf
Charge
Fig. 14 - Switching Time Waveforms
Fig. 17 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
L
VDS
Vary tp to obtain
required IAS
50 kΩ
D.U.T.
Rg
+
- VDD
12 V
0.2 μF
0.3 μF
+
IAS
D.U.T.
-
VDS
10 V
tp
0.01 Ω
VGS
3 mA
Fig. 15 - Unclamped Inductive Test Circuit
IG
ID
Current sampling resistors
Fig. 18 - Gate Charge Test Circuit
S20-0340-Rev. C, 11-May-2020
Document Number: 92132
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SiHD180N60E
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Vishay Siliconix
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
3
+
2
-
-
4
+
1
Rg
•
•
•
•
1 Driver gate drive
Period
P.W.
+
V
- DD
dv/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
D=
P.W.
Period
V GS = 10 V a
2
D.U.T. ISD waveform
Reverse
recovery
current
3 D.U.T. VDS
Body diode forward
current
di/dt
waveform
Diode recovery
dv/dt
Re-applied
voltage
V DD
Body diode forward drop
4 Inductor current
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 19 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?92132.
S20-0340-Rev. C, 11-May-2020
Document Number: 92132
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Package Information
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Vishay Siliconix
TO-252AA Case Outline
VERSION 1: FACILITY CODE = Y
E
A
C2
H
D
D1
L3
b3
e
b2
e1
L
gage plane height (0.5 mm)
L4
b
L5
E1
C
A1
MILLIMETERS
DIM.
MIN.
A
2.18
MAX.
2.38
A1
-
0.127
b
0.64
0.88
b2
0.76
1.14
b3
4.95
5.46
C
0.46
0.61
C2
0.46
0.89
D
5.97
6.22
D1
4.10
-
E
6.35
6.73
E1
4.32
-
H
9.40
10.41
e
2.28 BSC
e1
4.56 BSC
L
1.40
1.78
L3
0.89
1.27
L4
-
1.02
L5
1.01
1.52
Note
• Dimension L3 is for reference only
Revision: 03-Oct-2022
Document Number: 71197
1
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
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Vishay Siliconix
VERSION 2: FACILITY CODE = N
E
e
A
b3
E1
E1/2
c2
θ
e
L4
L5
L6
H
D
L3
D1
θ
0.25
(3°)
DETAIL "B"
C A B
(3°)
DETAIL "B"
A1
C
L
(L1)
b1
SEATING
C
PLANE
θ
L2
GAUGE
PLANE
H
C
(b)
c1
3x b
2x e
c
2x b2
MILLIMETERS
MILLIMETERS
DIM.
A
MIN.
2.18
MAX.
DIM.
MIN.
2.39
L
1.50
A1
-
0.13
L1
b
0.65
0.89
L2
MAX.
1.78
2.74 ref.
0.51 BSC
b1
0.64
0.79
L3
b2
0.76
1.13
L4
-
1.02
b3
4.95
5.46
L5
1.14
1.49
c
0.46
0.61
L6
0.65
0.85
c1
0.41
0.56
0°
10°
1
0°
15°
2
25°
35°
c2
0.46
0.60
D
5.97
6.22
D1
5.21
-
E
6.35
6.73
E1
4.32
e
H
2.29 BSC
9.94
0.89
1.27
Notes
• Dimensioning and tolerance confirm to ASME Y14.5M-1994
• All dimensions are in millimeters. Angles are in degrees
• Heat sink side flash is max. 0.8 mm
• Radius on terminal is optional
10.34
ECN: E22-0399-Rev. R, 03-Oct-2022
DWG: 5347
Revision: 03-Oct-2022
Document Number: 71197
2
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)
0.224
0.243
0.087
(2.202)
0.090
(2.286)
(10.668)
0.420
(6.180)
(5.690)
0.180
0.055
(4.572)
(1.397)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Return to Index
APPLICATION NOTE
Document Number: 72594
Revision: 21-Jan-08
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Revision: 01-Jan-2023
1
Document Number: 91000