SiHF068N60EF
www.vishay.com
Vishay Siliconix
EF Series Power MOSFET With Fast Body Diode
FEATURES
D
TO-220 FULLPAK
• 4th generation E series technology
• Low figure-of-merit (FOM) Ron x Qg
• Low effective capacitance (Co(er))
G
• Reduced switching and conduction losses
• Avalanche energy rated (UIS)
G
D
S
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
S
N-Channel MOSFET
APPLICATIONS
• Server and telecom power supplies
PRODUCT SUMMARY
VDS (V) at TJ max.
RDS(on) typ. (Ω) at 25 °C
• Switch mode power supplies (SMPS)
650
VGS = 10 V
Qg max. (nC)
• Power factor correction power supplies (PFC)
0.059
• Lighting
77
Qgs (nC)
19
- High-intensity discharge (HID)
Qgd (nC)
16
- Fluorescent ballast lighting
Configuration
Single
• Industrial
- Welding
- Motor drives
- Battery chargers
- Solar (PV inverters)
ORDERING INFORMATION
Package
TO-220 FULLPAK
Lead (Pb)-free and halogen-free
SiHF068N60EF-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-source voltage
VDS
600
Gate-source voltage
VGS
± 30
Continuous drain current (TJ = 150 °C) e
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed drain current a
ID
IDM
Linear derating factor
UNIT
V
16
10
A
115
0.31
W/°C
Single pulse avalanche energy b
EAS
226
mJ
Maximum power dissipation
PD
39
W
TJ, Tstg
-55 to +150
°C
Operating junction and storage temperature range
Drain-source voltage slope
TJ = 125 °C
Reverse diode dV/dt d
Soldering recommendations (peak temperature) c
For 10 s
Mounting torque, M3 screw
dV/dt
100
50
V/ns
260
°C
0.6
Nm
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature
b. VDD = 120 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 Ω, IAS = 4 A
c. 1.6 mm from case
d. ISD ≤ ID, di/dt = 210 A/μs, starting TJ = 25 °C
e. Limited by maximum junction temperature
S21-0987-Rev. C, 11-Oct-2021
Document Number: 92309
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF068N60EF
www.vishay.com
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
LIMIT
Maximum junction-to-ambient
RthJA
65
Maximum junction-to-case (drain)
RthJC
3.2
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
VDS temperature coefficient
Gate-source threshold voltage (N)
VDS
VGS = 0 V, ID = 250 μA
600
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.63
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
3
-
5
V
VGS = ± 20 V
-
-
± 100
nA
VGS = ± 30 V
-
-
±1
μA
Gate-source leakage
IGSS
Zero gate voltage drain current
IDSS
VDS = 480 V, VGS = 0 V
-
-
1
μA
VDS = 480 V, VGS = 0 V, TJ = 125 °C
-
-
2
mA
-
0.059
0.068
Ω
gfs
VDS = 30 V, ID = 16 A
-
9
-
S
Input capacitance
Ciss
2628
-
Coss
-
122
-
Reverse transfer capacitance
Crss
VGS = 0 V,
VDS = 100 V,
f = 1 MHz
-
Output capacitance
-
7
-
Effective output capacitance, energy
related a
Co(er)
-
87
-
Effective output capacitance, time
related b
Co(tr)
-
543
-
-
51
77
-
19
-
Drain-source on-state resistance
Forward transconductance
RDS(on)
VGS = 10 V
ID = 16 A
Dynamic
pF
VDS = 0 V to 480 V, VGS = 0 V
Total gate charge
Qg
Gate-source charge
Qgs
VGS = 10 V
ID = 16 A, VDS = 480 V
Gate-drain charge
Qgd
-
16
-
Turn-on delay time
td(on)
-
27
54
Rise time
Turn-off delay time
tr
td(off)
Fall time
tf
Gate input resistance
Rg
VDD = 480 V, ID = 16 A,
VGS = 10 V, Rg = 9.1 Ω
-
55
83
-
53
80
-
35
70
f = 1 MHz, open drain
0.3
0.7
1.4
-
-
41
-
-
115
nC
ns
Ω
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
IS
Pulsed diode forward current
ISM
Diode forward voltage
VSD
Reverse recovery time
trr
Reverse recovery charge
Qrr
Reverse recovery current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 16 A, VGS = 0 V
TJ = 25 °C, IF = IS = 16 A,
di/dt = 100 A/μs, VR = 400 V
S
-
-
1.2
V
-
152
304
ns
-
1
2
μC
-
14
-
A
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS
S21-0987-Rev. C, 11-Oct-2021
Document Number: 92309
2
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF068N60EF
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Axis Title
Axis Title
10000
1000
60
8V
100
30
7V
6V
5V
0
0
5
10
15
2.5
1000
2.0
1.5
VGS = 10 V
100
1.0
0.5
10
0
10
20
-60 -40 -20 0
20 40 60 80 100 120 140 160
VDS - Drain-to-Source Voltage (V)
TJ - Junction Temperature (°C)
Fig. 1 - Typical Output Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
Axis Title
15 V
14 V
13 V
12 V
11 V
10 V
10000
100 000
TJ = 150 °C
10 000
8V
1000
7V
40
100
6V
20
2nd line
C - Capacitance (pF)
60
Axis Title
10000
1st line
2nd line
80
Ciss
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds shorted
Crss = Cgd
Coss = Cds + Cgd
1000
1000
Coss
100
100
Crss
10
5V
0
5
10
15
10
1
10
0
20
0
100
200
300
400
500
600
VDS - Drain-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Axis Title
Axis Title
120
24
10000
1000
TJ = 150 °C
60
100
30
2nd line
Coss - Output Capacitance (pF)
TJ = 25 °C
90
1st line
2nd line
2nd line
ID - Drain-to-Source Current (A)
50 000
18
5000
Coss
Eoss
12
500
6
VDS = 25.6 V
10
0
0
5
10
15
20
50
0
0
100
200
300
400
500
VGS - Gate-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
Fig. 6 - Coss and Eoss vs. VDS
S21-0987-Rev. C, 11-Oct-2021
Eoss - Output Capacitance Stored Energy (µJ)
2nd line
2nd line
ID - Drain-to-Source Current (A)
1st line
2nd line
9V
ID =16 A
1st line
2nd line
90
RDS(on) - Drain-to-Source On-Resistance
(Normalized)
TJ = 25 °C
15 V
14 V
13 V
12 V
11 V
10 V
10000
3.0
1st line
2nd line
2nd line
ID - Drain-to-Source Current (A)
120
600
Document Number: 92309
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For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF068N60EF
www.vishay.com
Vishay Siliconix
Axis Title
Axis Title
10000
VDS = 480 V
VDS = 300 V
VDS = 120 V
16
6
100
3
1000
12
1st line
2nd line
1000
2nd line
ID - Drain Current (A)
9
10000
20
1st line
2nd line
2nd line
VGS - Gate-to-Source Voltage (V)
12
8
100
4
0
15
30
45
10
0
10
0
60
25
50
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
10
TJ = 25 °C
100
1
VGS = 0 V
10
0.1
1.0
1.2
1.4
1.6
1.8
1.2
10000
1.1
1000
1st line
2nd line
1000
2nd line
VDS - Drain-to-Source Breakdown Voltage
(Normalized)
TJ = 150 °C
1st line
2nd line
2nd line
ISD - Reverse Drain Current (A)
100
0.8
150
Axis Title
10000
0.6
125
Fig. 10 - Maximum Drain Current vs. Case Temperature
Axis Title
0.4
100
TC - Case Temperature (°C)
Qg - Total Gate Charge (nC)
0.2
75
1
0.9
100
ID = 1mA
0.8
10
-60 -40 -20 0
VSD - Source-Drain Voltage (V)
20 40 60 80 100 120 140 160
TJ - Junction Temperature (°C)
Fig. 11 - Temperature vs. Drain-to-Source Voltage
Fig. 8 - Typical Source-Drain Diode Forward Voltage
Axis Title
10000
1000
Operation in this area
limited by RDS(on)
IDM limited
1000
Limited by RDS(on) a
10
100 µs
BVDSS limited
1
1st line
2nd line
2nd line
ID - Drain Current (A)
100
100
0.1
1 ms
TC = 25 °C,
TJ = 150 °C,
single pulse
10 ms
0.01
1
10
100
10
1000
VDS - Drain-to-Source Voltage (V)
Fig. 9 - Maximum Safe Operating Area
Note
a. VGS > minimum VGS at which RDS(on) is specified
S21-0987-Rev. C, 11-Oct-2021
Document Number: 92309
4
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF068N60EF
www.vishay.com
Vishay Siliconix
Axis Title
1
10000
0.2
1000
1st line
2nd line
Normalized Effective Transient
Thermal Impedance
Duty cycle = 0.5
0.1
0.1
0.05
100
0.02
Single pulse
10
0.01
0.0001
0.001
0.01
0.1
1
Pulse Time (s)
Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case
RD
VDS
VDS
tp
VGS
D.U.T.
VDD
Rg
+
- VDD
VDS
10 V
Pulse width ≤ 1 μs
Duty factor ≤ 0.1 %
IAS
Fig. 13 - Switching Time Test Circuit
Fig. 16 - Unclamped Inductive Waveforms
VDS
Qg
10 V
90 %
Qgs
10 %
VGS
Qgd
VG
td(on)
td(off)
tr
tf
Charge
Fig. 14 - Switching Time Waveforms
Fig. 17 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
L
VDS
Vary tp to obtain
required IAS
50 kΩ
12 V
D.U.T.
Rg
0.2 μF
0.3 μF
+
- VDD
+
D.U.T.
IAS
10 V
tp
0.01 Ω
-
VDS
VGS
3 mA
Fig. 15 - Unclamped Inductive Test Circuit
IG
ID
Current sampling resistors
Fig. 18 - Gate Charge Test Circuit
S21-0987-Rev. C, 11-Oct-2021
Document Number: 92309
5
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF068N60EF
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
3
+
2
-
-
4
+
1
Rg
•
•
•
•
1 Driver gate drive
Period
P.W.
+
V
- DD
dv/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
D=
P.W.
Period
V GS = 10 V a
2
D.U.T. ISD waveform
Reverse
recovery
current
3 D.U.T. VDS
Body diode forward
current
di/dt
waveform
Diode recovery
dv/dt
Re-applied
voltage
V DD
Body diode forward drop
4 Inductor current
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 19 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?92309.
S21-0987-Rev. C, 11-Oct-2021
Document Number: 92309
6
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
TO-220 FULLPAK (High Voltage)
OPTION 1: FACILITY CODE = 9
A
F
G
Q1
E
D
ØR
A3
L1
3 x b2
3 x b1
Mold flash
bleeding
Q
L
Exposed Cu
3xb
2xe
C
Bottom view
MILLIMETERS
DIM.
MIN.
NOM.
A
4.60
4.70
4.80
b
0.70
0.80
0.91
b1
1.20
1.30
1.47
b2
1.10
1.20
1.30
C
0.45
0.50
0.63
D
15.80
15.87
15.97
e
MAX.
2.54 BSC
E
10.00
10.10
F
2.44
2.54
10.30
2.64
G
6.50
6.70
6.90
L
12.90
13.10
13.30
L1
3.13
3.23
3.33
Q
2.65
2.75
2.85
Q1
3.20
3.30
3.40
ØR
3.08
3.18
3.28
Notes
1. To be used only for process drawing
2. These dimensions apply to all TO-220 FULLPAK leadframe versions 3 leads
3. All critical dimensions should C meet Cpk > 1.33
4. All dimensions include burrs and plating thickness
5. No chipping or package damage
6. Facility code will be the 1st character located at the 2nd row of the unit marking
Revision: 08-Apr-2019
Document Number: 91359
1
For technical questions, contact: hvmos.techsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
OPTION 2: FACILITY CODE = Y
A
A1
E
ØP
n
d1
d3
D
u
L1
V
L
b3
A2
b2
c
b
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
A
4.570
4.830
0.180
0.190
A1
2.570
2.830
0.101
0.111
A2
2.510
2.850
0.099
0.112
b
0.622
0.890
0.024
0.035
b2
1.229
1.400
0.048
0.055
b3
1.229
1.400
0.048
0.055
c
0.440
0.629
0.017
0.025
D
8.650
9.800
0.341
0.386
d1
15.88
16.120
0.622
0.635
d3
12.300
12.920
0.484
0.509
E
10.360
10.630
0.408
e
2.54 BSC
0.419
0.100 BSC
L
13.200
13.730
0.520
0.541
L1
3.100
3.500
0.122
0.138
n
6.050
6.150
0.238
0.242
ØP
3.050
3.450
0.120
0.136
u
2.400
2.500
0.094
0.098
V
0.400
0.500
0.016
0.020
ECN: E19-0180-Rev. D, 08-Apr-2019
DWG: 5972
Notes
1. To be used only for process drawing
2. These dimensions apply to all TO-220 FULLPAK leadframe versions 3 leads
3. All critical dimensions should C meet Cpk > 1.33
4. All dimensions include burrs and plating thickness
5. No chipping or package damage
6. Facility code will be the 1st character located at the 2nd row of the unit marking
Revision: 08-Apr-2019
Document Number: 91359
2
For technical questions, contact: hvmos.techsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Legal Disclaimer Notice
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Disclaimer
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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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about the suitability of products for a particular application. It is the customer's responsibility to validate that a particular product
with the properties described in the product specification is suitable for use in a particular application. Parameters provided in
datasheets and / or specifications may vary in different applications and performance may vary over time. All operating
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Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited
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Revision: 01-Jan-2023
1
Document Number: 91000
