SiHF18N50D
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Vishay Siliconix
D Series Power MOSFET
FEATURES
D
TO-220 FULLPAK
• Optimal design
- Low area specific on-resistance
- Low input capacitance (Ciss)
Available
- Reduced capacitive switching losses
- High body diode ruggedness
- Avalanche energy rated (UIS)
• Optimal efficiency and operation
- Low cost
- Simple gate drive circuitry
- Low figure-of-merit (FOM): Ron x Qg
- Fast switching
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
G
S
G D S
N-Channel MOSFET
PRODUCT SUMMARY
VDS (V) at TJ max.
RDS(on) max. () at 25 °C
Note
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details
550
VGS = 10 V
Qg max. (nC)
0.28
76
Qgs (nC)
11
Qgd (nC)
17
Configuration
APPLICATIONS
• Consumer electronics
- Displays (LCD or Plasma TV)
• Server and telecom power supplies
- SMPS
• Industrial
- Welding
- Induction heating
- Motor drives
• Battery chargers
Single
ORDERING INFORMATION
Package
TO-220 FULLPAK
Lead (Pb)-free
SiHF18N50D-E3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
Drain-source voltage
Gate-source voltage
LIMIT
VDS
500
VGS
Gate-source voltage AC (f > 1 Hz)
Continuous drain current (TJ = 150 °C) e
SYMBOL
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed drain current a
ID
± 30
UNIT
V
30
18
11
A
IDM
53
0.3
W/°C
Single pulse avalanche energy b
EAS
115
mJ
Maximum power dissipation
PD
39
W
TJ, Tstg
-55 to +150
°C
Linear derating factor
Operating junction and storage temperature range
Drain-source voltage slope
TJ = 125 °C
Reverse diode dV/dt d
Soldering recommendations (peak temperature) c
Mounting torque
dV/dt
24
0.4
V/ns
For 10 s
300
°C
M3 screw
0.6
Nm
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature
b. VDD = 50 V, starting TJ = 25 °C, L = 2.3 mH, Rg = 25 , IAS = 10 A
c. 1.6 mm from case
d. ISD ID, starting TJ = 25 °C
e. Limited by maximum junction temperature
S18-0055-Rev. C, 22-Jan-18
Document Number: 91507
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For technical questions, contact: hvm@vishay.com
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SiHF18N50D
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THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum junction-to-ambient
RthJA
-
65
Maximum junction-to-case (drain)
RthJC
-
3.2
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
VDS temperature coefficient
Gate threshold voltage (N)
VDS
VGS = 0 V, ID = 250 μA
500
-
-
V
VDS/TJ
Reference to 25 °C, ID = 250 μA
-
0.58
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
3.0
-
5.0
V
Gate-source leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero gate voltage drain current
IDSS
VDS = 500 V, VGS = 0 V
-
-
1
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
10
μA
-
0.23
0.28
gfs
VDS = 50 V, ID = 9 A
-
6.4
-
S
Input capacitance
Ciss
-
1500
-
Output capacitance
Coss
Reverse transfer capacitance
Crss
VGS = 0 V,
VDS = 100 V,
f = 1.0 MHz
Effective output capacitance, energy
related a
Co(er)
Effective output capacitance, time
related b
Co(tr)
Drain-source on-state resistance
Forward transconductance
RDS(on)
VGS = 10 V
ID = 9 A
Dynamic
-
14
-
-
113
-
-
164
-
-
38
76
-
11
-
-
17
-
VGS = 0 V, VDS = 0 V to 400 V
Total gate charge
Qg
Qgs
Gate-drain charge
Qgd
Turn-on delay time
td(on)
Turn-off delay time
131
pF
Gate-source charge
Rise time
-
tr
td(off)
Fall time
tf
Gate input resistance
Rg
VGS = 10 V
ID = 9 A, VDS = 400 V
VDD = 400 V, ID = 9 A,
VGS = 10 V, Rg = 9.1
f = 1 MHz, open drain
nC
-
19
38
-
36
72
-
36
72
-
30
60
-
1.7
-
-
-
18
-
-
72
-
-
1.2
V
-
354
-
ns
-
3.9
-
μC
-
21
-
A
ns
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
IS
Pulsed diode forward current
ISM
Diode forward voltage
VSD
Reverse recovery time
trr
Reverse recovery charge
Qrr
Reverse recovery current
IRRM
MOSFET symbol
showing the
integral reverse
P - N junction diode
D
A
G
TJ = 25 °C, IS = 9 A, VGS = 0 V
TJ = 25 °C, IF = IS = 9 A,
dI/dt = 100 A/μs, VR = 20 V
S
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS
S18-0055-Rev. C, 22-Jan-18
Document Number: 91507
2
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF18N50D
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
60
3
50
40
15V
14V
13V
12V
11V
10V
9.0V
8.0V
7.0V
6.0V
TJ = 25 °C
ID = 9 A
2.5
RDS(on), Drain-to-Source
On Resistance (Normalized)
I D , Drain -to -Source Current (A)
TOP
30
20
10
2
1.5
1
VGS = 10 V
0.5
5.0 V
0
0
5
10
15
20
25
0
- 60 - 40 - 20
30
0
V DS , Drain -to -Source Voltage (V)
60
80
100 120 140 160
10 000
40
TOP
15V
14V
13V
12V
32
11V
10V
9.0V
8.0V
7.0V
24
6.0V
BOTYTOM 5.0V
TJ = 150 °C
Ciss
16
Capacitance (pF)
1000
ġ
ID , Drain-to-Source Current (A)
40
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 1 - Typical Output Characteristics
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
Coss
100
Crss
10
8
5.0 V
0
0
5
10
15
1
20
25
30
0
100
24
50
20
ġ
40
30
TJ = 150 °C
TJ = 25 °C
0
VGS, Gate-to-Source Voltage (V)
60
10
300
400
500
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 2 - Typical Output Characteristics
20
200
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
ID, Drain- to-Source Current (A)
20
TJ, Junction Temperature (°C)
VDS = 400 V
VDS = 250 V
VDS = 100 V
16
12
8
4
0
0
5
10
15
20
VGS, Gate
- -to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S18-0055-Rev. C, 22-Jan-18
25
0
10
20
30
40
50
60
70
Qg, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Document Number: 91507
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SiHF18N50D
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20.0
TJ = 150 °C
16.0
ID, Drain Current (A)
ISD, Reverse Drain Current (A)
100 ġ
10 ġ
ġ
TJ = 25 °C
ġ
1ġ
12.0
8.0
4.0
VGS = 0 ġV
0.1 ġ
0.2
0.4
0.6
0.8
1
1.2
1.4
25
1.6
50
VSD, Source-Drain Voltage (V)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
100
125
150
Fig. 9 - Maximum Drain Current vs. Case Temperature
625 ġ
1000
Operation in this area
limited by RDS(on)
10
100 μs
Limited by RDS(on)*
1 ms
VDS, Drain-to-Source
Breakdown Voltage (V)
600 ġ
100
ID, Drain Current (A)
75
TJ, Case Temperature (°C)
575 ġ
550 ġ
525 ġ
1
500 ġ
10 ms
TC = 25 °C
TJ = 150 °C
Single Pulse
BVDSS Limited
475 ġ
- 60 - 40 - 20
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Fig. 8 - Maximum Safe Operating Area
1000
0
20
40
60
80
100 120 140 160
TJ, Junction Temperature (°C)
Fig. 10 - Typical Drain-to-Source Voltage vs. Temperature
1
Normalized Effective Transient
Thermal Impedance
Duty cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single pulse
0.01
0.0001
0.001
0.01
Pulse Time (s)
0.1
1
Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case
S18-0055-Rev. C, 22-Jan-18
Document Number: 91507
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For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF18N50D
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Vishay Siliconix
RD
VDS
QG
10 V
VGS
D.U.T.
RG
QGS
+
- VDD
QGD
VG
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Charge
Fig. 12 - Switching Time Test Circuit
Fig. 16 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
VDS
90 %
50 kΩ
12 V
0.2 µF
0.3 µF
10 %
VGS
+
D.U.T.
td(on)
-
VDS
td(off) tf
tr
VGS
3 mA
Fig. 13 - Switching Time Waveforms
IG
ID
Current sampling resistors
L
Vary tp to obtain
required IAS
VDS
Fig. 17 - Gate Charge Test Circuit
D.U.T
RG
+
-
IAS
V DD
10 V
0.01 Ω
tp
Fig. 14 - Unclamped Inductive Test Circuit
VDS
tp
VDD
VDS
IAS
Fig. 15 - Unclamped Inductive Waveforms
S18-0055-Rev. C, 22-Jan-18
Document Number: 91507
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For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF18N50D
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Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 18 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91507.
S18-0055-Rev. C, 22-Jan-18
Document Number: 91507
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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Package Information
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Vishay Siliconix
TO-220 FULLPAK (High Voltage)
OPTION 1: FACILITY CODE = 9
A
F
G
Q1
E
D
ØR
A3
L1
3 x b2
3 x b1
Mold flash
bleeding
Q
L
Exposed Cu
3xb
2xe
C
Bottom view
MILLIMETERS
DIM.
MIN.
NOM.
A
4.60
4.70
4.80
b
0.70
0.80
0.91
b1
1.20
1.30
1.47
b2
1.10
1.20
1.30
C
0.45
0.50
0.63
D
15.80
15.87
15.97
e
MAX.
2.54 BSC
E
10.00
10.10
F
2.44
2.54
10.30
2.64
G
6.50
6.70
6.90
L
12.90
13.10
13.30
L1
3.13
3.23
3.33
Q
2.65
2.75
2.85
Q1
3.20
3.30
3.40
ØR
3.08
3.18
3.28
Notes
1. To be used only for process drawing
2. These dimensions apply to all TO-220 FULLPAK leadframe versions 3 leads
3. All critical dimensions should C meet Cpk > 1.33
4. All dimensions include burrs and plating thickness
5. No chipping or package damage
6. Facility code will be the 1st character located at the 2nd row of the unit marking
Revision: 08-Apr-2019
Document Number: 91359
1
For technical questions, contact: hvmos.techsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
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Vishay Siliconix
OPTION 2: FACILITY CODE = Y
A
A1
E
ØP
n
d1
d3
D
u
L1
V
L
b3
A2
b2
c
b
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
A
4.570
4.830
0.180
0.190
A1
2.570
2.830
0.101
0.111
A2
2.510
2.850
0.099
0.112
b
0.622
0.890
0.024
0.035
b2
1.229
1.400
0.048
0.055
b3
1.229
1.400
0.048
0.055
c
0.440
0.629
0.017
0.025
D
8.650
9.800
0.341
0.386
d1
15.88
16.120
0.622
0.635
d3
12.300
12.920
0.484
0.509
E
10.360
10.630
0.408
e
2.54 BSC
0.419
0.100 BSC
L
13.200
13.730
0.520
0.541
L1
3.100
3.500
0.122
0.138
n
6.050
6.150
0.238
0.242
ØP
3.050
3.450
0.120
0.136
u
2.400
2.500
0.094
0.098
V
0.400
0.500
0.016
0.020
ECN: E19-0180-Rev. D, 08-Apr-2019
DWG: 5972
Notes
1. To be used only for process drawing
2. These dimensions apply to all TO-220 FULLPAK leadframe versions 3 leads
3. All critical dimensions should C meet Cpk > 1.33
4. All dimensions include burrs and plating thickness
5. No chipping or package damage
6. Facility code will be the 1st character located at the 2nd row of the unit marking
Revision: 08-Apr-2019
Document Number: 91359
2
For technical questions, contact: hvmos.techsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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