SIHF8N50L-E3

SiHF8N50L www.vishay.com Vishay Siliconix Power MOSFET FEATURES D TO-220 FULLPAK • Low figure-of-merit Ron x Qg • 100 % avalanche tested Available • Gate charge improved G • trr/Qrr improved • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 S G D S Note * This datasheet provides information about parts that are RoHS-compliant and / or parts that are non-RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details. N-Channel MOSFET        PRODUCT SUMMARY VDS (V) at TJ max. RDS(on) () 560 VGS = 10 V Qg max. (nC) 1 34 Qgs (nC) 7.8 Qgd (nC) 10.4 Configuration Single ORDERING INFORMATION Package Lead (Pb)-free TO-220 FULLPAK SiHF8N50L-E3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 500 Gate-Source Voltage VGS ± 30 Continuous Drain Current a VGS at 10 V TC = 25 °C Pulsed Drain Current b ID 8 IDM 22 Linear Derating Factor Single Pulse Avalanche Energy c Maximum Power Dissipation TC = 25 °C Peak Diode Recovery dV/dt d Operating Junction and Storage Temperature Range Soldering Recommendations (Peak temperature) e Mounting Torque UNIT V A 0.32 W/°C EAS 180 mJ PD 40 W dV/dt 24 V/ns TJ, Tstg -55 to +150 For 10 s 300 M3 screw 0.6 °C Nm Notes a. Drain current limited by maximum junction temperature. b. Repetitive rating; pulse width limited by maximum junction temperature. c. VDD = 50 V, starting TJ = 25 °C, L = 10 mH, Rg = 25 , IAS = 6 A. d. ISD  8 A, dI/dt  460 A/μs, VDD  VDS, TJ  150 °C. e. 1.6 mm from case. THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 65 Maximum Junction-to-Case (Drain) RthJC - 3.1 S16-1602-Rev. C, 15-Aug-16 UNIT °C/W Document Number: 91387 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHF8N50L www.vishay.com Vishay Siliconix SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage VDS VGS = 0 V, ID = 250 μA 500 - - V VDS/TJ Reference to 25 °C, ID = 1 mA - 0.5 - V/°C VGS(th) VDS = VGS, ID = 250 μA 3.0 - 5.0 V Gate-Source Leakage IGSS VGS = ± 30 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 500 V, VGS = 0 V - - 50 VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 250 Drain-Source On-State Resistance Forward Transconductance μA - 0.85 1  gfs VDS = 50 V, ID = 3 A - 2 - S VGS = 0 V, VDS = 25 V, f = 1.0 MHz - 873 - - 105 - - 11 - RDS(on) VGS = 10 V ID = 4.0 A Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time - 22 34 - 7.8 - Qgd - 10.4 - td(on) - 17.3 - tr td(off) Fall Time tf Gate Input Resistance Rg VGS = 10 V ID = 6 A, VDS = 400 V VDD = 250 V, ID = 6 A RG = 14 VGS = 10 V f = 1 MHz, open drain pF nC - 35 - - 23.6 - - 17 - - 0.7 - - - 8 - - 22 - - 1.5 V - 63 - ns - 114 - nC - 3.3 - A ns  Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Current ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Body Diode Reverse Recovery Current IRRM S16-1602-Rev. C, 15-Aug-16 MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = 8 A, VGS = 0 V TJ = 25 °C, IF = IS, dI/dt = 100 A/μs, VR = 15 V Document Number: 91387 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHF8N50L www.vishay.com Vishay Siliconix ID, Drain-to-Source Current (A) 20 RDS(on), Drain-to-Source On Resistance (Normalized) TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) VGS TOP 15 V 14 V 13 V 12 V 11 V 10 V 9.0 V 8.0 V 7.0 V 6.0 V BOTTOM 5.0 V 16 12 TJ = 25 °C 8 4 7.0 V 0 0 5 10 15 20 25 30 3 ID = 8 A 2.5 2 1.5 1 0.5 VGS = 10 V 0 - 60 - 40 - 20 VDS, Drain-to-Source Voltage (V) Fig. 4 - Normalized On-Resistance vs. Temperature 15 V 14 V 13 V 12 V 11 V 10 V 9.0 V 8.0 V 7.0 V 6.0 V BOTTOM 5.0 V VGS = 0 V, f = 1MHz Ciss = Cgs + Cgd Cds SHORTED Crss = Cgd Coss = Cds + Cgd TOP 6 TJ = 150 °C C, Capacitance (pF) ID, Drain-to-Source Current (A) 1600 VGS 9 7.0 V 3 1200 Ciss Coss 800 400 Crss 0 0 0 5 10 15 20 25 30 1 10 100 1000 VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 2 - Typical Output Characteristics 16 20 VGS, Gate-to-Source Voltage (V) ID, Drain-to-Source Current (A) 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 1 - Typical Output Characteristics 12 0 14 12 10 8 TJ = 150 °C 6 TJ = 25 °C 4 2 0 VDS = 400 V VDS = 250 V VDS = 100 V ID = 8 A 16 12 8 4 0 5 6 7 8 9 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S16-1602-Rev. C, 15-Aug-16 10 0 5 10 15 20 25 30 35 QG, Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91387 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHF8N50L www.vishay.com Vishay Siliconix ISD, Reverse Drain Current (A) 100 RD VDS VGS 10 D.U.T. RG TJ = 150 °C + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % TJ = 25 °C 1 Fig. 9a - Switching Time Test Circuit VGS = 0 V 0.1 0.2 0.4 0.6 0.8 1 1.2 1.4 VDS 1.6 90 % VSD, Source-to-Drain Voltage (V) Fig. 7 - Typical Source-Drain Diode Forward Voltage 10 % VGS ID, Drain-to-Source Current (A) 100 t d(on) OPERATION IN THIS AREA LIMITED BY RDS(on) tr t d(off) t f Fig. 9b - Switching Time Waveforms 10 100 µs 1 ms 1 TC = 25 °C TJ = 150 °C Single Pulse 0.1 10 10 ms 100 1000 10 000 VDS, Drain-to-Source Voltage (V) Normalized Transient Thermal Impedance (ZthJC) Fig. 8 - Maximum Safe Operating Area 1 D = 0.50 0.20 0.1 PDM 0.10 t1 t2 0.05 0.02 0.01 0.0001 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC SINGLE PULSE (THERMAL RESPONSE) 0.001 0.01 0.1 1 t1 , Rectangular Pulse Duration (s) Fig. 10 - Maximum Effective Transient Thermal Impedance, Junction-to-Case S16-1602-Rev. C, 15-Aug-16 Document Number: 91387 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHF8N50L www.vishay.com Vishay Siliconix Current regulator Same type as D.U.T. 50 kΩ 15 V 12 V 0.2 µF 0.3 µF Driver L VDS D.U.T. D.U.T. RG + A - VDD IAS 20 V tp + V - DS VGS A 3 mA 0.01 Ω IG ID Current sampling resistors Fig. 11a - Unclamped Inductive Test Circuit Fig. 12b - Gate Charge Test Circuit V DS tp I AS Fig. 11b - Unclamped Inductive Waveforms QG VGS QGS QGD VG Charge Fig. 12a - Basic Gate Charge Waveform S16-1602-Rev. C, 15-Aug-16 Document Number: 91387 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHF8N50L www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 13 - For N-Channel          Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91387. S16-1602-Rev. C, 15-Aug-16 Document Number: 91387 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix TO-220 FULLPAK (High Voltage) OPTION 1: FACILITY CODE = 9 A F G Q1 E D ØR A3 L1 3 x b2 3 x b1 Mold flash bleeding Q L Exposed Cu 3xb 2xe C Bottom view MILLIMETERS DIM. MIN. NOM. A 4.60 4.70 4.80 b 0.70 0.80 0.91 b1 1.20 1.30 1.47 b2 1.10 1.20 1.30 C 0.45 0.50 0.63 D 15.80 15.87 15.97 e MAX. 2.54 BSC E 10.00 10.10 F 2.44 2.54 10.30 2.64 G 6.50 6.70 6.90 L 12.90 13.10 13.30 L1 3.13 3.23 3.33 Q 2.65 2.75 2.85 Q1 3.20 3.30 3.40 ØR 3.08 3.18 3.28 Notes 1. To be used only for process drawing 2. These dimensions apply to all TO-220 FULLPAK leadframe versions 3 leads 3. All critical dimensions should C meet Cpk > 1.33 4. All dimensions include burrs and plating thickness 5. No chipping or package damage 6. Facility code will be the 1st character located at the 2nd row of the unit marking Revision: 08-Apr-2019 Document Number: 91359 1 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix OPTION 2: FACILITY CODE = Y A A1 E ØP n d1 d3 D u L1 V L b3 A2 b2 c b MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. A 4.570 4.830 0.180 0.190 A1 2.570 2.830 0.101 0.111 A2 2.510 2.850 0.099 0.112 b 0.622 0.890 0.024 0.035 b2 1.229 1.400 0.048 0.055 b3 1.229 1.400 0.048 0.055 c 0.440 0.629 0.017 0.025 D 8.650 9.800 0.341 0.386 d1 15.88 16.120 0.622 0.635 d3 12.300 12.920 0.484 0.509 E 10.360 10.630 0.408 e 2.54 BSC 0.419 0.100 BSC L 13.200 13.730 0.520 0.541 L1 3.100 3.500 0.122 0.138 n 6.050 6.150 0.238 0.242 ØP 3.050 3.450 0.120 0.136 u 2.400 2.500 0.094 0.098 V 0.400 0.500 0.016 0.020 ECN: E19-0180-Rev. D, 08-Apr-2019 DWG: 5972 Notes 1. To be used only for process drawing 2. These dimensions apply to all TO-220 FULLPAK leadframe versions 3 leads 3. All critical dimensions should C meet Cpk > 1.33 4. All dimensions include burrs and plating thickness 5. No chipping or package damage 6. Facility code will be the 1st character located at the 2nd row of the unit marking Revision: 08-Apr-2019 Document Number: 91359 2 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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ALL RIGHTS RESERVED Revision: 01-Jan-2022 1 Document Number: 91000