SIHFL110TR-GE3

IRFL110, SiHFL110 www.vishay.com Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • • • • • • • • 100 RDS(on) () VGS = 10 V 0.54 Qg (Max.) (nC) 8.3 Qgs (nC) 2.3 Qgd (nC) 3.8 Configuration Single D DESCRIPTION Third generation power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SOT-223 package is designed for surface-mounting using vapor phase, infrared, or wave soldering techniques. Its unique package design allows for easy automatic pick-and-place as with other SOT or SOIC packages but has the added advantage of improved thermal performance due to an enlarged tab for heatsinking. Power dissipation of greater than 1.25 W is possible in a typical surface mount application. SOT-223 D G D S G Marking code: FB Surface mount Available in tape and reel Dynamic dV/dt rating Repetitive avalanche rated Fast switching Ease of paralleling Available Simple drive requirements Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 S N-Channel MOSFET ORDERING INFORMATION Package SOT-223 SOT-223 Lead (Pb)-free and Halogen-free SiHFL110-GE3 SiHFL110TR-GE3 a IRFL110PbF IRFL110TRPbF a SiHFL110-E3 SiHFL110T-E3 a Lead (Pb)-free Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER Drain-Source Voltage SYMBOL VDS LIMIT 100 Gate-Source Voltage VGS ± 20 Continuous Drain Current Pulsed Drain VGS at 10 V TC = 25 °C TC = 100 °C Current a ID IDM UNIT V 1.5 0.96 A 12 Linear Derating Factor 0.025 Linear Derating Factor (PCB Mount) e 0.017 W/°C Single Pulse Avalanche Energy b EAS 150 Repetitive Avalanche Current a IAR 1.5 A Repetitive Avalanche Energy a EAR 0.31 mJ Maximum Power Dissipation TC = 25 °C Maximum Power Dissipation (PCB Mount) e TA = 25 °C Peak Diode Recovery dV/dt c Operating Junction and Storage Temperature Range for 10 s Soldering Recommendations (Peak Temperature) d Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 25 V, starting TJ = 25 °C, L = 25 mH, Rg = 25 , IAS = 3.0 A (see fig. 12). c. ISD  5.6 A, dI/dt  75 A/μs, VDD  VDS, TJ  150 °C. d. 1.6 mm from case. e. When mounted on 1" square PCB (FR-4 or G-10 material). S14-1685-Rev. E, 18-Aug-14 PD 3.1 2.0 dV/dt 5.5 TJ, Tstg -55 to +150 300 mJ W V/ns °C Document Number: 91192 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFL110, SiHFL110 www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS SYMBOL MIN. TYP. MAX. Maximum Junction-to-Ambient  (PCB Mount)a PARAMETER RthJA - - 60 Maximum Junction-to-Case (Drain) RthJC - - 40 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage VDS VGS = 0 V, ID = 250 μA 100 - - V VDS/TJ Reference to 25 °C, ID = 1 mA - 0.63 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V Gate-Source Leakage IGSS VGS = ± 20 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 100 V, VGS = 0 V - - 25 VDS = 80 V, VGS = 0 V, TJ = 125 °C - - 250 Drain-Source On-State Resistance Forward Transconductance μA - - 0.54  gfs VDS = 50 V, ID = 0.90 A 1.1 - - S VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 - 180 - - 81 - - 15 - - - 8.3 - - 2.3 RDS(on) ID = 0.90 A b VGS = 10 V Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd - - 3.8 Turn-On Delay Time td(on) - 6.9 - tr - 16 - - 15 - - 9.4 - - 4.0 - - 6.0 - - - 1.5 - - 12 Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance td(off) VGS = 10 V ID = 5.6 A, VDS = 80 V, see fig. 6 and 13 b VDD = 50 V, ID = 5.6 A, Rg = 24 , RD = 8.4 , see fig. 10 b tf LD LS Between lead, 6 mm (0.25") from package and center of die contact pF nC ns D nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Current a Body Diode Voltage IS ISM VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the  integral reverse p - n junction diode D A G TJ = 25 °C, IS = 1.5 A, VGS = 0 S Vb TJ = 25 °C, IF = 5.6 A, dI/dt = 100 A/μs b - - 2.5 V - 100 200 ns - 0.44 0.88 μC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width  300 μs; duty cycle  2 %. S14-1685-Rev. E, 18-Aug-14 Document Number: 91192 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFL110, SiHFL110 www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 2 - Typical Output Characteristics, TC = 150 °C S14-1685-Rev. E, 18-Aug-14 Fig. 3 - Typical Transfer Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 91192 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFL110, SiHFL110 www.vishay.com Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage S14-1685-Rev. E, 18-Aug-14 Vishay Siliconix Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area Document Number: 91192 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFL110, SiHFL110 www.vishay.com Vishay Siliconix RD VDS VGS D.U.T. Rg + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a -Switching Time Test Circuit VDS 90 % 10 % VGS td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature tr td(off) tf Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case S14-1685-Rev. E, 18-Aug-14 Document Number: 91192 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFL110, SiHFL110 www.vishay.com Vishay Siliconix L Vary tp to obtain required IAS VDS VDS tp VDD D.U.T Rg + - I AS V DD VDS 10 V 0.01 Ω tp Fig. 12a - Unclamped Inductive Test Circuit IAS Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG 10 V 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform S14-1685-Rev. E, 18-Aug-14 Fig. 13b - Gate Charge Test Circuit Document Number: 91192 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFL110, SiHFL110 www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig.14 - For N-Channel         Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91192. S14-1685-Rev. E, 18-Aug-14 Document Number: 91192 7 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix SOT-223 (HIGH VOLTAGE) B D A 3 0.08 (0.003) B1 C 0.10 (0.004) M C B M A 4 3 H E 0.20 (0.008) M C A M L1 1 2 3 4xL 3xB e θ 0.10 (0.004) M C B M e1 4xC MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. A 1.55 1.80 0.061 0.071 0.033 B 0.65 0.85 0.026 B1 2.95 3.15 0.116 0.124 C 0.25 0.35 0.010 0.014 D 6.30 6.70 0.248 0.264 E 3.30 3.70 0.130 e 2.30 BSC e1 4.60 BSC 0.181 BSC H 6.71 7.29 0.264 L 0.91 - 0.036 L1 θ 0.061 BSC - 0.146 0.0905 BSC 0.287 0.0024 BSC 10' - 10' ECN: S-82109-Rev. A, 15-Sep-08 DWG: 5969 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension do not include mold flash. 4. Outline conforms to JEDEC outline TO-261AA. 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