SiHFPS40N50L
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Power MOSFET
FEATURES
D
• Superfast body diode eliminates the need for
External diodes in ZVS applications
Super-247
• Lower gate charge results in simpler drive
requirements
G
• Enhanced dV/dt capabilities offer improved
ruggedness
S
D
G
S
• Higher gate voltage threshold offers improved noise
immunity
N-Channel MOSFET
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
PRODUCT SUMMARY
VDS (V)
500
RDS(on) (Ω)
VGS = 10 V
APPLICATIONS
0.087
380
• Zero voltage switching SMPS
Qgs (nC)
80
• Telecom and server power supplies
Qgd (nC)
190
• Uninterruptible power supplies
Qg (Max.) (nC)
Configuration
Single
• Motor control applications
ORDERING INFORMATION
Package
Lead (Pb)-free and halogen free
Super-247
SiHFPS40N50L-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-source voltage
VDS
500
Gate-source voltage
VGS
± 30
VGS at 10 V
Continuous drain current
TC = 25 °C
TC = 100 °C
Pulsed drain current a
ID
IDM
Linear derating factor
b
UNIT
V
46
29
A
180
4.3
W/°C
mJ
EAS
920
Repetitive avalanche current a
IAR
46
A
Repetitive avalanche Energy a
EAR
54
mJ
Single pulse avalanche energy
Maximum power dissipation
TC = 25 °C
Peak diode recovery dV/dt c
Operating junction and storage temperature range
Soldering recommendations (peak temperature)
for 10 s
PD
540
W
dV/dt
34
V/ns
TJ, Tstg
- 55 to + 150
300 d
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Starting TJ = 25 °C, L = 0.86 mH, Rg = 25 Ω, IAS = 46 A (see fig. 12)
c. ISD ≤ 46 A, dI/dt ≤ 550 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
d. 1.6 mm from case
S21-0019-Rev. D, 18-Jan-2021
Document Number: 91260
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THERMAL RESISTANCE RATINGS
PARAMETER
junction-to-ambient a
SYMBOL
TYP.
MAX.
40
RthJA
-
Case-to-sink, flat, greased surface
RthCS
0.24
-
Maximum junction-to-case (drain) a
RthJC
-
0.23
Maximum
UNIT
°C/W
Note
a. Rth is measured at TJ approximately 90 °C
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
VDS temperature coefficient
Gate-source threshold voltage
Gate-source leakage
Zero gate voltage drain current
Drain-source on-state resistance
Forward transconductance
VDS
VGS = 0 V, ID = 250 μA
500
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.60
-
VGS(th)
VDS = VGS, ID = 250 μA
3.0
-
5.0
V/°C
V
VGS = ± 30 V
-
-
± 100
VDS = 500 V, VGS = 0 V
-
-
50
nA
μA
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
2.0
mA
-
0.087
0.100
Ω
21
-
-
S
-
8110
-
-
960
-
-
130
-
VDS = 1.0 V, f = 1.0 MHz
-
11200
-
VDS = 400 V, f = 1.0 MHz
-
240
-
-
440
-
-
310
380
IGSS
IDSS
RDS(on)
ID = 28 A b
VGS = 10 V
gfs
VDS = 50 V, ID = 46 A
Input capacitance
Ciss
Output capacitance
Coss
Reverse transfer capacitance
Crss
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
Output capacitance
Coss
Dynamic
Effective output capacitance
Effective output capacitance
(energy related)
Coss eff.
Total gate charge
Qg
Qgs
Gate-drain charge
Internal gate resistance
Qgd
Rg
Turn-on delay time
td(on)
Turn-off delay time
Fall time
VDS = 0 V to 400 V c
Coss eff. (ER)
Gate-source charge
Rise time
VGS = 0 V
tr
td(off)
VGS = 10 V
ID = 46 A, VDS = 400 V,
see fig. 7 and 15 b
f = 1 MHz, open drain
VDD = 250 V, ID = 46 A,
Rg = 0.85 Ω, VGS = 10 V,
see fig. 14a and 14b b
tf
pF
-
-
-
-
80
nC
-
-
-
0.90
190
-
Ω
-
27
-
-
170
-
-
50
-
-
69
-
-
-
46
-
-
180
ns
Drain-source body diode characteristics
Continuous source-drain diode current
IS
Pulsed diode forward current a
ISM
Body diode voltage
VSD
Body diode reverse recovery time
trr
Body diode reverse recovery charge
Qrr
Reverse recovery current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 46 A, VGS = 0 V b
-
-
1.5
TJ = 25 °C, IF = 46 A
-
170
250
TJ = 125 °C, dI/dt = 100 A/μs b
-
220
330
TJ = 25 °C, IS = 46 A, VGS = 0 V b
-
705
1060
TJ = 125 °C, dI/dt = 100 A/μs b
-
1.3
2.0
TJ = 25 °C
-
9.0
-
V
ns
nC
A
Forward turn-on time
ton
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 400 μs; duty cycle ≤ 2 %
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS
Coss eff. (ER) is a fixed capacitance that stores the same energy as Coss while VDS is rising from 0 % to 80 % VDS
S21-0019-Rev. D, 18-Jan-2021
Document Number: 91260
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SiHFPS40N50L
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
RDS(on) , Drain-to-Source On Resistance
(Normalized)
1000
I D , Drain-to-Source Current (A)
TOP
100
10
1
4.5V
0.1
20μs PULSE WIDTH
TJ = 25 °C
0.01
0.1
1
10
100
3.0
ID = 47A
2.5
2.0
1.5
1.0
0.5
1000000
C, Capacitance(pF)
I D , Drain-to-Source Current (A)
100000
10
4.5V
Coss = Cds + Cgd
10000
Ciss
1000
Coss
100
1
20µs PULSE WIDTH
TJ = 150 °C
0.1
0.1
1
10
Crss
10
1
10
100
Fig. 2 - Typical Output Characteristics
100
1000
VDS, Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
40
1000
35
100
30
TJ = 150° C
Energy (µJ)
I D , Drain-to-Source Current (A)
80 100 120 140 160
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
TOP
100
20 40 60
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 1 - Typical Output Characteristics
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM4.5V
0
TJ , Junction Temperature ( ° C)
VDS , Drain-to-Source Voltage (V)
1000
VGS = 10V
0.0
-60 -40 -20
10
TJ = 25 ° C
25
20
15
10
1
5
0.1
V DS= 50V
20µs PULSE WIDTH
4
5
6
7
8
9
10
0
11
VGS , Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S21-0019-Rev. D, 18-Jan-2021
0
100
200
300
400
500
600
VDS, Drain-to-Source Voltage (V)
Fig. 6 - Typical Output Capacitance Stored Energy vs. VDS
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SiHFPS40N50L
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50
ID = 47A
V DS= 400V
V DS= 250V
V DS= 100V
15
40
ID , Drain Current (A)
VGS , Gate-to-Source Voltage (V)
20
Vishay Siliconix
10
5
30
20
10
0
0
0
100
200
300
400
25
50
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
75
ISD , Reverse Drain Current (A)
VDS
VGS
100
150
RD
D.U.T.
RG
10
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
TJ = 25 ° C
1
0.1
0.2
125
Fig. 9 - Maximum Drain Current vs. Case Temperature
1000
TJ = 150° C
100
TC , Case Temperature ( °C)
QG , Total Gate Charge (nC)
Fig. 10a - Switching Time Test Circuit
V GS = 0 V
0.7
1.2
1.7
VDS
2.2
VSD ,Source-to-Drain Voltage (V)
90 %
Fig. 8 - Typical Source Drain Diode Forward Voltage
10 %
VGS
td(on)
tr
td(off) tf
Fig. 10b - Switching Time Waveforms
S21-0019-Rev. D, 18-Jan-2021
Document Number: 91260
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SiHFPS40N50L
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Vishay Siliconix
Thermal Response(Z thJC )
1
0.1
D = 0.50
0.20
0.10
0.05
0.01
PDM
0.02
0.01
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D = t1 / t 2
2. Peak TJ = P DM x Z thJC + TC
0.001
0.00001
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
ID , Drain Current (A)
15 V
100
Driver
L
VDS
D.U.T.
RG
+
A
- VDD
IAS
20 V
tp
10us
100us
10
1ms
0.01 Ω
TC = 25 °C
TJ = 150 °C
Single Pulse
Fig. 12a - Unclamped Inductive Test Circuit
1
10ms
10
100
100
VDS , Drain-to-Source Voltage (V)
tp
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
2000
EAS , Single Pulse Avalanche Energy (mJ)
VDS
TOP
BOTTOM
ID
21A
30A
46A
1500
IAS
1000
Fig. 12b - Unclamped Inductive Waveforms
500
0
25
50
75
100
125
150
Starting TJ , Junction Temperature( °C)
Fig. 12d - Maximum Safe Operating Area
S21-0019-Rev. D, 18-Jan-2021
Document Number: 91260
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SiHFPS40N50L
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Current regulator
Same type as D.U.T.
12 V
QG
VGS
50 kΩ
0.2 µF
QGS
0.3 µF
QGD
+
D.U.T.
-
VDS
VG
VGS
3 mA
IG
ID
Current sampling resistors
Charge
Fig. 13b - Basic Gate Charge Waveform
Fig. 13a - Gate Charge Test Circuit
S21-0019-Rev. D, 18-Jan-2021
Document Number: 91260
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SiHFPS40N50L
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Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91260.
S21-0019-Rev. D, 18-Jan-2021
Document Number: 91260
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Package Information
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Vishay Siliconix
TO-274AA (High Voltage)
VERSION 1: FACILITY CODE = Y
B
A
E
E4
A
D2
E1
A1
R
D1
D
L1
L
Detail “A”
C
b
e
A2
0.10 (0.25) M B A M
10°
b4
b2
Lead Tip
5°
Detail “A”
Scale: 2:1
MILLIMETERS
INCHES
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
DIM.
MIN.
MAX.
MIN.
A
4.70
5.30
0.185
0.209
D1
15.50
16.10
0.610
0.634
A1
1.50
2.50
0.059
0.098
D2
0.70
1.30
0.028
0.051
A2
2.25
2.65
0.089
0.104
E
15.10
16.10
0.594
0.634
13.30
13.90
0.524
0.547
b
1.30
1.60
0.051
0.063
E1
b2
1.80
2.20
0.071
0.087
e
5.45 BSC
MAX.
0.215 BSC
b4
3.00
3.25
0.118
0.128
L
13.70
14.70
0.539
0.579
c (1)
0.38
0.89
0.015
0.035
L1
1.00
1.60
0.039
0.063
D
19.80
20.80
0.780
0.819
R
2.00
3.00
0.079
0.118
Notes
• Dimensioning and tolerancing per ASME Y14.5M-1994
• Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outer extremes of the plastic body
• Outline conforms to JEDEC® outline to TO-274AA
(1) Dimension measured at tip of lead
Revision: 19-Oct-2020
Document Number: 91365
1
For technical questions, contact: hvm@vishay.com
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
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Vishay Siliconix
VERSION 2: FACILITY CODE = N
A
E
A
E3
B
D
D1
D2
E2
Q
A2
L1
F
F
H
H
C
G
L
G
A1
e
b
3x
0.25 M B A M
b1
C
b3
E4
E1
b’, b2, b4
C
C’
Base metal
b, b1, b3
Plating
SECTION "F-F", "G-G" AND "H-H"
SCALE: NONE
MILLIMETERS
MILLIMETERS
DIM.
MIN.
MAX.
DIM.
MIN.
MAX.
A
4.83
5.21
D1
16.25
17.65
A1
2.29
2.54
D2
0.50
0.80
A2
1.91
2.16
E
15.75
16.13
b’
1.07
1.28
E1
13.10
14.15
b
1.07
1.33
E2
3.68
5.10
b1
1.91
2.41
E3
1.00
1.90
b2
1.91
2.16
E4
12.38
13.43
b3
2.87
3.38
e
b4
2.87
3.13
N
c’
0.55
0.65
L
19.81
c
0.55
0.68
L1
3.70
4.00
D
20.80
21.10
Q
5.49
6.00
5.44 BSC
3
20.32
ECN: E20-0538-Rev. C, 19-Oct-2020
DWG: 5975
Notes
• Dimensioning and tolerancing per ASME Y14.5M-1994
• Outline conforms to JEDEC® outline to TO-274AD
• Dimensions are measured in mm, angles are in degree
• Metal surfaces are tin plated, except area of cut
Revision: 19-Oct-2020
Document Number: 91365
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Disclaimer
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited
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