SiHFPS40N60K
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Power MOSFET
FEATURES
D
• Low gate charge Qg results in simple drive
requirement
Super-247
• Improved gate, avalanche and dynamic dV/dt
ruggedness
G
• Fully
characterized
capacitance
avalanche voltage and current
S
D
G
S
• Enhanced body diode dV/dt capability
N-Channel MOSFET
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
PRODUCT SUMMARY
VDS (V)
APPLICATIONS
600
RDS(on) (Ω)
and
VGS = 10 V
• Hard switching primary or PFC switch
0.110
330
• Switch mode power supply (SMPS)
Qgs (nC)
84
• Uninterruptible power supply
Qgd (nC)
150
• High speed power switching
Qg (Max.) (nC)
Configuration
Single
• Motor drive
ORDERING INFORMATION
Package
Super-247
Lead (Pb)-free and halogen-free
SiHFPS40N60K-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-source voltage
VDS
600
Gate-source voltage
VGS
± 30
VGS at 10 V
Continuous drain current
TC = 25 °C
Pulsed drain current a
V
40
ID
TC = 100 °C
UNIT
A
24
IDM
160
4.5
W/°C
Single pulse avalanche energy b
EAS
600
mJ
Repetitive avalanche current a
IAR
40
A
EAR
57
mJ
PD
570
W
dV/dt
7.5
V/ns
TJ, Tstg
- 55 to + 150
Linear derating factor
Repetitive avalanche
energy a
TC = 25 °C
Maximum power dissipation
Peak diode recovery dV/dt c
Operating junction and storage temperature range
Soldering recommendations (peak temperature)
°C
300 d
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Starting TJ = 25 °C, L = 0.84 mH, Rg = 25 Ω, IAS = 38 A, dV/dt = 5.5 V/ns (see fig. 12a)
c. ISD ≤ 38 A, dI/dt ≤ 150 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
d. 1.6 mm from case
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum junction-to-ambient
Case-to-sink, flat, greased surface
Maximum junction-to-case (drain)
S21-0019-Rev. C, 18-Jan-2021
SYMBOL
TYP.
MAX.
UNIT
RthJA
RthCS
RthJC
0.24
-
40
0.22
°C/W
Document Number: 91261
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SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
VDS temperature coefficient
Gate-source threshold voltage
VDS
VGS = 0 V, ID = 250 μA
600
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.63
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
3.0
-
5.0
V
Gate-source leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero gate voltage drain current
IDSS
VDS = 600 V, VGS = 0 V
-
-
50
VDS = 480 V, VGS = 0 V, TJ = 125 °C
-
-
250
Drain-source on-state resistance
Forward transconductance
μA
-
0.110
0.130
Ω
gfs
VDS = 50 V, ID = 24 A b
21
-
-
S
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
-
7970
-
-
750
-
RDS(on)
ID = 24 A b
VGS = 10 V
Dynamic
Input capacitance
Ciss
Output capacitance
Coss
Reverse transfer capacitance
Crss
Output capacitance
Effective output capacitance
Coss
Total gate charge
Qg
Gate-source charge
Qgs
Gate-drain charge
Qgd
Turn-on delay time
td(on)
Rise time
Turn-off delay time
Fall time
VGS = 0 V
Coss eff.
-
75
-
VDS = 1.0 V, f = 1.0 MHz
-
9440
-
VDS = 480 V, f = 1.0 MHz
-
200
-
VDS = 0 V to 480 V c
-
260
-
-
-
330
ID = 38 A, VDS = 480 V,
see fig. 6 and 13 b
VGS = 10 V
tr
VDD = 300 V, ID = 38 A,
RG = 4.3 Ω, see fig. 10 b
td(off)
tf
-
-
84
-
-
150
-
47
-
-
110
-
-
97
-
-
60
-
-
-
40
-
-
160
pF
nC
ns
Drain-source body diode characteristics
Continuous source-drain diode current
IS
Pulsed diode forward current a
ISM
Body diode voltage
VSD
Body diode reverse recovery time
Body diode reverse recovery charge
Body diode recovery current
Forward turn-on time
trr
Qrr
IRRM
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 38 A, VGS = 0 V b
TJ = 25 °C
TJ = 125 °C
TJ = 25 °C
IF = 38 A, dI/dt = 100
A/μs
TJ = 125 °C
TJ = 25 °C
-
-
1.5
-
630
950
-
730
1090
-
14
20
-
17
25
-
39
58
V
ns
μC
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS
S21-0019-Rev. C, 18-Jan-2021
Document Number: 91261
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SiHFPS40N60K
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
1000
3.5
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
I D = 38A
10
3.0
1
0.1
4.5V
0.01
20μs PULSE WIDTH
Tj = 25°C
0.001
0.1
1
10
2.5
(Normalized)
100
R DS(on) , Drain-to-Source On Resistance
ID, Drain-to-Source Current (A)
TOP
2.0
1.5
1.0
0.5
V GS = 10V
0.0
100
-60
-40
-20
Fig. 1 - Typical Output Characteristics
60
80
100
120
140
160
( ° C)
100000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
VGS
Ciss
Crss
Coss
= 0V,
f = 1 MHZ
= Cgs + C gd, Cds SHORTED
= Cgd
= C ds + C gd
10000
C, Capacitance(pF)
ID, Drain-to-Source Current (A)
40
Fig. 4 - Normalized On-Resistance vs. Temperature
TOP
10
20
TJ , Junction Temperature
VDS, Drain-to-Source Voltage (V)
100
0
4.5V
1
Ciss
1000
Coss
100
Crss
20μs PULSE WIDTH
Tj = 150°C
0.1
0.1
1
10
100
10
1
VDS, Drain-to-Source Voltage (V)
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
12
1000
I D = 38A
VDS = 480V
VDS = 300V
VDS = 120V
10
T J= 150 ° C
VGS , Gate-to-Source Voltage (V)
I D, Drain-to-Source Current (A)
100
10
TJ = 25 °C
1
0.1
7
5
2
V DS= 50V
20μs PULSE WIDTH
0
0.01
4
6
8
10
11
13
15
V GS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S21-0019-Rev. C, 18-Jan-2021
0
50
100
150
200
250
QG, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Document Number: 91261
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SiHFPS40N60K
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100
30
I D , Drain Current (A)
40
I SD , Reverse Drain Current (A)
1000
T J= 150 ° C
10
TJ = 25 °C
1
20
10
V GS = 0 V
0.1
0
0.2
0.6
0.9
1.3
1.6
25
50
V SD,Source-to-Drain Voltage (V)
75
Fig. 7 - Typical Source-Drain Diode Forward Voltage
125
RD
OPERATION IN THIS AREA
LIMITED BY R DS(on)
VDS
VGS
100
D.U.T.
RG
100μsec
10
10 V
1
1
+
- VDD
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
1msec
0.1
150
( ° C)
Fig. 9 - Maximum Drain Current vs. Case Temperature
1000
ID, Drain-to-Source Current (A)
100
TC , Case Temperature
10msec
Fig. 10a - Switching Time Test Circuit
Tc = 25°C
Tj = 150°C
Single Pulse
VDS
10
1000
90 %
100
10000
VDS , Drain-toSource Voltage (V)
Fig. 8 - Maximum Safe Operating Area
10 %
VGS
td(on)
tr
td(off) tf
Fig. 10b - Switching Time Waveforms
S21-0019-Rev. C, 18-Jan-2021
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(Z thJC )
1
D = 0.50
0.1
Thermal Response
0.20
0.10
0.05
P DM
0.02
0.01
0.01
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D =
2. Peak T
0.001
0.00001
0.0001
0.001
t1/ t 2
J = P DM x Z thJC
0.01
+TC
0.1
1
t 1, Rectangular Pulse Duration (sec)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
1200
960
Driver
L
VDS
D.U.T.
RG
+
A
- VDD
IAS
20 V
tp
EAS , Single Pulse Avalanche Energy (mJ)
15 V
0.01 Ω
TOP
ID
17A
24A
BOTTOM
38A
720
480
240
0
25
Fig. 12a - Unclamped Inductive Test Circuit
50
75
100
125
150
( ° C)
Starting Tj, Junction Temperature
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
VDS
IAS
5.0
VGS(th) Gate threshold Voltage (V)
tp
4.5
4.0
ID = 250μA
3.5
3.0
2.5
Fig. 12b - Unclamped Inductive Waveforms
2.0
-75
-50
-25
0
25
50
75
100
125 150
T J , Temperature ( °C )
Fig. 12d - Threshold Voltage vs. Temperature
S21-0019-Rev. C, 18-Jan-2021
Document Number: 91261
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SiHFPS40N60K
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Vishay Siliconix
Current regulator
Same type as D.U.T.
QG
VGS V
50 kΩ
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
-
VDS
VG
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
S21-0019-Rev. C, 18-Jan-2021
Fig. 13b - Gate Charge Test Circuit
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Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91261.
S21-0019-Rev. C, 18-Jan-2021
Document Number: 91261
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Package Information
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Vishay Siliconix
TO-274AA (High Voltage)
VERSION 1: FACILITY CODE = Y
B
A
E
E4
A
D2
E1
A1
R
D1
D
L1
L
Detail “A”
C
b
e
A2
0.10 (0.25) M B A M
10°
b4
b2
Lead Tip
5°
Detail “A”
Scale: 2:1
MILLIMETERS
INCHES
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
DIM.
MIN.
MAX.
MIN.
A
4.70
5.30
0.185
0.209
D1
15.50
16.10
0.610
0.634
A1
1.50
2.50
0.059
0.098
D2
0.70
1.30
0.028
0.051
A2
2.25
2.65
0.089
0.104
E
15.10
16.10
0.594
0.634
13.30
13.90
0.524
0.547
b
1.30
1.60
0.051
0.063
E1
b2
1.80
2.20
0.071
0.087
e
5.45 BSC
MAX.
0.215 BSC
b4
3.00
3.25
0.118
0.128
L
13.70
14.70
0.539
0.579
c (1)
0.38
0.89
0.015
0.035
L1
1.00
1.60
0.039
0.063
D
19.80
20.80
0.780
0.819
R
2.00
3.00
0.079
0.118
Notes
• Dimensioning and tolerancing per ASME Y14.5M-1994
• Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outer extremes of the plastic body
• Outline conforms to JEDEC® outline to TO-274AA
(1) Dimension measured at tip of lead
Revision: 19-Oct-2020
Document Number: 91365
1
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
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Vishay Siliconix
VERSION 2: FACILITY CODE = N
A
E
A
E3
B
D
D1
D2
E2
Q
A2
L1
F
F
H
H
C
G
L
G
A1
e
b
3x
0.25 M B A M
b1
C
b3
E4
E1
b’, b2, b4
C
C’
Base metal
b, b1, b3
Plating
SECTION "F-F", "G-G" AND "H-H"
SCALE: NONE
MILLIMETERS
MILLIMETERS
DIM.
MIN.
MAX.
DIM.
MIN.
MAX.
A
4.83
5.21
D1
16.25
17.65
A1
2.29
2.54
D2
0.50
0.80
A2
1.91
2.16
E
15.75
16.13
b’
1.07
1.28
E1
13.10
14.15
b
1.07
1.33
E2
3.68
5.10
b1
1.91
2.41
E3
1.00
1.90
b2
1.91
2.16
E4
12.38
13.43
b3
2.87
3.38
e
b4
2.87
3.13
N
c’
0.55
0.65
L
19.81
c
0.55
0.68
L1
3.70
4.00
D
20.80
21.10
Q
5.49
6.00
5.44 BSC
3
20.32
ECN: E20-0538-Rev. C, 19-Oct-2020
DWG: 5975
Notes
• Dimensioning and tolerancing per ASME Y14.5M-1994
• Outline conforms to JEDEC® outline to TO-274AD
• Dimensions are measured in mm, angles are in degree
• Metal surfaces are tin plated, except area of cut
Revision: 19-Oct-2020
Document Number: 91365
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Disclaimer
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