SiHG16N50C
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V) at TJ max.
• Low Figure-of-Merit Ron x Qg
560 V
RDS(on) (Ω)
VGS = 10 V
0.38
Qg (Max.) (nC)
• 100 % Avalanche Tested
68
Qgs (nC)
• Gate Charge Improved
17.6
Qgd (nC)
• Trr/Qrr Improved
21.8
Configuration
Single
• Compliant to RoHS Directive 2002/95/EC
D
TO-247AC
G
S
D
G
S
N-Channel MOSFET
ORDERING INFORMATION
Package
TO-247AC
Lead (Pb)-free
SiHG16N50C-E3
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
500
Gate-Source Voltage
VGS
± 30
Continuous Drain Current (TJ = 150 °C)a
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Currentc
ID
Maximum Power Dissipation
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)d
for 10 s
V
16
10
A
IDM
40
2
W/°C
EAS
320
mJ
PD
250
W
TJ, Tstg
- 55 to + 150
Linear Derating Factor
Single Pulse Avalanche Energyb
UNIT
300
°C
Notes
a. Limited by maximum junction temperature.
b. VDD = 50 V, starting TJ = 25 °C, L = 2.5 mH, Rg = 25 Ω, IAS = 16 A.
c. Repetitive rating; pulse width limited by maximum junction temperature.
d. 1.6 mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91418
S10-1355-Rev. A, 14-Jun-10
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SiHG16N50C
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
40
Maximum Junction-to-Case (Drain)
RthJC
-
0.5
UNIT
°C/W
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage (N)
VDS
VGS = 0 V, ID = 250 μA
500
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.6
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
3.0
-
5.0
V
Gate-Source Leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 500 V, VGS = 0 V
-
-
50
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
250
VGS = 10 V
μA
-
0.317
0.38
Ω
gfs
VDS = 50 V, ID = 3 A
-
3
-
S
Input Capacitance
Ciss
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz
-
1900
-
-
230
-
-
24
-
-
45
68
-
18
-
Drain-Source On-State Resistance
Forward Transconductancea
RDS(on)
ID = 8 A
Dynamic
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
VGS = 10 V
ID = 16 A, VDS = 400 V
Gate-Drain Charge
Qgd
-
22
-
Turn-On Delay Time
td(on)
-
27
-
Rise Time
Turn-Off Delay Time
tr
td(off)
Fall Time
tf
Gate Input Resistance
Rg
pF
nC
VDD = 250 V, ID = 16 A,
Rg = 9.1 Ω, VGS = 10 V
-
156
-
-
29
-
-
31
-
f = 1 MHz, open drain
-
1.6
-
-
-
16
-
-
30
-
-
1.8
V
-
555
-
ns
-
5.5
-
μC
-
18
-
A
ns
Ω
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Current
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Body Diode Reverse Recovery Current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 10 A, VGS = 0 V
TJ = 25 °C, IF = IS, dI/dt = 100 A/μs,
VR = 20 V
Note
• The information shown here is a preliminary product proposal, not a commercial product data sheet. Vishay Siliconix is not committed to
produce this or any similar product. This information should not be used for design purposes, nor construed as an offer to furnish or sell
such products.
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Document Number: 91418
S10-1355-Rev. A, 14-Jun-10
SiHG16N50C
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
45
50
15 V
14 V
13 V
12 V
11 V
10 V
9.0 V
8.0 V
7.0 V
6.0 V
BOTTOM 5.0 V
40
35
30
25
TJ = 25 °C
20
15
10
5
7.0 V
0
0
5
10
15
20
15
TJ = 150 °C
10
TJ = 25 °C
5
0
25
0
30
TJ = 150 °C
10
7.0 V
5
0
0
25
2
4
6
8
10
12
14
16
18
20
Fig. 3 - Typical Transfer Characteristics
15 V
14 V
13 V
12 V
11 V
10 V
9.0 V
8.0 V
7.0 V
6.0 V
BOTTOM 5.0 V
15
30
Fig. 1 - Typical Output Characteristics
TOP
20
35
VGS, Gate-to-Source Voltage (V)
VGS
25
20
40
VDS, Drain-to-Source Voltage (V)
30
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
RDS(on), Drain-to-Source On-Resistance
(Normalized)
ID, Drain-to-Source Current (A)
VGS
45
5
10
15
20
25
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
Document Number: 91418
S10-1355-Rev. A, 14-Jun-10
30
3
ID = 16 A
2.5
2
1.5
1
0.5
VGS = 10 V
0
- 60 - 40 - 20
0
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
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SiHG16N50C
Vishay Siliconix
VGS = 0 V, f = 1MHz
Ciss = Cgs +Cgd Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
C, Capacitance (pF)
2400
2000
Ciss
1600
1200
Coss
800
400
Crss
100
ISD, Reverse Drain Current (A)
2800
TJ = 150 °C
10
TJ = 25 °C
1
VGS = 0 V
0.1
0
1
10
100
0.2
1000
VDS, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
ID = 16 A
0.8
1
1.2
1.4
1.6
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100
VDS = 400 V
VDS = 250 V
VDS = 100 V
20
0.6
Fig. 7 - Typical Source-Drain Diode Forward Voltage
ID, Drain-to-Source Current (A)
VGS, Gate-to-Source Voltage (V)
24
0.4
VSD, Source-to-Drain Voltage (V)
16
12
8
4
100 µs
10
1
1 ms
TC = 25 °C
TJ = 150 °C
Single Pulse
10 ms
0.1
0
0
20
40
60
80
10
VDS
VGS
RG
RD
Fig. 8 - Maximum Safe Operating Area
VDS
90 %
D.U.T.
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 9a - Switching Time Test Circuit
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4
1000
VDS, Drain-to-Source Voltage (V)
QG, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
100
10 %
VGS
t d(on)
tr
t d(off) t f
Fig. 9b - Switching Time Waveforms
Document Number: 91418
S10-1355-Rev. A, 14-Jun-10
SiHG16N50C
Vishay Siliconix
1
Thermal Response (ZthJC)
0.5
0.2
0.1
0.1
PDM
0.05
t1
0.02
t2
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
Single Pulse
(Thermal Response)
0.01
10-4
10-3
10-2
0.1
1
t1, Rectangular Pulse Duration (s)
Fig. 10 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
15 V
QG
VGS
L
VDS
Driver
QGS
D.U.T.
RG
+
A
- VDD
IAS
20 V
VG
A
0.01 Ω
tp
QGD
Charge
Fig. 11a - Unclamped Inductive Test Circuit
Fig. 12a - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
V DS
50 kΩ
tp
12 V
0.2 µF
0.3 µF
D.U.T.
+
V
- DS
VGS
3 mA
I AS
IG
ID
Current sampling resistors
Fig. 11b - Unclamped Inductive Waveforms
Document Number: 91418
S10-1355-Rev. A, 14-Jun-10
Fig. 12b - Gate Charge Test Circuit
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SiHG16N50C
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
Period
P.W.
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 13 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91418.
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Document Number: 91418
S10-1355-Rev. A, 14-Jun-10
Package Information
www.vishay.com
Vishay Siliconix
TO-247AC (High Voltage)
VERSION 1: FACILITY CODE = 9
MILLIMETERS
DIM.
MIN.
MAX.
A
4.83
A1
2.29
MILLIMETERS
NOTES
DIM.
MIN.
MAX.
NOTES
5.21
D1
16.25
16.85
5
2.55
D2
0.56
0.76
A2
1.50
2.49
E
15.50
15.87
b
1.12
1.33
E1
13.46
14.16
5
b1
1.12
1.28
E2
4.52
5.49
3
b2
1.91
2.39
b3
1.91
2.34
b4
2.87
3.22
b5
2.87
3.18
c
0.55
0.69
c1
0.55
0.65
D
20.40
20.70
4
6
e
L
14.90
15.40
6, 8
L1
3.96
4.16
6
ØP
3.56
3.65
7
6
4
5.44 BSC
Ø P1
7.19 ref.
Q
5.31
5.69
S
5.54
5.74
Notes
(1) Package reference: JEDEC® TO247, variation AC
(2) All dimensions are in mm
(3) Slot required, notch may be rounded
(4) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the
outermost extremes of the plastic body
(5) Thermal pad contour optional with dimensions D1 and E1
(6) Lead finish uncontrolled in L1
(7) Ø P to have a maximum draft angle of 1.5° to the top of the part with a maximum hole diameter of 3.91 mm
(8) Dimension b2 and b4 does not include dambar protrusion. Allowable dambar protrusion shall be 0.1 mm total in excess of b2 and b4
dimension at maximum material condition
Revision: 19-Oct-2020
Document Number: 91360
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
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Vishay Siliconix
VERSION 2: FACILITY CODE = Y
A
A
4
E
B
3 R/2
E/2
7 ØP
Ø k M DBM
A2
S
(Datum B)
ØP1
A
D2
Q
4
4
2xR
(2)
D1
D
1
2
4
D
3
Thermal pad
5 L1
C
L
See view B
2 x b2
3xb
0.10 M C A M
4
E1
A
0.01 M D B M
View A - A
C
2x e
A1
b4
(b1, b3, b5)
Planting
Lead Assignments
1. Gate
2. Drain
3. Source
4. Drain
D DE
Base metal
E
C
(c)
C
c1
(b, b2, b4)
(4)
Section C - C, D - D, E - E
View B
MILLIMETERS
DIM.
MIN.
MAX.
A
4.58
5.31
MILLIMETERS
NOTES
DIM.
MIN.
MAX.
D2
0.51
1.30
15.87
A1
2.21
2.59
E
15.29
A2
1.17
2.49
E1
13.72
b
0.99
1.40
e
5.46 BSC
b1
0.99
1.35
Øk
b2
1.53
2.39
L
14.20
16.25
b3
1.65
2.37
L1
3.71
4.29
b4
2.42
3.43
ØP
3.51
3.66
b5
2.59
3.38
Ø P1
-
7.39
c
0.38
0.86
Q
5.31
5.69
4.52
c1
0.38
0.76
R
D
19.71
20.82
S
D1
13.08
-
NOTES
0.254
5.49
5.51 BSC
Notes
(1) Dimensioning and tolerancing per ASME Y14.5M-1994
(2) Contour of slot optional
(3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body
(4) Thermal pad contour optional with dimensions D1 and E1
(5) Lead finish uncontrolled in L1
(6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154")
(7) Outline conforms to JEDEC outline TO-247 with exception of dimension c
Revision: 19-Oct-2020
Document Number: 91360
2
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
VERSION 3: FACILITY CODE = N
A
E
R/2
D2
B
A
P
A2
D1
L1
D
D
K M D BM
R
S
Q
N
P1
b2
L
C
e
b
b4
C
E1
A1
0.01 M D B M
0.10 M C A M
b1, b3, b5
c
c1
Base metal
Plating
b, b2, b4
MILLIMETERS
MILLIMETERS
DIM.
MIN.
MAX.
DIM.
MIN.
A
4.65
5.31
D2
0.51
MAX.
1.35
A1
2.21
2.59
E
15.29
15.87
13.46
A2
1.17
1.37
E1
b
0.99
1.40
e
-
b1
0.99
1.35
k
b2
1.65
2.39
L
14.20
b3
1.65
2.34
L1
3.71
b4
2.59
3.43
N
b5
2.59
3.38
P
3.56
c
0.38
0.89
P1
-
7.39
c1
0.38
0.84
Q
5.31
5.69
D
19.71
20.70
R
4.52
D1
13.08
-
S
5.46 BSC
0.254
16.10
4.29
7.62 BSC
3.66
5.49
5.51 BSC
ECN: E20-0545-Rev. F, 19-Oct-2020
DWG: 5971
Notes
(1) Dimensioning and tolerancing per ASME Y14.5M-1994
(2) Contour of slot optional
(3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body
(4) Thermal pad contour optional with dimensions D1 and E1
(5) Lead finish uncontrolled in L1
(6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154")
Revision: 19-Oct-2020
Document Number: 91360
3
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Legal Disclaimer Notice
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Vishay
Disclaimer
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