SiHG20N50C
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Vishay Siliconix
Power MOSFET
FEATURES
D
• Low figure-of-merit Ron x Qg
TO-247AC
• 100 % avalanche tested
• High peak current capability
G
• dv/dt ruggedness
Available
• Improved Trr/Qrr
S
D
• Improved gate charge
S
G
• High power dissipations capability
N-Channel MOSFET
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
PRODUCT SUMMARY
VDS (V) at TJ max.
560
RDS(on) ()
VGS = 10 V
Qg max. (nC)
0.270
76
Qgs (nC)
21
Qgd (nC)
34
Configuration
Single
ORDERING INFORMATION
Package
TO-247AC
Lead (Pb)-free
SiHG20N50C-E3
Lead (Pb)-free and halogen-free
SiHG20N50C-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-source voltage
VDS
500
Gate-source voltage
VGS
± 30
Continuous drain current (TJ = 150 °C) a
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed drain current b
11
Single pulse avalanche
Reverse diode dv/dt d
Operating junction and storage temperature range
Soldering recommendations (peak temperature) d
A
80
Linear derating factor
Maximum power dissipation
V
20
ID
IDM
energy c
UNIT
1.8
W/°C
EAS
361
mJ
PD
250
W
dv/dt
5
V/ns
TJ, Tstg
-55 to +150
For 10 s
300
°C
Notes
a. Limited by maximum junction temperature
b. Repetitive rating; pulse width limited by maximum junction temperature
c. VDD = 50 V, starting TJ = 25 °C, L = 2.5 mH, Rg = 25 , IAS = 17 A
d. ISD 18 A, di/dt 380 A/μs, VDD VDS, TJ 150 °C
e. 1.6 mm from case
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum junction-to-ambient
RthJA
-
40
Maximum junction-to-case (drain)
RthJC
-
0.5
S17-1726-Rev. D, 20-Nov-17
UNIT
°C/W
Document Number: 91382
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHG20N50C
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Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
VDS temperature coefficient
Gate-source threshold voltage (N)
VDS
VGS = 0 V, ID = 250 μA
500
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.7
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
3.0
-
5.0
V
Gate-source leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero gate voltage drain current
IDSS
VDS = 500 V, VGS = 0 V
-
-
25
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
250
μA
-
0.225
0.270
gfs
VDS = 50 V, ID = 10 A
-
6.4
-
S
Input capacitance
Ciss
2451
2942
Coss
-
300
360
Reverse transfer capacitance
Crss
VGS = 0 V,
VDS = 25 V,
f = 1 MHz
-
Output capacitance
-
26
32
Drain-source on-state resistance
Forward transconductance
RDS(on)
VGS = 10 V
ID = 10 A
Dynamic
Total gate charge
Qg
Gate-source charge
Qgs
Gate-drain charge
Turn-on delay time
Rise time
Turn-off delay time
pF
-
65
76
-
21
-
Qgd
-
29
-
td(on)
-
80
-
VDD = 250 V, ID = 18 A, Rg = 9.1
-
27
-
-
32
-
-
44
-
f = 1 MHz, open drain
-
1.1
-
-
-
20
S
-
-
80
TJ = 25 °C, IS = 18 A, VGS = 0 V
-
-
1.5
V
-
503
-
ns
-
6.7
-
μC
-
30
-
A
tr
td(off)
Fall time
tf
Gate input resistance
Rg
VGS = 10 V
ID = 18 A, VDS = 400 V
nC
ns
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
IS
Pulsed diode forward current
ISM
Diode forward voltage
VSD
Reverse recovery time
trr
Reverse recovery charge
Qrr
Reverse recovery current
IRRM
S17-1726-Rev. D, 20-Nov-17
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IF = IS,
di/dt = 100 A/μs, VR = 35 V
Document Number: 91382
2
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHG20N50C
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Vishay Siliconix
70
VGS
Top
15 V
14 V
13 V
12 V
11 V
10 V
9.0 V
8.0 V
7.0 V
6.0 V
Bottom 5.0 V
ID, Drain Current (A)
60
50
40
30
TJ = 25 °C
20
7.0 V
10
0
0
6
12
18
24
RDS(on), Drain-to-Source On Resistance
(Normalized)
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
30
3
ID = 17 A
2.5
2
1.5
VGS = 10 V
1
0.5
0
- 60 - 40 - 20
Fig. 1 - Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 4 - Normalized On-Resistance vs. Temperature
40
105
VGS
15 V
14 V
13 V
12 V
30
11 V
10 V
9.0 V
8.0 V
7.0 V
20
6.0 V
Bottom 5.0 V
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
Capacitance (pF)
TJ = 150 °C
Top
ID, Drain Current (A)
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
VDS, Drain-to-Source Voltage (V)
7.0 V
10
0
104
Ciss
103
102
Coss
Crss
10
0
6
12
18
24
30
1
VDS, Drain-to-Source Voltage (V)
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
100
VGS, Gate-to-Source Voltage (V)
20
TJ = 150 °C
ID, Drain Current (A)
0
10
TJ = 25 °C
1
0.1
ID = 17 A
VDS = 400 V
VDS = 250 V
VDS = 100 V
16
12
8
4
0
0.01
5
6
7
8
9
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S17-1726-Rev. D, 20-Nov-17
10
0
30
60
90
120
QG, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Document Number: 91382
3
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHG20N50C
www.vishay.com
Vishay Siliconix
1000
Operation in this area limited
by RDS(on)
TJ = 150 °C
10
ID, Drain Current (A)
ISD, Reverse Drain Current (A)
100
TJ = 25 °C
1
VGS = 0 V
0.1
0.2
0.5
0.8
1.1
100
10
100 µs
1 ms
1
TC = 25 °C
TJ = 150 °C
Single Pulse
10 ms
0.1
100
10
1.4
1000
10 000
VDS, Drain-to-Source Voltage (V)
VSD, Source-to-Drain Voltage (V)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
20
ID, Drain Current (A)
15
10
5
0
25
50
75
100
125
150
TC, Case Temperature (°C)
Fig. 9 - Maximum Drain Current vs. Case Temperature
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
10-4
Single Pulse
10-3
10-2
0.1
1
Pulse Time (s)
Fig. 10 - Normalized Thermal Transient Impedance, Junction-to-Case (TO-247)
S17-1726-Rev. D, 20-Nov-17
Document Number: 91382
4
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHG20N50C
www.vishay.com
Vishay Siliconix
RD
VDS
QG
10 V
VGS
D.U.T.
Rg
QGS
+
- VDD
10 V
QGD
VG
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Charge
Fig. 11 - Switching Time Test Circuit
Fig. 15 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
VDS
90 %
50 kΩ
12 V
0.2 µF
0.3 µF
10 %
VGS
+
td(on)
D.U.T.
td(off) tf
tr
-
VDS
VGS
Fig. 12 - Switching Time Waveforms
3 mA
IG
ID
Current sampling resistors
L
Vary tp to obtain
required IAS
VDS
Fig. 16 - Gate Charge Test Circuit
D.U.T
Rg
+
-
IAS
V DD
10 V
0.01 Ω
tp
Fig. 13 - Unclamped Inductive Test Circuit
VDS
tp
VDD
VDS
IAS
Fig. 14 - Unclamped Inductive Waveforms
S17-1726-Rev. D, 20-Nov-17
Document Number: 91382
5
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHG20N50C
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 17 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91382.
S17-1726-Rev. D, 20-Nov-17
Document Number: 91382
6
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
TO-247AC (High Voltage)
A
A
4
E
B
3 R/2
E/2
7 ØP
Ø k M DBM
A2
S
(Datum B)
ØP1
A
D2
Q
4
4
2xR
(2)
D1
D
1
2
4
D
3
Thermal pad
5 L1
C
L
A
See view B
2 x b2
3xb
0.10 M C A M
4
E1
0.01 M D B M
View A - A
C
2x e
A1
b4
Planting
Lead Assignments
1. Gate
2. Drain
3. Source
4. Drain
D DE
(b1, b3, b5)
Base metal
E
C
(c)
C
c1
(b, b2, b4)
(4)
Section C - C, D - D, E - E
View B
MILLIMETERS
DIM.
MIN.
MAX.
A
4.58
5.31
A1
2.21
2.59
A2
1.17
2.49
b
0.99
1.40
b1
0.99
1.35
b2
1.53
2.39
b3
1.65
2.37
b4
2.42
3.43
b5
2.59
3.38
c
0.38
0.86
c1
0.38
0.76
D
19.71
20.82
D1
13.08
ECN: X13-0103-Rev. D, 01-Jul-13
DWG: 5971
INCHES
MIN.
MAX.
0.180
0.209
0.087
0.102
0.046
0.098
0.039
0.055
0.039
0.053
0.060
0.094
0.065
0.093
0.095
0.135
0.102
0.133
0.015
0.034
0.015
0.030
0.776
0.820
0.515
-
DIM.
D2
E
E1
e
Øk
L
L1
N
ØP
Ø P1
Q
R
S
MILLIMETERS
MIN.
MAX.
0.51
1.30
15.29
15.87
13.72
5.46 BSC
0.254
14.20
16.25
3.71
4.29
7.62 BSC
3.51
3.66
7.39
5.31
5.69
4.52
5.49
5.51 BSC
INCHES
MIN.
MAX.
0.020
0.051
0.602
0.625
0.540
0.215 BSC
0.010
0.559
0.640
0.146
0.169
0.300 BSC
0.138
0.144
0.291
0.209
0.224
0.178
0.216
0.217 BSC
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Contour of slot optional.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions D1 and E1.
5. Lead finish uncontrolled in L1.
6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154").
7. Outline conforms to JEDEC outline TO-247 with exception of dimension c.
8. Xian and Mingxin actually photo.
Revision: 01-Jul-13
Document Number: 91360
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
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including but not limited to the warranty expressed therein.
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Revision: 08-Feb-17
1
Document Number: 91000
