SiHG24N65EF
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Vishay Siliconix
E Series Power MOSFET with Fast Body Diode
FEATURES
PRODUCT SUMMARY
VDS (V) at TJ max.
• Fast body diode MOSFET using E series
technology
• Reduced trr, Qrr, and IRRM
• Low figure-of-merit (FOM) Ron x Qg
• Low input capacitance (Ciss)
• Low switching losses due to reduced Qrr
• Ultra low gate charge (Qg)
• Avalanche energy rated (UIS)
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
700
RDS(on) max. () at 25 °C
VGS = 10 V
Qg max. (nC)
0.156
122
Qgs (nC)
17
Qgd (nC)
36
Configuration
Single
D
APPLICATIONS
TO-247AC
• Telecommunications
- Server and telecom power supplies
• Lighting
- High-intensity discharge (HID)
- Fluorescent ballast lighting
• Consumer and computing
- ATX power supplies
• Industrial
- Welding
- Battery chargers
• Renewable energy
- Solar (PV inverters)
• Switch mode power supplies (SMPS)
• Applications using the following topologies
- LCC
- Phase shifted bridge (ZVS)
- 3-level inverter
- AC/DC bridge
G
S
S
D
G
N-Channel MOSFET
ORDERING INFORMATION
Package
TO-247AC
Lead (Pb)-free and halogen-free
SiHG24N65EF-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-source voltage
VDS
650
Gate-source voltage
VGS
± 30
Continuous drain current (TJ = 150 °C)
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed drain current a
ID
UNIT
V
24
15
A
IDM
65
2
W/°C
Single pulse avalanche energy b
EAS
691
mJ
Maximum power dissipation
PD
250
W
TJ, Tstg
-55 to +150
°C
Linear derating factor
Operating junction and storage temperature range
Drain-source voltage slope
TJ = 125 °C
Reverse diode dV/dt d
Soldering recommendations (peak temperature) c
for 10 s
dV/dt
70
50
300
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature
b. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 , IAS = 7 A
c. 1.6 mm from case
d. ISD ID, dI/dt = 900 A/μs, starting TJ = 25 °C
S18-0015-Rev. C, 15-Jan-18
Document Number: 91610
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THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum junction-to-ambient
RthJA
-
40
Maximum junction-to-case (drain)
RthJC
-
0.5
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
VDS temperature coefficient
Gate-source threshold voltage (N)
VDS
VGS = 0 V, ID = 250 μA
650
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.68
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2
-
4
V
VGS = ± 20 V
-
-
± 100
nA
VGS = ± 30 V
-
-
±1
μA
VDS = 520 V, VGS = 0 V
-
-
1
VDS = 520 V, VGS = 0 V, TJ = 125 °C
-
-
500
Gate-source leakage
IGSS
Zero gate voltage drain current
IDSS
μA
-
0.13
0.156
gfs
VDS = 30 V, ID = 12 A
-
7.2
-
S
Input capacitance
Ciss
2774
-
Coss
-
128
-
Reverse transfer capacitance
Crss
VGS = 0 V,
VDS = 100 V,
f = 1 MHz
-
Output capacitance
-
4
-
Effective output capacitance, energy
related a
Co(er)
-
96
-
Effective output capacitance, time
related b
Co(tr)
-
333
-
-
81
122
-
17
-
Drain-source on-state resistance
Forward transconductance
RDS(on)
VGS = 10 V
ID = 12 A
Dynamic
pF
VDS = 0 V to 520 V, VGS = 0 V
Total gate charge
Qg
Gate-source charge
Qgs
VGS = 10 V
ID = 12 A, VDS = 520 V
Gate-drain charge
Qgd
-
36
-
Turn-on delay time
td(on)
-
24
48
Rise time
Turn-off delay time
tr
td(off)
Fall time
tf
Gate input resistance
Rg
VDD = 520 V, ID = 12 A,
VGS = 10 V, Rg = 9.1
-
34
68
-
80
120
-
46
92
f = 1 MHz, open drain
0.2
0.5
1.0
-
-
24
-
-
65
nC
ns
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
IS
Pulsed diode forward current
ISM
Diode forward voltage
VSD
Reverse recovery time
trr
Reverse recovery charge
Qrr
Reverse recovery current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 12 A, VGS = 0 V
TJ = 25 °C, IF = IS = 12 A,
dI/dt = 100 A/μs, VR = 400 V
S
-
0.9
1.2
V
-
151
288
ns
-
0.9
2.1
μC
-
13
-
A
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS
S18-0015-Rev. C, 15-Jan-18
Document Number: 91610
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
60
3
TJ = 25 °C
ID = 12 A
RDS(on), Drain-to-Source
On Resistance (Normalized)
ID, Drain-to-Source Current (A)
80
40
20
6V
2.5
2
1.5
VGS = 10 V
1
0.5
5V
0
0
5
10
15
20
25
0
- 60 - 40 - 20 0
30
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 1 - Typical Output Characteristics
10 000
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
30
20
Ciss
TJ = 150 °C
ġ
Capacitance (pF)
40
7V
6V
1000
Coss
100
ġ
ġ
Crss
10
10
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
ġ
5V
1
0
0
5
10
15
20
25
0
30
VDS, Drain-to-Source Voltage (V)
100
200
300
400
500
600
VDS, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 2 - Typical Output Characteristics
16
5000
14
60
12
10
40
Coss (pF)
ID, Drain-to-Source Current (A)
80
TJ = 150 °C
Coss
Eoss
8
500
Eoss (μJ)
ID, Drain-to-Source Current (A)
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
VDS, Drain-to-Source Voltage (V)
6
20
4
TJ = 25 °C
VDS = 28.8 V
2
0
0
5
10
15
20
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S18-0015-Rev. C, 15-Jan-18
25
50
0
0
100
200
300
400
500
600
VDS
Fig. 6 - Coss and Eoss vs. VDS
Document Number: 91610
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25
VDS = 520 V
VDS = 325 V
VDS = 130 V
20
ID, Drain Current (A)
VGS, Gate-to-Source Voltage (V)
24
16
12
8
4
0
20
15
10
5
0
0
60
30
90
120
150
25
Qg, Total Gate Charge (nC)
50
75
100
125
150
TJ, Case Temperature (°C)
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 10 - Maximum Drain Current vs. Case Temperature
850
100
ISD, Reverse Drain Current (A)
ID = 10 mA
VDS, Drain-to-Source
Breakdown Voltage (V)
825
TJ = 150 °C
TJ = 25 °C
10
ġ
1
0.1
0.4
0.6
0.8
1
1.2
1.4
1.6
VSD, Source-Drain Voltage (V)
ID, Drain Current (A)
700
650
- 60 - 40 - 20 0
20 40 60 80 100 120 140 160
Fig. 11 - Temperature vs. Drain-to-Source Voltage
100 μs
Limited by RDS(on)*
1 ms
Operation in this Area
Limited by RDS(on)
10 ms
0.1
TC = 25 °C
TJ = 150 °C
Single Pulse
0.01
1
725
IDM = Limited
10
1
750
TJ, Junction Temperature (°C)
Fig. 8 - Typical Source-Drain Diode Forward Voltage
100
775
675
VGS = 0 V
0.2
800
BVDSS Limited
10
100
1000
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Fig. 9 - Maximum Safe Operating Area
S18-0015-Rev. C, 15-Jan-18
Document Number: 91610
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Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
0.0001
0.001
0.01
0.1
1
Pulse Time (s)
Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case
RD
VDS
VDS
tp
VGS
VDD
D.U.T.
RG
+
- VDD
VDS
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
IAS
Fig. 16 - Unclamped Inductive Waveforms
Fig. 13 - Switching Time Test Circuit
VDS
QG
10 V
90 %
QGS
10 %
VGS
QGD
VG
td(on)
td(off) tf
tr
Charge
Fig. 17 - Basic Gate Charge Waveform
Fig. 14 - Switching Time Waveforms
L
Vary tp to obtain
required IAS
Current regulator
Same type as D.U.T.
VDS
50 kΩ
D.U.T
RG
+
-
IAS
12 V
0.2 µF
0.3 µF
V DD
+
D.U.T.
10 V
tp
0.01 Ω
-
VDS
VGS
3 mA
Fig. 15 - Unclamped Inductive Test Circuit
IG
ID
Current sampling resistors
Fig. 18 - Gate Charge Test Circuit
S18-0015-Rev. C, 15-Jan-18
Document Number: 91610
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SiHG24N65EF
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Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 19 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91610.
S18-0015-Rev. C, 15-Jan-18
Document Number: 91610
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
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Vishay Siliconix
TO-247AC (High Voltage)
VERSION 1: FACILITY CODE = 9
MILLIMETERS
DIM.
MIN.
MAX.
A
4.83
A1
2.29
MILLIMETERS
NOTES
DIM.
MIN.
MAX.
NOTES
5.21
D1
16.25
16.85
5
2.55
D2
0.56
0.76
A2
1.50
2.49
E
15.50
15.87
b
1.12
1.33
E1
13.46
14.16
5
b1
1.12
1.28
E2
4.52
5.49
3
b2
1.91
2.39
b3
1.91
2.34
b4
2.87
3.22
b5
2.87
3.18
c
0.55
0.69
c1
0.55
0.65
D
20.40
20.70
4
6
e
L
14.90
15.40
6, 8
L1
3.96
4.16
6
ØP
3.56
3.65
7
6
4
5.44 BSC
Ø P1
7.19 ref.
Q
5.31
5.69
S
5.54
5.74
Notes
(1) Package reference: JEDEC® TO247, variation AC
(2) All dimensions are in mm
(3) Slot required, notch may be rounded
(4) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the
outermost extremes of the plastic body
(5) Thermal pad contour optional with dimensions D1 and E1
(6) Lead finish uncontrolled in L1
(7) Ø P to have a maximum draft angle of 1.5° to the top of the part with a maximum hole diameter of 3.91 mm
(8) Dimension b2 and b4 does not include dambar protrusion. Allowable dambar protrusion shall be 0.1 mm total in excess of b2 and b4
dimension at maximum material condition
Revision: 19-Oct-2020
Document Number: 91360
1
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Package Information
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VERSION 2: FACILITY CODE = Y
A
A
4
E
B
3 R/2
E/2
7 ØP
Ø k M DBM
A2
S
(Datum B)
ØP1
A
D2
Q
4
4
2xR
(2)
D1
D
1
2
4
D
3
Thermal pad
5 L1
C
L
See view B
2 x b2
3xb
0.10 M C A M
4
E1
A
0.01 M D B M
View A - A
C
2x e
A1
b4
(b1, b3, b5)
Planting
Lead Assignments
1. Gate
2. Drain
3. Source
4. Drain
D DE
Base metal
E
C
(c)
C
c1
(b, b2, b4)
(4)
Section C - C, D - D, E - E
View B
MILLIMETERS
DIM.
MIN.
MAX.
A
4.58
5.31
MILLIMETERS
NOTES
DIM.
MIN.
MAX.
D2
0.51
1.30
15.87
A1
2.21
2.59
E
15.29
A2
1.17
2.49
E1
13.72
b
0.99
1.40
e
5.46 BSC
b1
0.99
1.35
Øk
b2
1.53
2.39
L
14.20
16.25
b3
1.65
2.37
L1
3.71
4.29
b4
2.42
3.43
ØP
3.51
3.66
b5
2.59
3.38
Ø P1
-
7.39
c
0.38
0.86
Q
5.31
5.69
4.52
c1
0.38
0.76
R
D
19.71
20.82
S
D1
13.08
-
NOTES
0.254
5.49
5.51 BSC
Notes
(1) Dimensioning and tolerancing per ASME Y14.5M-1994
(2) Contour of slot optional
(3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body
(4) Thermal pad contour optional with dimensions D1 and E1
(5) Lead finish uncontrolled in L1
(6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154")
(7) Outline conforms to JEDEC outline TO-247 with exception of dimension c
Revision: 19-Oct-2020
Document Number: 91360
2
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VERSION 3: FACILITY CODE = N
A
E
R/2
D2
B
A
P
A2
D1
L1
D
D
K M D BM
R
S
Q
N
P1
b2
L
C
e
b
b4
C
E1
A1
0.01 M D B M
0.10 M C A M
b1, b3, b5
c
c1
Base metal
Plating
b, b2, b4
MILLIMETERS
MILLIMETERS
DIM.
MIN.
MAX.
DIM.
MIN.
A
4.65
5.31
D2
0.51
MAX.
1.35
A1
2.21
2.59
E
15.29
15.87
13.46
A2
1.17
1.37
E1
b
0.99
1.40
e
-
b1
0.99
1.35
k
b2
1.65
2.39
L
14.20
b3
1.65
2.34
L1
3.71
b4
2.59
3.43
N
b5
2.59
3.38
P
3.56
c
0.38
0.89
P1
-
7.39
c1
0.38
0.84
Q
5.31
5.69
D
19.71
20.70
R
4.52
D1
13.08
-
S
5.46 BSC
0.254
16.10
4.29
7.62 BSC
3.66
5.49
5.51 BSC
ECN: E20-0545-Rev. F, 19-Oct-2020
DWG: 5971
Notes
(1) Dimensioning and tolerancing per ASME Y14.5M-1994
(2) Contour of slot optional
(3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body
(4) Thermal pad contour optional with dimensions D1 and E1
(5) Lead finish uncontrolled in L1
(6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154")
Revision: 19-Oct-2020
Document Number: 91360
3
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Legal Disclaimer Notice
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Disclaimer
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