SIHG30N60E-E3

SiHG30N60E www.vishay.com Vishay Siliconix E Series Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) at TJ max. • • • • • • 650 RDS(on) max. at 25 °C (Ω) VGS = 10 V Qg max. (nC) 0.125 130 Qgs (nC) 15 Qgd (nC) 39 Configuration Single APPLICATIONS D • • • • Server and telecom power supplies Switch mode power supplies (SMPS) Power factor correction power supplies (PFC) Lighting - High-intensity discharge (HID) - Fluorescent ballast lighting - LED lighting • Industrial - Welding - Induction heating - Motor drives • Battery chargers • Renewable energy - Solar (PV inverters) TO-247AC G S D G Low figure-of-merit (FOM) Ron x Qg Low input capacitance (Ciss) Reduced switching and conduction losses Ultra low gate charge (Qg) Available Avalanche energy rated (UIS) Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 S N-Channel MOSFET ORDERING INFORMATION Package TO-247AC Lead (Pb)-free SiHG30N60E-E3 Lead (Pb)-free and Halogen-free SiHG30N60E-GE3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 600 Gate-Source Voltage VGS ± 30 Continuous Drain Current (TJ = 150 °C) VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Current a ID UNIT V 29 18 A IDM 65 2 W/°C Single Pulse Avalanche Energy b EAS 690 mJ Maximum Power Dissipation PD 250 W TJ, Tstg -55 to +150 °C Linear Derating Factor Operating Junction and Storage Temperature Range Drain-Source Voltage Slope Reverse Diode dV/dt VDS = 0 V to 80 % VDS d Soldering Recommendations (Peak Temperature) c for 10 s dV/dt 70 18 300 V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 Ω, IAS = 7 A. c. 1.6 mm from case. d. ISD ≤ ID, dI/dt = 100 A/μs, starting TJ = 25 °C. S15-1063-Rev. H, 04-May-15 Document Number: 91455 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG30N60E www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 62 Maximum Junction-to-Case (Drain) RthJC - 0.5 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage (N) Gate-Source Leakage Zero Gate Voltage Drain Current VDS VGS = 0 V, ID = 250 μA 600 - - V ΔVDS/TJ Reference to 25 °C, ID = 250 μA - 0.64 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2.0 2.8 4.0 V VGS = ± 20 V - - ± 100 nA μA IGSS IDSS VGS = ± 30 V - - ±1 VDS = 600 V, VGS = 0 V - - 1 VDS = 600 V, VGS = 0 V, TJ = 150 °C - - 100 μA - 0.104 0.125 Ω gfs VDS = 8 V, ID = 3 A - 5.4 - S Input Capacitance Ciss 2600 - Coss - 138 - Reverse Transfer Capacitance Crss VGS = 0 V, VDS = 100 V, f = 1.0 MHz - Output Capacitance - 3 - Effective Output Capacitance, Energy Related a Co(er) - 98 - Effective Output Capacitance, Time Related b Co(tr) - 346 - - 85 130 - 15 - Drain-Source On-State Resistance Forward Transconductance a RDS(on) VGS = 10 V ID = 15 A Dynamic pF VDS = 0 V to 480 V, VGS = 0 V Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd - 39 - Turn-On Delay Time td(on) - 19 40 Rise Time Turn-Off Delay Time tr td(off) Fall Time tf Gate Input Resistance Rg VGS = 10 V ID = 15 A, VDS = 480 V nC VDD = 380 V, ID = 15 A, VGS = 10 V, Rg = 4.7 Ω - 32 65 - 63 95 - 36 75 f = 1 MHz, open drain - 0.63 - - - 29 - - 65 TJ = 25 °C, IS = 15 A, VGS = 0 V - - 1.3 - 402 605 ns TJ = 25 °C, IF = IS = 15 A, dI/dt = 100 A/μs, VR = 20 V - 7 15 μC - 32 65 A ns Ω Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Current ISM Diode Forward Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Reverse Recovery Current IRRM MOSFET symbol showing the integral reverse p - n junction diode D A G S V Notes a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS. b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS. S15-1063-Rev. H, 04-May-15 Document Number: 91455 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG30N60E www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 80 3.0 TOP 15 V 14 V 13 V 12 V 11 V 10 V 9.0 V 8.0 V 7.0 V 6.0 V BOTTOM 5.0 V ID - Drain Current (A) 60 TJ = 25 °C 50 40 30 20 VGS = 10 V 2.0 1.5 1.0 0.5 5V 10 ID = 15 A 2.5 RDS(on) - On-Resistance (Normalized) 70 0.0 0 0 5 10 15 20 25 - 60 - 40 - 20 30 0 20 40 60 80 100 120 140 160 TJ - Junction Temperature (°C) VDS - Drain-to-Source Voltage (V) Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 4 - Normalized On-Resistance vs. Temperature 50 10 000 Ciss TOP 15 V 14 V 13 V 12 V 11 V 10 V 9.0 V 8.0 V 7.0 V 6.0 V BOTTOM 5.0 V 30 20 VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd x Cds shorted Crss = Cgd Coss = Cds + Cgd 1000 C - Capacitance (pF) ID - Drain Current (A) 40 100 Coss 10 10 Crss TJ = 150 °C 1 0 0 5 10 15 20 25 0 30 100 200 300 400 500 600 VDS - Drain-to-Source Voltage (V) VDS - Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics, TC = 150 °C Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 80 18 16 TJ = 25 °C 14 2000 TJ = 150 °C 40 10 Coss Eoss 8 200 Eoss (μJ) 12 Coss (pF) ID, Drain Current (A) 60 6 20 4 2 0 20 0 5 10 15 20 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S15-1063-Rev. H, 04-May-15 25 0 0 100 200 300 400 500 600 VDS Fig. 6 - Coss and Eoss vs. VDS Document Number: 91455 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG30N60E www.vishay.com Vishay Siliconix 24 30.0 VDS = 300 V ID = 15 A 25.0 VDS = 120 V 16 VDS = 480 V 12 8 ID, Drain Current (A) VGS - Gate-to-Source Voltage (V) 20 20.0 15.0 10.0 4 5.0 0 0 0 25 50 75 100 125 25 150 50 75 125 150 TC - Temperature (°C) Qg - Total Gate Charge (nC) Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 10 - Maximum Drain Current vs. Case Temperature 1000 VDS, Drain-to-Source Breakdown Voltage (V) 725 100 IS - Source Current (A) 100 TJ = 150 °C 10 1 TJ = 25 °C 0.1 0.01 0.001 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VSD - Source-to-Drain Voltage (V) 700 675 650 625 600 575 550 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 TJ - Temperature (°C) Fig. 8 - Typical Source-Drain Diode Forward Voltage Fig. 11 - Temperature vs. Drain-to-Source Voltage 1000 ID, Drain Current (A) Operation in this area limited by RDS(on) 100 IDM Limited 0.1 μs 1 μs 10 μs 10 100 μs 1 ms 1 0.1 0.1 TC = 25 °C TJ = 150 °C Single Pulse 10 ms BVDSS Limited 100 1 10 1000 VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Fig. 9 - Maximum Safe Operating Area S15-1063-Rev. H, 04-May-15 Document Number: 91455 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG30N60E www.vishay.com Vishay Siliconix Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 0.0001 0.001 0.01 0.1 1 Square Wave Pulse Duration (s) Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case VGS VDS RD VDS tp VDD D.U.T. RG + - VDD VDS 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % IAS Fig. 16 - Unclamped Inductive Waveforms Fig. 13 - Switching Time Test Circuit VDS 90 % QG 10 V QGS 10 % VGS QGD VG td(on) td(off) tf tr Fig. 14 - Switching Time Waveforms Charge Fig. 17 - Basic Gate Charge Waveform L Vary tp to obtain required IAS VDS Current regulator Same type as D.U.T. D.U.T RG + - IAS V DD 50 kΩ 12 V 0.2 µF 0.3 µF 10 V tp + 0.01 Ω Fig. 15 - Unclamped Inductive Test Circuit D.U.T. - VDS VGS 3 mA IG ID Current sampling resistors Fig. 18 - Gate Charge Test Circuit S15-1063-Rev. H, 04-May-15 Document Number: 91455 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG30N60E www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 19 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91455. S15-1063-Rev. H, 04-May-15 Document Number: 91455 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix TO-247AC (High Voltage) VERSION 1: FACILITY CODE = 9 MILLIMETERS DIM. MIN. MAX. A 4.83 A1 2.29 MILLIMETERS NOTES DIM. MIN. MAX. NOTES 5.21 D1 16.25 16.85 5 2.55 D2 0.56 0.76 A2 1.50 2.49 E 15.50 15.87 b 1.12 1.33 E1 13.46 14.16 5 b1 1.12 1.28 E2 4.52 5.49 3 b2 1.91 2.39 b3 1.91 2.34 b4 2.87 3.22 b5 2.87 3.18 c 0.55 0.69 c1 0.55 0.65 D 20.40 20.70 4 6 e L 14.90 15.40 6, 8 L1 3.96 4.16 6 ØP 3.56 3.65 7 6 4 5.44 BSC Ø P1 7.19 ref. Q 5.31 5.69 S 5.54 5.74 Notes (1) Package reference: JEDEC® TO247, variation AC (2) All dimensions are in mm (3) Slot required, notch may be rounded (4) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outermost extremes of the plastic body (5) Thermal pad contour optional with dimensions D1 and E1 (6) Lead finish uncontrolled in L1 (7) Ø P to have a maximum draft angle of 1.5° to the top of the part with a maximum hole diameter of 3.91 mm (8) Dimension b2 and b4 does not include dambar protrusion. Allowable dambar protrusion shall be 0.1 mm total in excess of b2 and b4 dimension at maximum material condition Revision: 19-Oct-2020 Document Number: 91360 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix VERSION 2: FACILITY CODE = Y A A 4 E B 3 R/2 E/2 7 ØP Ø k M DBM A2 S (Datum B) ØP1 A D2 Q 4 4 2xR (2) D1 D 1 2 4 D 3 Thermal pad 5 L1 C L See view B 2 x b2 3xb 0.10 M C A M 4 E1 A 0.01 M D B M View A - A C 2x e A1 b4 (b1, b3, b5) Planting Lead Assignments 1. Gate 2. Drain 3. Source 4. Drain D DE Base metal E C (c) C c1 (b, b2, b4) (4) Section C - C, D - D, E - E View B MILLIMETERS DIM. MIN. MAX. A 4.58 5.31 MILLIMETERS NOTES DIM. MIN. MAX. D2 0.51 1.30 15.87 A1 2.21 2.59 E 15.29 A2 1.17 2.49 E1 13.72 b 0.99 1.40 e 5.46 BSC b1 0.99 1.35 Øk b2 1.53 2.39 L 14.20 16.25 b3 1.65 2.37 L1 3.71 4.29 b4 2.42 3.43 ØP 3.51 3.66 b5 2.59 3.38 Ø P1 - 7.39 c 0.38 0.86 Q 5.31 5.69 4.52 c1 0.38 0.76 R D 19.71 20.82 S D1 13.08 - NOTES 0.254 5.49 5.51 BSC Notes (1) Dimensioning and tolerancing per ASME Y14.5M-1994 (2) Contour of slot optional (3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body (4) Thermal pad contour optional with dimensions D1 and E1 (5) Lead finish uncontrolled in L1 (6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154") (7) Outline conforms to JEDEC outline TO-247 with exception of dimension c Revision: 19-Oct-2020 Document Number: 91360 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix VERSION 3: FACILITY CODE = N A E R/2 D2 B A P A2 D1 L1 D D K M D BM R S Q N P1 b2 L C e b b4 C E1 A1 0.01 M D B M 0.10 M C A M b1, b3, b5 c c1 Base metal Plating b, b2, b4 MILLIMETERS MILLIMETERS DIM. MIN. MAX. DIM. MIN. A 4.65 5.31 D2 0.51 MAX. 1.35 A1 2.21 2.59 E 15.29 15.87 13.46 A2 1.17 1.37 E1 b 0.99 1.40 e - b1 0.99 1.35 k b2 1.65 2.39 L 14.20 b3 1.65 2.34 L1 3.71 b4 2.59 3.43 N b5 2.59 3.38 P 3.56 c 0.38 0.89 P1 - 7.39 c1 0.38 0.84 Q 5.31 5.69 D 19.71 20.70 R 4.52 D1 13.08 - S 5.46 BSC 0.254 16.10 4.29 7.62 BSC 3.66 5.49 5.51 BSC ECN: E20-0545-Rev. F, 19-Oct-2020 DWG: 5971 Notes (1) Dimensioning and tolerancing per ASME Y14.5M-1994 (2) Contour of slot optional (3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body (4) Thermal pad contour optional with dimensions D1 and E1 (5) Lead finish uncontrolled in L1 (6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154") Revision: 19-Oct-2020 Document Number: 91360 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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