SIHG33N60EF-GE3

SIHG33N60EF-GE3

  • 厂商:

    TFUNK(威世)

  • 封装:

    TO-247

  • 描述:

    特性:采用E系列技术的快速体二极管MOSFET。 降低trr、Qrr和IRRM。 低品质因数 (FOM):Ron × Qg。 低输入电容 (Ciss)。 降低开关和传导损耗。 超低栅极电荷 (Qg)。...

  • 详情介绍
  • 数据手册
  • 价格&库存
SIHG33N60EF-GE3 数据手册
SiHG33N60EF www.vishay.com Vishay Siliconix EF Series Power MOSFET with Fast Body Diode FEATURES PRODUCT SUMMARY VDS (V) at TJ max. • Fast body diode MOSFET using E series technology • Reduced trr, Qrr, and IRRM • Low figure-of-merit (FOM): Ron x Qg • Low input capacitance (Ciss) • Reduced switching and conduction losses • Ultra low gate charge (Qg) • Avalanche energy rated (UIS) • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 650 RDS(on) max. at 25 °C () VGS = 10 V 0.098 Qg (Max.) (nC) 155 Qgs (nC) 22 Qgd (nC) 43 Configuration Single D TO-247AC APPLICATIONS • Telecommunications - Server and telecom power supplies • Lighting - High-intensity discharge (HID) - Light emitting diodes (LEDs) • Consumer and computing - ATX power supplies • Industrial - Welding - Battery chargers • Renewable energy - Solar (PV inverters) • Switch mode power suppliers (SMPS) • Applications using the following topologies - LLC - Phase shifted bridge (ZVS) - 3-level inverter - AC/DC bridge G S D S G N-Channel MOSFET ORDERING INFORMATION Package TO-247AC Lead (Pb)-free and Halogen-free SiHG33N60EF-GE3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 600 Gate-Source Voltage VGS ± 30 Continuous Drain Current (TJ = 150 °C) VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Current (Typical) a ID Maximum Power Dissipation Operating Junction and Storage Temperature Range Drain-Source Voltage Slope TJ = 125 °C Reverse Diode dV/dt d Soldering Recommendations (Peak Temperature) c for 10 s V 33 21 A IDM 100 2.2 W/°C EAS 691 mJ Linear Derating Factor Single Pulse Avalanche Energy b UNIT PD 278 W TJ, Tstg -55 to +150 °C dV/dt 70 50 300 V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 , IAS = 7 A. c. 1.6 mm from case. d. ISD  ID, dI/dt = 900 A/μs, starting TJ = 25 °C. S17-0295-Rev. C, 27-Feb-17 Document Number: 91590 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG33N60EF www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 40 Maximum Junction-to-Case (Drain) RthJC - 0.45 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage (N) Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance a VDS VGS = 0 V, ID = 250 μA 600 - - V VDS/TJ Reference to 25 °C, ID = 1 mA - 0.72 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V VGS = ± 20 V - - ± 100 nA μA IGSS IDSS RDS(on) gfs VGS = ± 30 V - - ±1 VDS = 480 V, VGS = 0 V - - 1 VDS = 480 V, VGS = 0 V, TJ = 125 °C - - 500 - 0.085 0.098  - 12 - S VGS = 10 V ID = 16.5 A VDS = 30 V, ID = 16.5 A μA Dynamic Input Capacitance Ciss VGS = 0 V, - 3454 - Output Capacitance Coss VDS = 100 V, - 154 - Reverse Transfer Capacitance Crss f = 1 MHz - 8 - Effective Output Capacitance, Energy Related b Co(er) - 121 - Effective Output Capacitance, Time Related c Co(tr) - 437 - - 103 155 - 22 - pF VGS = 0 V, VDS = 0 V to 480 V Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd - 43 - Turn-On Delay Time td(on) - 28 56 tr VDD = 480 V, ID = 16.5 A Rg = 9.1 , VGS = 10 V - 43 86 - 161 242 - 48 96 f = 1 MHz, open drain 0.2 0.5 1.0 - - 33 S - 100 - TJ = 25 °C, IS = 16.5 A, VGS = 0 V - 0.9 1.2 V - 162 324 ns - 1.0 2.0 μC - 13 - A Rise Time Turn-Off Delay Time td(off) Fall Time tf Gate Input Resistance Rg VGS = 10 V ID = 16.5 A, VDS = 480 V nC ns  Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Current ISM Diode Forward Voltage VSD Reverse Recovery Time trr Reverse Recovery Charge Qrr Reverse Recovery Current IRRM MOSFET symbol showing the  integral reverse p - n junction diode D A G TJ = 25 °C, IF = IS = 16.5 A, dI/dt = 100 A/μs, VR = 400 V Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDS. c. Coss(tr) is a fixed capacitance that gives the charging time as Coss while VDS is rising from 0 % to 80 % VDS. S17-0295-Rev. C, 27-Feb-17 Document Number: 91590 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG33N60EF www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 3.0 120 TOP 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V 80 ID = 16.5 A RDS(on), Drain-to-Source On-Resistance (Normalized) ID, Drain-to-Source Current (A) 100 TJ = 25 °C 60 40 20 2.5 2.0 1.5 1.0 VGS = 10 V 0.5 0 0 0 5 10 15 20 25 - 60 - 40 - 20 30 80 40 60 80 100 120 140 160 10 000 TOP 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V TJ = 150 °C Ciss VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds shorted Crss = Cgd Coss = Cds + Cgd 1000 C, Capacitance (pF) ID, Drain-to-Source Current (A) 20 Fig. 4 - Normalized On-Resistance vs. Temperature Fig. 1 - Typical Output Characteristics 60 0 TJ, Junction Temperature (°C) VDS, Drain-to-Source Voltage (V) 40 20 Coss 100 Crss 10 0 1 0 5 10 15 20 25 VDS, Drain-to-Source Voltage (V) 30 0 100 200 300 400 500 VDS, Drain-to-Source Voltage (V) 600 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 2 - Typical Output Characteristics 25 120 5000 80 60 TJ = 150 °C 15 Eoss Coss 500 10 Eoss (μJ) 20 Coss (pF) ID, Drain-to-Source Current (A) 100 40 5 20 VDS = 26.4 V 50 0 0 5 10 15 20 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S17-0295-Rev. C, 27-Feb-17 25 0 0 100 200 300 VDS 400 500 600 Fig. 6 - Coss and Eoss vs. VDS Document Number: 91590 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG33N60EF www.vishay.com Vishay Siliconix 40 VDS = 480 V VDS = 300 V VDS = 120 V 20 30 ID, Drain Current (A) VGS, Gate-to-Source Voltage (V) 24 16 12 8 20 10 4 0 0 0 40 80 120 160 Qg, Total Gate Charge (nC) 200 Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage 25 50 75 100 125 TC, Case Temperature (°C) 150 Fig. 10 - Maximum Drain Current vs. Case Temperature 750 VDS, Drain-to-Source Breakdown Voltage (V) ISD, Reverse Drain Current (A) 100 TJ = 150 °C 10 TJ = 25 °C 1 VGS = 0 V 0.1 0.2 0.4 0.6 0.8 1.0 1.2 VSD, Source-Drain Voltage (V) 1.4 1.6 Fig. 8 - Typical Source-Drain Diode Forward Voltage Operation in this Area Limited by RDS(on) ID, Drain Current (A) 100 725 700 675 650 625 600 575 ID = 250 μA 550 -60 -40 -20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 11 - Typical Drain-to-Source Voltage vs. Temperature IDM Typical 10 Limited by RDS(on)* 100 μs 1 1 ms TC = 25 °C TJ = 150 °C Single Pulse 10 ms BVDSS Limited 0.1 1 10 100 1000 VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Fig. 9 - Maximum Safe Operating Area S17-0295-Rev. C, 27-Feb-17 Document Number: 91590 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG33N60EF www.vishay.com Vishay Siliconix 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 0.0001 0.001 0.01 0.1 1 Pulse Time (s) Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case RD VDS VDS tp VGS VDD D.U.T. RG + - VDD VDS 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % IAS Fig. 13 - Switching Time Test Circuit Fig. 16 - Unclamped Inductive Waveforms VDS QG 10 V 90 % QGS 10 % VGS QGD VG td(on) td(off) tf tr Charge Fig. 14 - Switching Time Waveforms Fig. 17 - Basic Gate Charge Waveform Current regulator Same type as D.U.T. L Vary tp to obtain required IAS VDS 50 kΩ D.U.T RG 12 V + - IAS 0.2 µF 0.3 µF V DD + D.U.T. - VDS 10 V tp 0.01 Ω VGS 3 mA Fig. 15 - Unclamped Inductive Test Circuit IG ID Current sampling resistors Fig. 18 - Gate Charge Test Circuit S17-0295-Rev. C, 27-Feb-17 Document Number: 91590 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG33N60EF www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 19 - For N-Channel           Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91590. S17-0295-Rev. C, 27-Feb-17 Document Number: 91590 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix TO-247AC (High Voltage) VERSION 1: FACILITY CODE = 9 MILLIMETERS DIM. MIN. MAX. A 4.83 A1 2.29 MILLIMETERS NOTES DIM. MIN. MAX. NOTES 5.21 D1 16.25 16.85 5 2.55 D2 0.56 0.76 A2 1.50 2.49 E 15.50 15.87 b 1.12 1.33 E1 13.46 14.16 5 b1 1.12 1.28 E2 4.52 5.49 3 b2 1.91 2.39 b3 1.91 2.34 b4 2.87 3.22 b5 2.87 3.18 c 0.55 0.69 c1 0.55 0.65 D 20.40 20.70 4 6 e L 14.90 15.40 6, 8 L1 3.96 4.16 6 ØP 3.56 3.65 7 6 4 5.44 BSC Ø P1 7.19 ref. Q 5.31 5.69 S 5.54 5.74 Notes (1) Package reference: JEDEC® TO247, variation AC (2) All dimensions are in mm (3) Slot required, notch may be rounded (4) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outermost extremes of the plastic body (5) Thermal pad contour optional with dimensions D1 and E1 (6) Lead finish uncontrolled in L1 (7) Ø P to have a maximum draft angle of 1.5° to the top of the part with a maximum hole diameter of 3.91 mm (8) Dimension b2 and b4 does not include dambar protrusion. Allowable dambar protrusion shall be 0.1 mm total in excess of b2 and b4 dimension at maximum material condition Revision: 19-Oct-2020 Document Number: 91360 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix VERSION 2: FACILITY CODE = Y A A 4 E B 3 R/2 E/2 7 ØP Ø k M DBM A2 S (Datum B) ØP1 A D2 Q 4 4 2xR (2) D1 D 1 2 4 D 3 Thermal pad 5 L1 C L See view B 2 x b2 3xb 0.10 M C A M 4 E1 A 0.01 M D B M View A - A C 2x e A1 b4 (b1, b3, b5) Planting Lead Assignments 1. Gate 2. Drain 3. Source 4. Drain D DE Base metal E C (c) C c1 (b, b2, b4) (4) Section C - C, D - D, E - E View B MILLIMETERS DIM. MIN. MAX. A 4.58 5.31 MILLIMETERS NOTES DIM. MIN. MAX. D2 0.51 1.30 15.87 A1 2.21 2.59 E 15.29 A2 1.17 2.49 E1 13.72 b 0.99 1.40 e 5.46 BSC b1 0.99 1.35 Øk b2 1.53 2.39 L 14.20 16.25 b3 1.65 2.37 L1 3.71 4.29 b4 2.42 3.43 ØP 3.51 3.66 b5 2.59 3.38 Ø P1 - 7.39 c 0.38 0.86 Q 5.31 5.69 4.52 c1 0.38 0.76 R D 19.71 20.82 S D1 13.08 - NOTES 0.254 5.49 5.51 BSC Notes (1) Dimensioning and tolerancing per ASME Y14.5M-1994 (2) Contour of slot optional (3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body (4) Thermal pad contour optional with dimensions D1 and E1 (5) Lead finish uncontrolled in L1 (6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154") (7) Outline conforms to JEDEC outline TO-247 with exception of dimension c Revision: 19-Oct-2020 Document Number: 91360 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix VERSION 3: FACILITY CODE = N A E R/2 D2 B A P A2 D1 L1 D D K M D BM R S Q N P1 b2 L C e b b4 C E1 A1 0.01 M D B M 0.10 M C A M b1, b3, b5 c c1 Base metal Plating b, b2, b4 MILLIMETERS MILLIMETERS DIM. MIN. MAX. DIM. MIN. A 4.65 5.31 D2 0.51 MAX. 1.35 A1 2.21 2.59 E 15.29 15.87 13.46 A2 1.17 1.37 E1 b 0.99 1.40 e - b1 0.99 1.35 k b2 1.65 2.39 L 14.20 b3 1.65 2.34 L1 3.71 b4 2.59 3.43 N b5 2.59 3.38 P 3.56 c 0.38 0.89 P1 - 7.39 c1 0.38 0.84 Q 5.31 5.69 D 19.71 20.70 R 4.52 D1 13.08 - S 5.46 BSC 0.254 16.10 4.29 7.62 BSC 3.66 5.49 5.51 BSC ECN: E20-0545-Rev. F, 19-Oct-2020 DWG: 5971 Notes (1) Dimensioning and tolerancing per ASME Y14.5M-1994 (2) Contour of slot optional (3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body (4) Thermal pad contour optional with dimensions D1 and E1 (5) Lead finish uncontrolled in L1 (6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154") Revision: 19-Oct-2020 Document Number: 91360 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer's technical experts. Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited to the warranty expressed therein. Hyperlinks included in this datasheet may direct users to third-party websites. These links are provided as a convenience and for informational purposes only. Inclusion of these hyperlinks does not constitute an endorsement or an approval by Vishay of any of the products, services or opinions of the corporation, organization or individual associated with the third-party website. Vishay disclaims any and all liability and bears no responsibility for the accuracy, legality or content of the third-party website or for that of subsequent links. Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. © 2022 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED Revision: 01-Jan-2022 1 Document Number: 91000
SIHG33N60EF-GE3
物料型号:SiHG33N60EF

器件简介:SiHG33N60EF是一款由Vishay Siliconix生产的N-Channel MOSFET,属于EF系列,具有快速体二极管,使用E系列技术制造。它符合RoHS标准,无卤素。

引脚分配:文档中提供了两种版本的封装信息,包括TO-247AC。引脚分配为1. Gate,2. Source,3. Drain,4. Drain。

参数特性: - 漏源电压(Vps):600V - 栅源电压(VGs):±30V - 连续漏电流(Id):33A(Tc=25°C时) - 脉冲漏电流(IOM):100A(典型值) - 单一脉冲雪崩能量(EAS):691mJ - 最大功耗(Pd):278W - 工作结温范围(TJ,Tstg):-55°C至+150°C - 漏源电压斜率(dV/dt):70V/ns

功能详解: - 该MOSFET具有低导通电阻(Ron)和低输入电容(Ciss),减少了开关和传导损耗。 - 具有超低栅极电荷(Qg),提高了开关速度。 - 额定雪崩能量,增强了器件的耐压能力。

应用信息: - 适用于电信、服务器和电信电源、高强度放电灯(HID)、发光二极管(LED)照明、消费和计算设备ATX电源、工业焊接、电池充电器、可再生能源如太阳能(PV逆变器)、开关模式电源供应器(SMPS)等。

封装信息: - 提供了TO-247AC封装的详细尺寸和引脚分配,包括不同版本(Facility Code = 9, Y, N)的尺寸差异。
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