SiHH180N60E
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Vishay Siliconix
E Series Power MOSFET
FEATURES
Pin 4: drain
• 4th generation E series technology
PowerPAK® 8 x 8
• Low figure-of-merit (FOM) Ron x Qg
• Low effective capacitance (Co(er))
Pin 1:
gate
4
1
2
• Reduced switching and conduction losses
• Avalanche energy rated (UIS)
Pin 2:
Kelvin connection
3
• Kelvin connection for reduced gate noise
Pin 3: source
3
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
N-Channel MOSFET
APPLICATIONS
•
•
•
•
Server and telecom power supplies
Switch mode power supplies (SMPS)
Power factor correction power supplies (PFC)
Lighting
- High-intensity discharge (HID)
- Fluorescent ballast lighting
• Industrial
- Welding
- Induction heating
- Motor drives
- Battery chargers
- Solar (PV inverters)
PRODUCT SUMMARY
VDS (V) at TJ max.
RDS(on) typ. () at 25 °C
650
VGS = 10 V
Qg max. (nC)
0.155
33
Qgs (nC)
7
Qgd (nC)
11
Configuration
Single
ORDERING INFORMATION
Package
PowerPAK 8 x 8
Lead (Pb)-free and halogen-free
SiHH180N60E-T1-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-source voltage
VDS
600
Gate-source voltage
VGS
± 30
Continuous drain current (TJ = 150 °C)
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed drain current a
ID
Maximum power dissipation
Operating junction and storage temperature range
Drain-source voltage slope
TJ = 125 °C
Reverse diode dv/dt c
V
19
12
A
IDM
44
0.9
W/°C
EAS
111
mJ
Linear derating factor
Single pulse avalanche energy b
UNIT
PD
114
W
TJ, Tstg
-55 to +150
°C
dv/dt
100
22
V/ns
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature
b. VDD = 120 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 , IAS = 2.8 A
c. ISD ID, di/dt = 100 A/μs, starting TJ = 25 °C
S20-0339-Rev. C, 11-May-2020
Document Number: 92106
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHH180N60E
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Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum junction-to-ambient
RthJA
42
55
Maximum junction-to-case (drain)
RthJC
0.76
1.1
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
VDS temperature coefficient
Gate-source threshold voltage (N)
Gate-source leakage
Zero gate voltage drain current
VDS
VGS = 0 V, ID = 250 μA
600
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.63
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
3.0
-
5.0
V
VGS = ± 20 V
-
-
± 100
nA
VGS = ± 30 V
-
-
±1
μA
VDS = 600 V, VGS = 0 V
-
-
1
VDS = 480 V, VGS = 0 V, TJ = 125 °C
-
-
10
IGSS
IDSS
μA
-
0.155
0.180
gfs
VDS = 20 V, ID = 9.5 A
-
5.3
-
S
Input capacitance
Ciss
-
1085
-
Output capacitance
Coss
-
56
-
Reverse transfer capacitance
Crss
VGS = 0 V,
VDS = 100 V,
f = 1 MHz
-
5
-
Effective output capacitance, energy
related a
Co(er)
-
41
-
Effective output capacitance, time
related b
Co(tr)
-
251
-
-
22
33
-
7
-
-
11
-
Drain-source on-state resistance
Forward transconductance a
RDS(on)
VGS = 10 V
ID = 9.5 A
Dynamic
pF
VDS = 0 V to 480 V, VGS = 0 V
Total gate charge
Qg
Gate-source charge
Qgs
Gate-drain charge
Qgd
Turn-on delay time
td(on)
Rise time
Turn-off delay time
tr
td(off)
Fall time
tf
Gate input resistance
Rg
VGS = 10 V
ID = 9.5 A, VDS = 480 V
-
14
28
VDD = 480 V, ID = 9.5 A,
VGS = 10 V, Rg = 9.1
-
49
98
-
22
44
-
23
46
f = 1 MHz
0.3
0.7
1.4
-
-
19
nC
ns
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
IS
Pulsed diode forward current
ISM
Diode forward voltage
VSD
Reverse recovery time
trr
Reverse recovery charge
Qrr
Reverse recovery current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 9.5 A, VGS = 0 V
TJ = 25 °C, IF = IS = 9.5 A,
di/dt = 100 A/μs, VR = 25 V
S
-
-
44
-
-
1.2
-
282
564
ns
-
3.6
7.2
μC
-
24
-
A
V
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS
S20-0339-Rev. C, 11-May-2020
Document Number: 92106
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHH180N60E
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Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
45
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
35
30
25
TJ = 25 °C
ID = 9.5 A
RDS(on), Drain-to-Source On-Resistance
(Normalized)
40
ID, Drain-to-Source Current (A)
3.0
TOP
20
15
10
5
0
2.0
1.5
1.0
VGS = 10 V
0.5
0
0
5
10
15
VDS, Drain-to-Source Voltage (V)
-60 -40 -20
20
Fig. 1 - Typical Output Characteristics
32
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
20
Fig. 4 - Normalized On-Resistance vs. Temperature
TJ = 150 °C
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds shorted
Crss = Cgd
Coss = Cds + Cgd
10 000
C, Capacitance (pF)
24
0 20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
100 000
TOP
28
ID, Drain-to-Source Current (A)
2.5
16
12
Ciss
1000
100
Coss
10
Crss
8
4
0
1
5
10
15
VDS, Drain-to-Source Voltage (V)
20
Fig. 2 - Typical Output Characteristics
0
100
200
300
400
500
VDS, Drain-to-Source Voltage (V)
600
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
10 000
45
9
8
40
Coss, Output Capacitance (pF)
ID, Drain-to-Source Current (A)
TJ = 25 °C
35
30
TJ = 150 °C
25
20
15
10
7
1000
6
5
Eoss
4
100
3
Coss
2
1
5
VDS = 29.5 V
10
0
0
5
10
15
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S20-0339-Rev. C, 11-May-2020
20
0
0
100
200
300
400
500
Eoss, Output Capacitance Stored Energy (μJ)
0
600
VDS, Drain-to-Source Voltage (V)
Fig. 6 - Coss and Eoss vs. VDS
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SiHH180N60E
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20
VDS = 480 V
VDS = 300 V
VDS = 120 V
16
9
ID, Drain Current (A)
VGS, Gate-to-Source Voltage (V)
12
Vishay Siliconix
6
8
3
4
0
0
0
7
14
21
Qg, Total Gate Charge (nC)
25
28
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
50
75
100
125
TC, Case Temperature (°C)
150
Fig. 10 - Maximum Drain Current vs. Case Temperature
100
775
VDS, Drain-to-Source Breakdown Voltage (V)
ISD, Reverse Drain Current (A)
12
TJ = 150 °C
10
TJ = 25 °C
1
VGS = 0 V
0.1
0.2
0.4
0.6
0.8
1.0
VSD, Source-Drain Voltage (V)
1.2
1.4
Fig. 8 - Typical Source-Drain Diode Forward Voltage
750
725
700
675
650
ID = 250 μA
625
600
575
-60 -40 -20
0 20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 11 - Temperature vs. Drain-to-Source Voltage
1000
ID, Drain Current (A)
100
Operation in this area
limited by RDS(on)
IDM limited
10
100 μs
Limited by RDS(on)a
1
1 ms
TC = 25 °C,
TJ = 150 °C,
single pulse
0.1
10 ms
BVDSS limited
0.01
1
10
100
VDS, Drain-to-Source Voltage (V)
1000
Fig. 9 - Maximum Safe Operating Area
Note
a. VGS > minimum VGS at which RDS(on) is specified
S20-0339-Rev. C, 11-May-2020
Document Number: 92106
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHH180N60E
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Vishay Siliconix
1
Normalized Effective Transient
Thermal Impedance
Duty cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single pulse
0.01
0.000001
0.00001
0.0001
0.001
Pulse Time (s)
0.01
0.1
1
Fig. 12 - Normalized Transient Thermal Impedance, Junction-to-Case
1
Normalized Effective Transient
Thermal Impedance
Duty cycle = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
Single pulse
0.001
0.0001
0.001
0.01
0.1
1
10
100
1000
Pulse Time (s)
Fig. 13 - Normalized Thermal Transient Impedance, Junction-to-Ambient
VDS
VGS
Rg
RD
VDS
90 %
D.U.T.
+
- VDD
10 V
Pulse width ≤ 1 μs
Duty factor ≤ 0.1 %
10 %
VGS
td(on)
tr
td(off)
tf
Fig. 15 - Switching Time Waveforms
Fig. 14 - Switching Time Test Circuit
S20-0339-Rev. C, 11-May-2020
Document Number: 92106
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SiHH180N60E
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Vishay Siliconix
L
VDS
Vary tp to obtain
required IAS
D.U.T.
Rg
+
- VDD
IAS
10 V
tp
0.01 Ω
Fig. 16 - Unclamped Inductive Test Circuit
VDS
tp
VDD
VDS
IAS
Fig. 17 - Unclamped Inductive Waveforms
Qg
10 V
Qgs
Qgd
VG
Charge
Fig. 18 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
50 kΩ
12 V
0.2 μF
0.3 μF
+
D.U.T.
-
VDS
VGS
3 mA
IG
ID
Current sampling resistors
Fig. 19 - Gate Charge Test Circuit
S20-0339-Rev. C, 11-May-2020
Document Number: 92106
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SiHH180N60E
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Vishay Siliconix
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
3
+
2
-
-
4
+
1
Rg
•
•
•
•
1 Driver gate drive
Period
P.W.
+
V
- DD
dv/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
D=
P.W.
Period
V GS = 10 V a
2
D.U.T. ISD waveform
Reverse
recovery
current
3 D.U.T. VDS
Body diode forward
current
di/dt
waveform
Diode recovery
dv/dt
Re-applied
voltage
V DD
Body diode forward drop
4 Inductor current
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 20 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?92106.
S20-0339-Rev. C, 11-May-2020
Document Number: 92106
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Package Information
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Vishay Siliconix
PowerPAK® 8 x 8 Case Outline
D2
D3
2x
E3
0.1 C A
D
A
2x
0.1 C B
K
E
E2
PPAK 8 x 8
(8 mm x 8 mm)
L
B
e
Pin 1 dot 5, 6
by marking
TOP SIDE VIEW
b
0.08 C
A1
DIM.
A2
A
BACK SIDE VIEW
MILLIMETERS
INCHES
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A
0.95
1.00
1.05
0.037
0.039
0.041
A1
0.00
-
0.05
0.000
-
0.002
A2
020 ref.
0.008 ref.
b
0.95
1.00
1.05
0.037
0.039
0.041
D
7.90
8.00
8.10
0.311
0.315
0.319
D2
7.10
7.20
7.30
0.280
0.283
0.287
D3
0.40 BSC
e
0.016 BSC
2.00 BSC
0.079 BSC
E
7.90
8.00
8.10
0.311
0.315
0.319
E2
4.30
4.35
4.40
0.169
0.171
0.173
E3
0.40 BSC
K
L
0.016 BSC
2.75 BSC
0.45
N (3)
0.50
0.108 BSC
0.55
8
0.018
0.020
0.022
8
Notes
(1) Use millimeters as the primary measurement
(2) Dimensioning and tolerances conform to ASME Y14.5 M - 1994
(3) N is the number of terminals
(4) The pin 1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
(5) Exact shape and size of this feature is optional
ECN: E20-0518-Rev. B, 28-Sep-2020
DWG: 6041
Revision: 28-Sep-2020
1
Document Number: 67859
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PAD Pattern
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Vishay Siliconix
Recommended Minimum PADs for PowerPAK® 8 mm x 8 mm
8.3
7.3
0.68
4.45
0.4
2.65
0.37
0.7
1.1
2
Dimensions in millimeters
Revision: 07-Apr-16
Document Number: 68441
1
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Revision: 09-Jul-2021
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Document Number: 91000