SiHH24N65E
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Vishay Siliconix
E Series Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V) at TJ max.
• Completely lead (Pb)-free device
700
RDS(on) typ. () at 25 °C
VGS = 10 V
• Low figure-of-merit (FOM) Ron x Qg
0.130
Qg max. (nC)
116
• Low input capacitance (Ciss)
Qgs (nC)
19
• Reduced switching and conduction losses
33
• Ultra low gate charge (Qg)
Qgd (nC)
Configuration
Single
PowerPAK® 8 x 8
• Avalanche energy rated (UIS)
• Kelvin connection for reduced gate noise
Pin 4
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
4
Pin 1
APPLICATIONS
1
2
3
• Server and telecom power supplies
Pin 2
• Switch mode power supplies (SMPS)
3
• Power factor correction power supplies (PFC)
Pin 3
N-Channel MOSFET
• Lighting
- High-intensity discharge (HID)
- Fluorescent ballast lighting
• Industrial
- Welding
- Induction heating
- Motor drives
- Battery chargers
- Renewable energy
- Solar (PV inverters)
ORDERING INFORMATION
Package
PowerPAK 8 x 8
Lead (Pb)-free and Halogen-free
SiHH24N65E-T1-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
650
Gate-Source Voltage
VGS
± 30
Continuous Drain Current (TJ = 150 °C)
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Current a
ID
IDM
Linear Derating Factor
UNIT
V
23
15
A
58
1.61
W/°C
Single Pulse Avalanche Energy b
EAS
353
mJ
Maximum Power Dissipation
PD
202
W
TJ, Tstg
-55 to +150
°C
Operating Junction and Storage Temperature Range
Drain-Source Voltage Slope
TJ = 125 °C
Reverse Diode dV/dt c
dV/dt
70
16
V/ns
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. VDD = 140 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 , IAS = 5 A.
c. ISD ID, dI/dt = 100 A/μs, starting TJ = 25 °C.
S16-0524-Rev. A, 21-Mar-16
Document Number: 91784
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHH24N65E
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Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
38
50
Maximum Junction-to-Case (Drain)
RthJC
0.48
0.62
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage (N)
VDS
VGS = 0 V, ID = 250 μA
650
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.75
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
VGS = ± 20 V
-
-
± 100
nA
VGS = ± 30 V
-
-
±1
μA
VDS = 650 V, VGS = 0 V
-
-
1
VDS = 520 V, VGS = 0 V, TJ = 125 °C
-
-
25
Gate-Source Leakage
IGSS
Zero Gate Voltage Drain Current
IDSS
μA
-
0.130
0.150
gfs
VDS = 30 V, ID = 12 A
-
8.2
-
S
Input Capacitance
Ciss
2814
-
Coss
-
121
-
Reverse Transfer Capacitance
Crss
VGS = 0 V,
VDS = 100 V,
f = 1 MHz
-
Output Capacitance
-
5
-
Effective Output Capacitance, Energy
Related a
Co(er)
-
88
-
Effective Output Capacitance, Time
Related b
Co(tr)
-
365
-
-
77
116
-
19
-
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
VGS = 10 V
ID = 12 A
Dynamic
pF
VDS = 0 V to 520 V, VGS = 0 V
Total Gate Charge
Qg
Gate-Source Charge
Qgs
VGS = 10 V
ID = 12 A, VDS = 520 V
Gate-Drain Charge
Qgd
-
33
-
Turn-On Delay Time
td(on)
-
29
58
Rise Time
Turn-Off Delay Time
tr
td(off)
Fall Time
tf
Gate Input Resistance
Rg
VDD = 520 V, ID = 12 A,
VGS = 10 V, Rg = 9.1
-
59
71
-
78
117
-
46
92
f = 1 MHz, open drain
0.27
0.55
1.10
-
-
23
-
-
58
nC
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Current
ISM
Diode Forward Voltage
VSD
Reverse Recovery Time
trr
Reverse Recovery Charge
Qrr
Reverse Recovery Current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 12 A, VGS = 0 V
TJ = 25 °C, IF = IS = 12 A,
dI/dt = 100 A/μs, VR = 25 V
S
-
0.9
1.2
V
-
436
872
ns
-
7.4
14.8
μC
-
29
-
A
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDS.
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS.
S16-0524-Rev. A, 21-Mar-16
Document Number: 91784
2
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHH24N65E
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Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
3.0
60
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
40
ID = 12 A
TJ = 25 °C
RDS(on), Drain-to-Source On-Resistance
(Normalized)
ID, Drain-to-Source Current (A)
TOP
20
2.5
2.0
1.5
1.0
VGS = 10 V
0.5
0
0
-60 -40 -20
0
5
10
15
VDS, Drain-to-Source Voltage (V)
20
40
60
80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 1 - Typical Output Characteristics
10 000
40
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
30
TJ = 150 °C
Ciss
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds shorted
Crss = Cgd
Coss = Cds + Cgd
1000
C, Capacitance (pF)
20
Coss
100
Crss
10
10
1
0
0
5
10
15
VDS, Drain-to-Source Voltage (V)
0
20
100
200
300
400
500
600
VDS, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 2 - Typical Output Characteristics
80
16
14
60
12
10
Coss (pF)
ID, Drain-to-Source Current (A)
5000
TJ = 25 °C
40
TJ = 150 °C
Eoss
Coss
8
500
Eoss (μJ)
ID, Drain-to-Source Current (A)
0
20
6
20
4
2
VDS = 28.2 V
0
50
0
5
10
15
20
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S16-0524-Rev. A, 21-Mar-16
25
0
0
100
200
300
VDS
400
500
600
Fig. 6 - COSS and EOSS vs. VDS
Document Number: 91784
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For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHH24N65E
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Vishay Siliconix
25
VDS = 520 V
VDS = 325 V
VDS = 130 V
20
20
ID, Drain Current (A)
VGS, Gate-to-Source Voltage (V)
24
16
12
8
0
0
30
60
90
120
Qg, Total Gate Charge (nC)
25
150
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
50
75
100
125
TC, Case Temperature (°C)
150
Fig. 10 - Maximum Drain Current vs. Case Temperature
100
850
VDS, Drain-to-Source Breakdown Voltage (V)
ISD, Reverse Drain Current (A)
10
5
4
0
TJ = 150 °C
10
TJ = 25 °C
1
VGS = 0 V
0.1
0.2
0.4
0.6
0.8
1.0
1.2
VSD, Source-Drain Voltage (V)
1.4
1.6
Fig. 8 - Typical Source-Drain Diode Forward Voltage
Operation in this Area
Limited by RDS(on)
100
825
800
775
750
725
700
675
ID = 250 μA
650
-60 -40 -20
0 20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 11 - Temperature vs. Drain-to-Source Voltage
IDM Limited
10
ID, Drain Current (A)
15
100 μs
Limited by RDS(on)*
1
1 ms
10 ms
0.1
TC = 25 °C
TJ = 150 °C
Single Pulse
BVDSS Limited
0.01
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Fig. 9 - Maximum Safe Operating Area
S16-0524-Rev. A, 21-Mar-16
Document Number: 91784
4
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHH24N65E
www.vishay.com
Vishay Siliconix
1
Duty Cycle = 0.5
Normalized Effective Transient
Thermal Impedance
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
0.001
0.000001
0.00001
0.0001
0.001
Pulse Time (s)
0.01
0.1
1
Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case
1
Normalized Transient Thermal
Impedance, RthJA
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.01
0.02
Single Pulse
0.001
0.0001
0.0001
0.001
0.01
0.1
1
10
100
1000
Pulse Time (s)
Fig. 13 - Normalized Thermal Transient Impedance, Junction-to-Ambient
VDS
VGS
L
RD
Vary tp to obtain
required IAS
VDS
D.U.T.
RG
D.U.T
RG
+
- VDD
+
-
IAS
10 V
V DD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
0.01 Ω
tp
Fig. 14 - Switching Time Test Circuit
Fig. 16 - Unclamped Inductive Test Circuit
VDS
VDS
tp
90 %
VDD
VDS
10 %
VGS
td(on)
tr
td(off) tf
Fig. 15 - Switching Time Waveforms
S16-0524-Rev. A, 21-Mar-16
IAS
Fig. 17 - Unclamped Inductive Waveforms
Document Number: 91784
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHH24N65E
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Vishay Siliconix
Current regulator
Same type as D.U.T.
QG
10 V
50 kΩ
QGS
QGD
12 V
0.2 µF
0.3 µF
+
VG
D.U.T.
-
VDS
VGS
Charge
3 mA
IG
ID
Current sampling resistors
Fig. 18 - Basic Gate Charge Waveform
Fig. 19 - Gate Charge Test Circuit
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
Period
P.W.
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 20 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91784.
S16-0524-Rev. A, 21-Mar-16
Document Number: 91784
6
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
PowerPAK® 8 x 8 Case Outline
D2
D3
2x
E3
0.1 C A
D
A
2x
0.1 C B
K
E
E2
PPAK 8 x 8
(8 mm x 8 mm)
L
B
e
Pin 1 dot 5, 6
by marking
TOP SIDE VIEW
b
0.08 C
A1
DIM.
A2
A
BACK SIDE VIEW
MILLIMETERS
INCHES
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A
0.95
1.00
1.05
0.037
0.039
0.041
A1
0.00
-
0.05
0.000
-
0.002
A2
020 ref.
0.008 ref.
b
0.95
1.00
1.05
0.037
0.039
0.041
D
7.90
8.00
8.10
0.311
0.315
0.319
D2
7.10
7.20
7.30
0.280
0.283
0.287
D3
0.40 BSC
e
0.016 BSC
2.00 BSC
0.079 BSC
E
7.90
8.00
8.10
0.311
0.315
0.319
E2
4.30
4.35
4.40
0.169
0.171
0.173
E3
0.40 BSC
K
L
0.016 BSC
2.75 BSC
0.45
N (3)
0.50
0.108 BSC
0.55
8
0.018
0.020
0.022
8
Notes
(1) Use millimeters as the primary measurement
(2) Dimensioning and tolerances conform to ASME Y14.5 M - 1994
(3) N is the number of terminals
(4) The pin 1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
(5) Exact shape and size of this feature is optional
ECN: E20-0518-Rev. B, 28-Sep-2020
DWG: 6041
Revision: 28-Sep-2020
1
Document Number: 67859
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PAD Pattern
www.vishay.com
Vishay Siliconix
Recommended Minimum PADs for PowerPAK® 8 mm x 8 mm
8.3
7.3
0.68
4.45
0.4
2.65
0.37
0.7
1.1
2
Dimensions in millimeters
Revision: 07-Apr-16
Document Number: 68441
1
For technical questions, contact: pmostechsupport@vishay.com
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Legal Disclaimer Notice
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Vishay
Disclaimer
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Revision: 01-Jan-2022
1
Document Number: 91000
