SIHP12N50E-BE3

SiHP12N50E www.vishay.com Vishay Siliconix E Series Power MOSFET FEATURES D • Low figure-of-merit (FOM) Ron x Qg TO-220AB • Low input capacitance (Ciss) • Reduced switching and conduction losses • Low gate charge (Qg) G Available • Avalanche energy rated (UIS) G D • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 S S N-Channel MOSFET APPLICATIONS • Computing PRODUCT SUMMARY - PC silver box / ATX power supplies VDS (V) at TJ max. 550 RDS(on) max. at 25 °C () VGS = 10 V Qg max. (nC) • Lighting 0.380 - Two stage LED lighting 50 Qgs (nC) 6 Qgd (nC) 10 Configuration • Consumer electronics • Applications using hard switched topologies - Power factor correction (PFC) Single - Two switch forward converter - Flyback converter • Switch mode power supplies (SMPS) ORDERING INFORMATION Package TO-220AB SiHP12N50E-BE3 a Lead (Pb)-free and halogen-free SiHP12N50E-GE3 Note a. “-BE3” denotes alternate manufacturing location ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-source voltage VDS 500 Gate-source voltage VGS ± 30 Continuous drain current (TJ = 150 °C) VGS at 10 V TC = 25 °C TC = 100 °C Pulsed drain current a ID IDM Linear derating factor Single pulse avalanche energy b Maximum power dissipation Operating junction and storage temperature range Drain-source voltage slope TJ = 125 °C Reverse diode dV/dt d Soldering recommendations (peak temperature) c For 10 s UNIT V 10.5 6.6 A 21 0.91 W/°C EAS 103 mJ PD 114 W TJ, Tstg -55 to +150 °C dV/dt 70 27 300 V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature b. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 , IAS = 2.7 A c. 1.6 mm from case d. ISD  ID, dI/dt = 100 A/μs, starting TJ = 25 °C S22-0948-Rev. D, 21-Nov-2022 Document Number: 91617 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHP12N50E www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum junction-to-ambient RthJA - 62 Maximum junction-to-case (drain) RthJC - 1.1 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-source breakdown voltage VDS temperature coefficient Gate-source threshold Voltage (N) VDS VGS = 0 V, ID = 250 μA 500 - - V VDS/TJ Reference to 25 °C, ID = 1 mA - 0.60 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V VGS = ± 20 V - - ± 100 nA VGS = ± 30 V - - ±1 μA VDS = 500 V, VGS = 0 V - - 1 VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 10 Gate-source leakage IGSS Zero gate voltage drain current IDSS μA - 0.330 0.380  gfs VDS = 30 V, ID = 6 A - 3.1 - S Input capacitance Ciss 886 - Coss - 52 - Reverse transfer capacitance Crss VGS = 0 V, VDS = 100 V, f = 1 MHz - Output capacitance - 6 - Effective output capacitance, energy related a Co(er) - 45 - Effective output capacitance, time  related b Co(tr) - 131 - - 25 50 - 6 - Drain-source on-state resistance Forward transconductance RDS(on) VGS = 10 V ID = 6 A Dynamic pF VDS = 0 V to 400 V, VGS = 0 V Total gate charge Qg Gate-source charge Qgs VGS = 10 V ID = 6 A, VDS = 400 V Gate-drain charge Qgd - 10 - Turn-on delay time td(on) - 13 26 Rise time Turn-off delay time tr td(off) Fall time tf Gate input resistance Rg nC VDD = 400 V, ID = 6 A, VGS = 10 V, Rg = 9.1  - 16 32 - 29 58 - 12 24 f = 1 MHz, open drain - 0.92 - - - 10.5 - - 21 - - 1.2 V - 244 - ns - 2.5 - μC - 19 - A ns  Drain-Source Body Diode Characteristics Continuous source-drain diode current IS Pulsed diode forward current ISM Diode forward voltage VSD Reverse recovery time trr Reverse recovery charge Qrr Reverse recovery current IRRM MOSFET symbol showing the  integral reverse p - n junction diode D A G TJ = 25 °C, IS = 7.5 A, VGS = 0 V TJ = 25 °C, IF = IS = 6 A, dI/dt = 100 A/μs, VR = 25 V S Notes a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS S22-0948-Rev. D, 21-Nov-2022 Document Number: 91617 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHP12N50E www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 30 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V 24 18 3.0 TJ = 25 °C ID = 6 A RDS(on), Drain-to-Source On-Resistance (Normalized) 12 6 0 2.0 1.5 1.0 VGS = 10 V 0.5 0 0 5 10 15 20 25 VDS, Drain-to-Source Voltage (V) 30 - 60 - 40 - 20 Fig. 1 - Typical Output Characteristics TOP 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V 12 10 000 TJ = 150 °C 8 VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds shorted Crss = Cgd Coss = Cds + Cgd Ciss 1000 C, Capacitance (pF) 16 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 4 - Normalized On-Resistance vs. Temperature 20 ID, Drain-to-Source Current (A) 2.5 100 Coss Crss 10 4 0 1 0 5 10 15 20 25 VDS, Drain-to-Source Voltage (V) 30 Fig. 2 - Typical Output Characteristics 0 100 200 300 400 VDS, Drain-to-Source Voltage (V) 500 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 30 6 5000 5 TJ = 25 °C 20 4 Coss (pF) ID, Drain-to-Source Current (A) 25 15 TJ = 150 °C Eoss Coss 3 500 10 Eoss (μJ) ID, Drain-to-Source Current (A) TOP 2 VDS = 30.4 V 5 1 0 50 0 5 10 15 20 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S22-0948-Rev. D, 21-Nov-2022 25 0 0 100 200 300 400 500 VDS Fig. 6 - Coss and Eoss vs. VDS Document Number: 91617 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHP12N50E www.vishay.com Vishay Siliconix 12 VDS = 400 V VDS = 250 V VDS = 100 V 20 9 ID, Drain Current (A) VGS, Gate-to-Source Voltage (V) 24 16 12 8 3 4 0 0 0 10 20 30 40 Qg, Total Gate Charge (nC) 50 Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage 25 50 75 100 125 TC, Case Temperature (°C) 150 Fig. 10 - Maximum Drain Current vs. Case Temperature 650 VDS, Drain-to-Source Breakdown Voltage (V) 100 ISD, Reverse Drain Current (A) 6 TJ = 150 °C 10 TJ = 25 °C 1 VGS = 0 V 0.1 0.2 0.4 0.6 0.8 1.0 VSD, Source-Drain Voltage (V) 1.2 1.4 600 575 550 525 500 ID = 250 μA 475 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 8 - Typical Source-Drain Diode Forward Voltage 100 625 Fig. 11 - Temperature vs. Drain-to-Source Voltage Operation in this Area Limited by RDS(on) ID, Drain Current (A) IDM Limited 10 100 μs Limited by RDS(on)* 1 1 ms 0.1 10 ms TC = 25 °C TJ = 150 °C Single Pulse BVDSS Limited 0.01 1 10 100 1000 VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Fig. 9 - Maximum Safe Operating Area S22-0948-Rev. D, 21-Nov-2022 Document Number: 91617 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHP12N50E www.vishay.com Vishay Siliconix 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.05 0.1 0.02 Single Pulse 0.01 0.0001 0.001 0.01 Pulse Time (s) 0.1 1 Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case RD VDS VDS tp VGS VDD D.U.T. RG + - VDD VDS 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % IAS Fig. 13 - Switching Time Test Circuit Fig. 16 - Unclamped Inductive Waveforms VDS QG 10 V 90 % QGS 10 % VGS QGD VG td(on) td(off) tf tr Charge Fig. 14 - Switching Time Waveforms Fig. 17 - Basic Gate Charge Waveform L Vary tp to obtain required IAS Current regulator Same type as D.U.T. VDS 50 kΩ D.U.T RG + - IAS 12 V 0.2 µF 0.3 µF V DD + D.U.T. 10 V tp 0.01 Ω - VDS VGS 3 mA Fig. 15 - Unclamped Inductive Test Circuit IG ID Current sampling resistors Fig. 18 - Gate Charge Test Circuit S22-0948-Rev. D, 21-Nov-2022 Document Number: 91617 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHP12N50E www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 19 - For N-Channel           Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91617. S22-0948-Rev. D, 21-Nov-2022 Document Number: 91617 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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