SiHP18N50C
www.vishay.com
Vishay Siliconix
Power MOSFET
FEATURES
D
• Low figure-of-merit Ron x Qg
TO-220AB
Available
• 100 % avalanche tested
• High peak current capability
G
Available
• dv/dt ruggedness
• Improved trr/Qrr
G
D
S
• Improved gate charge
S
• High power dissipations capability
N-Channel MOSFET
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
Note
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details
PRODUCT SUMMARY
VDS (V) at TJ max.
RDS(on) ()
560
VGS = 10 V
0.225
Qg max. (nC)
76
Qgs (nC)
21
Qgd (nC)
29
Configuration
Single
ORDERING INFORMATION
Package
TO-220AB
Lead (Pb)-free and halogen-free
SiHP18N50C-E3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-source voltage
VDS
500
Gate-source voltage
VGS
± 30
Continuous drain current (TJ = 150 °C) a
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed drain current b
UNIT
V
18
ID
11
A
IDM
72
1.8
W/°C
Single pulse avalanche energy c
EAS
361
mJ
Maximum power dissipation
PD
223
W
dv/dt
5
V/ns
TJ, Tstg
-55 to +150
Linear derating factor
Reverse diode dv/dt d
Operating junction and storage temperature range
Soldering recommendations (peak temperature) d
For 10 s
300
°C
Notes
a. Drain current limited by maximum junction temperature
b. Repetitive rating; pulse width limited by maximum junction temperature
c. VDD = 50 V, starting TJ = 25 °C, L = 2.5 mH, Rg = 25 , IAS = 17 A
d. ISD 18 A, di/dt 380 A/μs, VDD VDS, TJ 150 °C
e. 1.6 mm from case
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum junction-to-ambient
RthJA
-
62
Maximum junction-to-case (drain)
RthJC
-
0.56
S17-1726-Rev. E, 20-Nov-17
UNIT
°C/W
Document Number: 91374
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SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
VDS temperature coefficient
Gate-source threshold voltage (N)
VDS
VGS = 0 V, ID = 250 μA
500
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.6
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
3.0
-
5.0
V
Gate-source leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero gate voltage drain current
IDSS
VDS = 500 V, VGS = 0 V
-
-
25
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
250
μA
-
0.225
0.270
gfs
VDS = 50 V, ID = 10 A
-
6.4
-
S
Input capacitance
Ciss
2451
2942
Coss
-
300
360
Reverse transfer capacitance
Crss
VGS = 0 V,
VDS = 25 V,
f = 1 MHz
-
Output capacitance
-
26
32
Drain-source on-state resistance
Forward transconductance a
RDS(on)
VGS = 10 V
ID = 10 A
Dynamic
Total gate charge
Qg
Gate-source charge
Qgs
Gate-drain charge
Turn-on delay time
Rise time
Turn-off delay time
pF
-
65
76
-
21
-
Qgd
-
29
-
td(on)
-
80
-
VDD = 250 V, ID = 18 A,
VGS = 10 V, Rg = 7.5
-
27
-
-
32
-
-
44
-
f = 1 MHz, open drain
-
1.1
-
-
-
18
S
-
-
72
TJ = 25 °C, IS = 18 A, VGS = 0 V
-
-
1.5
V
-
503
-
ns
-
6.7
-
μC
-
30
-
A
tr
td(off)
Fall time
tf
Gate input resistance
Rg
VGS = 10 V
ID = 18 A, VDS = 400 V
nC
ns
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
IS
Pulsed diode forward current
ISM
Diode forward voltage
VSD
Reverse recovery time
trr
Reverse recovery charge
Qrr
Reverse recovery current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IF = IS,
di/dt = 100 A/μs, VR = 35 V
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature
The information shown here is a preliminary product proposal, not a commercial product datasheet. Vishay Siliconix is not committed to produce this or any similar
product. This information should not be used for design purposes, nor construed as an offer to furnish or sell such products.
S17-1726-Rev. E, 20-Nov-17
Document Number: 91374
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SiHP18N50C
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Vishay Siliconix
70
VGS
Top
15 V
14 V
13 V
12 V
11 V
10 V
9.0 V
8.0 V
7.0 V
6.0 V
Bottom 5.0 V
ID, Drain Current (A)
60
50
40
30
TJ = 25 °C
20
7.0 V
10
0
0
6
12
18
24
RDS(on), Drain-to-Source On Resistance
(Normalized)
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
30
3
ID = 17 A
2.5
2
1.5
VGS = 10 V
1
0.5
0
- 60 - 40 - 20
Fig. 1 - Typical Output Characteristics, TC = 150 °C
Fig. 4 - Normalized On-Resistance vs. Temperature
40
105
VGS
15 V
14 V
13 V
12 V
30
11 V
10 V
9.0 V
8.0 V
7.0 V
20
6.0 V
Bottom 5.0 V
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds shorted
Crss = Cgd
Coss = Cds + Cgd
Capacitance (pF)
TJ = 150 °C
Top
ID, Drain Current (A)
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
VDS, Drain-to-Source Voltage (V)
7.0 V
10
0
104
Ciss
103
102
Coss
Crss
10
0
6
12
18
24
30
1
VDS, Drain-to-Source Voltage (V)
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
100
VGS, Gate-to-Source Voltage (V)
20
TJ = 150 °C
ID, Drain Current (A)
0
10
TJ = 25 °C
1
0.1
ID = 17 A
VDS = 400 V
VDS = 250 V
VDS = 100 V
16
12
8
4
0
0.01
5
6
7
8
9
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S17-1726-Rev. E, 20-Nov-17
10
0
30
60
90
120
QG, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Document Number: 91374
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SiHP18N50C
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103
Operation in this area limited
by RDS(on)
TJ = 150 °C
10
102
ID, Drain Current (A)
ISD, Reverse Drain Current (A)
100
TJ = 25 °C
1
10
1 ms
1
VGS = 0 V
0.1
0.2
0.5
0.8
1.1
100 µs
TC = 25 °C
TJ = 150 °C
Single pulse
10 ms
0.1
1.4
102
10
VSD, Source-to-Drain Voltage (V)
103
104
VDS, Drain-to-Source Voltage (V)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
ID, Drain Current (A)
20
15
10
5
0
25
50
75
100
125
150
TC, Case Temperature (°C)
Fig. 9 - Maximum Drain Current vs. Case Temperature
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
10-4
Single Pulse
10-3
10-2
0.1
1
Pulse Time (s)
Fig. 10 - Normalized Thermal Transient Impedance, Junction-to-Case
S17-1726-Rev. E, 20-Nov-17
Document Number: 91374
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SiHP18N50C
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RD
VDS
VGS
QG
10 V
D.U.T.
RG
+
- VDD
QGS
10 V
QGD
VG
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Charge
Fig. 11 - Switching Time Test Circuit
Fig. 15 - Basic Gate Charge Waveform
VDS
Current regulator
Same type as D.U.T.
90 %
50 kΩ
12 V
0.2 µF
0.3 µF
10 %
VGS
+
td(on)
D.U.T.
td(off) tf
tr
-
VDS
VGS
Fig. 12 - Switching Time Waveforms
3 mA
IG
ID
Current sampling resistors
L
Vary tp to obtain
required IAS
VDS
Fig. 16 - Gate Charge Test Circuit
D.U.T
RG
+
-
IAS
V DD
10 V
0.01 Ω
tp
Fig. 13 - Unclamped Inductive Test Circuit
VDS
tp
VDD
VDS
IAS
Fig. 14 - Unclamped Inductive Waveforms
S17-1726-Rev. E, 20-Nov-17
Document Number: 91374
5
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHP18N50C
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Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 17 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91374.
S17-1726-Rev. E, 20-Nov-17
Document Number: 91374
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Package Information
www.vishay.com
Vishay Siliconix
TO-220-1
A
E
F
D
H(1)
Q
ØP
3
2
L(1)
1
M*
L
b(1)
C
b
e
J(1)
e(1)
MILLIMETERS
DIM.
INCHES
MIN.
MAX.
MIN.
MAX.
A
4.24
4.65
0.167
0.183
b
0.69
1.02
0.027
0.040
b(1)
1.14
1.78
0.045
0.070
c
0.36
0.61
0.014
0.024
D
14.33
15.85
0.564
0.624
E
9.96
10.52
0.392
0.414
e
2.41
2.67
0.095
0.105
e(1)
4.88
5.28
0.192
0.208
F
1.14
1.40
0.045
0.055
H(1)
6.10
6.71
0.240
0.264
J(1)
2.41
2.92
0.095
0.115
L
13.36
14.40
0.526
0.567
L(1)
3.33
4.04
0.131
0.159
ØP
3.53
3.94
0.139
0.155
Q
2.54
3.00
0.100
0.118
ECN: E21-0621-Rev. D, 04-Nov-2021
DWG: 6031
Note
• M* = 0.052 inches to 0.064 inches (dimension including protrusion), heatsink hole for HVM
Document Number: 66542
1
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Revison: 04-Nov-2021
Package Information
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Vishay Siliconix
TO-220 FULLPAK (High Voltage)
OPTION 1: FACILITY CODE = 9
A
F
G
Q1
E
D
ØR
A3
L1
3 x b2
3 x b1
Mold flash
bleeding
Q
L
Exposed Cu
3xb
2xe
C
Bottom view
MILLIMETERS
DIM.
MIN.
NOM.
A
4.60
4.70
4.80
b
0.70
0.80
0.91
b1
1.20
1.30
1.47
b2
1.10
1.20
1.30
C
0.45
0.50
0.63
D
15.80
15.87
15.97
e
MAX.
2.54 BSC
E
10.00
10.10
F
2.44
2.54
10.30
2.64
G
6.50
6.70
6.90
L
12.90
13.10
13.30
L1
3.13
3.23
3.33
Q
2.65
2.75
2.85
Q1
3.20
3.30
3.40
ØR
3.08
3.18
3.28
Notes
1. To be used only for process drawing
2. These dimensions apply to all TO-220 FULLPAK leadframe versions 3 leads
3. All critical dimensions should C meet Cpk > 1.33
4. All dimensions include burrs and plating thickness
5. No chipping or package damage
6. Facility code will be the 1st character located at the 2nd row of the unit marking
Revision: 08-Apr-2019
Document Number: 91359
1
For technical questions, contact: hvmos.techsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
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Vishay Siliconix
OPTION 2: FACILITY CODE = Y
A
A1
E
ØP
n
d1
d3
D
u
L1
V
L
b3
A2
b2
c
b
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
A
4.570
4.830
0.180
0.190
A1
2.570
2.830
0.101
0.111
A2
2.510
2.850
0.099
0.112
b
0.622
0.890
0.024
0.035
b2
1.229
1.400
0.048
0.055
b3
1.229
1.400
0.048
0.055
c
0.440
0.629
0.017
0.025
D
8.650
9.800
0.341
0.386
d1
15.88
16.120
0.622
0.635
d3
12.300
12.920
0.484
0.509
E
10.360
10.630
0.408
e
2.54 BSC
0.419
0.100 BSC
L
13.200
13.730
0.520
0.541
L1
3.100
3.500
0.122
0.138
n
6.050
6.150
0.238
0.242
ØP
3.050
3.450
0.120
0.136
u
2.400
2.500
0.094
0.098
V
0.400
0.500
0.016
0.020
ECN: E19-0180-Rev. D, 08-Apr-2019
DWG: 5972
Notes
1. To be used only for process drawing
2. These dimensions apply to all TO-220 FULLPAK leadframe versions 3 leads
3. All critical dimensions should C meet Cpk > 1.33
4. All dimensions include burrs and plating thickness
5. No chipping or package damage
6. Facility code will be the 1st character located at the 2nd row of the unit marking
Revision: 08-Apr-2019
Document Number: 91359
2
For technical questions, contact: hvmos.techsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Disclaimer
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