SiHP25N60EFL
www.vishay.com
Vishay Siliconix
E Series Power MOSFET With
Fast Body Diode and Low Gate Charge
FEATURES
D
• Reduced figure-of-merit (FOM): Ron x Qg
TO-220AB
• Fast body diode MOSFET using E series
technology
• Reduced trr, Qrr, and IRRM
• Increased robustness due to low Qrr
Available
• Low input capacitance (Ciss)
• Reduced switching and conduction losses
• Avalanche energy rated (UIS)
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
G
G
D
S
S
N-Channel MOSFET
APPLICATIONS
PRODUCT SUMMARY
VDS (V) at TJ max.
• Telecommunications
- Server and telecom power supplies
• Computing
- ATX power supplies
• Industrial
- Welding
- Induction heating
- Battery chargers
- Uninterruptible power supplies (UPS)
• Renewable energy
- String PV inverters
650
RDS(on) typ. () at 25 °C
VGS = 10 V
Qg (Max.) (nC)
0.127
75
Qgs (nC)
17
Qgd (nC)
19
Configuration
Single
ORDERING INFORMATION
Package
TO-220AB
SiHP25N60EFL-BE3 a
Lead (Pb)-free and halogen-free
SiHP25N60EFL-GE3
Note
a. “-BE3” denotes alternate manufacturing location
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-source voltage
VDS
600
Gate-source voltage
VGS
± 30
Continuous drain current (TJ = 150 °C)
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed drain current a
ID
IDM
Linear derating factor
Single pulse avalanche
energy b
Maximum power dissipation
Operating junction and storage temperature range
Drain-source voltage slope
TJ = 125 °C
Reverse diode dV/dt d
Soldering recommendations (peak temperature) c
For 10 s
UNIT
V
25
16
A
61
2
W/°C
EAS
353
mJ
PD
250
W
TJ, Tstg
-55 to +150
°C
dV/dt
70
15
300
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature
b. VDD = 140 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 , IAS = 5 A
c. 1.6 mm from case
S22-0949-Rev. C, 21-Nov-2022
Document Number: 91811
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHP25N60EFL
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Vishay Siliconix
d. ISD ID, dI/dt = 100 A/μs, starting TJ = 25 °C
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum junction-to-ambient
RthJA
-
62
Maximum junction-to-case (drain)
RthJC
-
0.5
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
VDS temperature coefficient
Gate-source threshold Voltage (N)
VDS
VGS = 0 V, ID = 250 μA
600
-
-
V
VDS/TJ
Reference to 25 °C, ID = 10 mA
-
0.69
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
3.0
-
5.0
V
VGS = ± 20 V
-
-
± 100
nA
VGS = ± 30 V
-
-
±1
μA
VDS = 480 V, VGS = 0 V
-
-
1
VDS = 480 V, VGS = 0 V, TJ = 125 °C
-
-
500
Gate-source leakage
IGSS
Zero gate voltage drain current
IDSS
Drain-source on-state resistance
Forward transconductance
μA
-
0.127
0.146
gfs
VDS = 30 V, ID = 12.5 A
-
11.3
-
S
VGS = 0 V,
VDS = 100 V,
f = 1 MHz
-
2274
-
-
137
-
-
4
-
-
79
-
-
330
-
-
50
75
-
17
-
RDS(on)
VGS = 10 V
ID = 12.5 A
Dynamic
Input capacitance
Ciss
Output capacitance
Coss
Reverse transfer capacitance
Crss
Effective output capacitance, energy
related a
Co(er)
Effective output capacitance, time
related b
Co(tr)
pF
VDS = 0 V to 480 V, VGS = 0 V
Total gate charge
Qg
Gate-source charge
Qgs
VGS = 10 V
ID = 12.5 A, VDS = 480 V
Gate-drain charge
Qgd
-
19
-
Turn-on delay time
td(on)
-
25
50
Rise time
Turn-off delay time
tr
td(off)
Fall time
tf
Gate input resistance
Rg
VDD = 480 V, ID = 12.5 A,
Rg = 9.1 , VGS = 10 V
-
39
68
-
47
94
-
21
42
f = 1 MHz, open drain
0.4
0.7
1.4
-
-
25
-
-
61
nC
ns
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
IS
Pulsed diode forward current
ISM
Diode forward voltage
VSD
Reverse recovery time
trr
Reverse recovery charge
Qrr
Reverse recovery current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 12.5 A, VGS = 0 V
TJ = 25 °C, IF = IS =12.5 A,
dI/dt = 100 A/μs, VR = 25 V
-
0.9
1.2
V
-
138
276
ns
-
0.8
1.6
μC
-
11
-
A
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS
S22-0949-Rev. C, 21-Nov-2022
Document Number: 91811
2
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHP25N60EFL
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
3.0
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
40
ID = 12.5 A
RDS(on), Drain-to-Source On-Resistance
(Normalized)
ID, Drain-to-Source Current (A)
60
TJ = 25 °C
20
2.5
2.0
1.5
1.0
VGS = 10 V
0.5
0
0
0
5
10
15
VDS, Drain-to-Source Voltage (V)
-60 -40 -20
20
0 20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 1 - Typical Output Characteristics
100 000
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
30
24
TJ = 150 °C
10 000
Ciss
C, Capacitance (pF)
ID, Drain-to-Source Current (A)
36
18
12
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds shorted
Crss = Cgd
Coss = Cds + Cgd
1000
Coss
100
10
Crss
6
1
0
0
5
10
15
VDS, Drain-to-Source Voltage (V)
0
20
100
200
300
400
500
600
VDS, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 2 - Typical Output Characteristics
18
14
TJ = 25 °C
40
TJ = 150 °C
10
Coss
Eoss
8
500
Eoss (μJ)
12
Coss (pF)
ID, Drain-to-Source Current (A)
16
5000
60
6
20
4
2
VDS = 27.8 V
50
0
0
5
10
15
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S22-0949-Rev. C, 21-Nov-2022
20
0
0
100
200
300
VDS
400
500
600
Fig. 6 - COSS and EOSS vs. VDS
Document Number: 91811
3
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHP25N60EFL
www.vishay.com
Vishay Siliconix
25
VDS = 480 V
VDS = 300 V
VDS = 120 V
20
20
ID, Drain Current (A)
VGS, Gate-to-Source Voltage (V)
24
16
12
8
15
10
5
4
0
0
0
20
40
60
80
Qg, Total Gate Charge (nC)
100
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
25
50
75
100
125
TC, Case Temperature (°C)
150
Fig. 10 - Maximum Drain Current vs. Case Temperature
VDS, Drain-to-Source Breakdown Voltage (V)
775
ISD, Reverse Drain Current (A)
100
TJ = 150 °C
10
TJ = 25 °C
1
VGS = 0 V
0.1
0.2
0.4
0.6
0.8
1.0
VSD, Source-Drain Voltage (V)
1.2
1.4
Fig. 8 - Typical Source-Drain Diode Forward Voltage
Operation in this area
limited by RDS(on)
ID, Drain Current (A)
100
750
725
700
675
650
625
600
ID = 10 mA
575
-60 -40 -20
0 20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 11 - Typical Drain-to-Source Voltage vs. Temperature
IDM limited
10
100 μs
Limited by RDS(on)*
1
1 ms
0.1
10 ms
TC = 25 °C
TJ = 150 °C
Single pulse
BVDSS limited
0.01
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Fig. 9 - Maximum Safe Operating Area
S22-0949-Rev. C, 21-Nov-2022
Document Number: 91811
4
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHP25N60EFL
www.vishay.com
Vishay Siliconix
1
Normalized Effective Transient
Thermal Impedance
Duty cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single pulse
0.01
0.0001
0.001
0.01
0.1
1
Pulse Time (s)
Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case
RD
VDS
VDS
tp
VGS
VDD
D.U.T.
RG
+
- VDD
VDS
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
IAS
Fig. 13 - Switching Time Test Circuit
Fig. 16 - Unclamped Inductive Waveforms
VDS
QG
10 V
90 %
QGS
10 %
VGS
QGD
VG
td(on)
td(off) tf
tr
Charge
Fig. 14 - Switching Time Waveforms
Fig. 17 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
L
Vary tp to obtain
required IAS
VDS
50 kΩ
12 V
0.2 µF
0.3 µF
D.U.T
RG
+
-
IAS
+
V DD
D.U.T.
-
VDS
VGS
10 V
tp
0.01 Ω
3 mA
IG
ID
Current sampling resistors
Fig. 15 - Unclamped Inductive Test Circuit
S22-0949-Rev. C, 21-Nov-2022
Fig. 18 - Gate Charge Test Circuit
Document Number: 91811
5
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHP25N60EFL
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 19 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91811.
S22-0949-Rev. C, 21-Nov-2022
Document Number: 91811
6
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Revision: 01-Jan-2023
1
Document Number: 91000