SIHP4N80E-BE3

SiHP4N80E www.vishay.com Vishay Siliconix E Series Power MOSFET FEATURES D • Low figure-of-merit (FOM) Ron x Qg TO-220AB • Low input capacitance (Ciss) • Reduced switching and conduction losses • Ultra low gate charge (Qg) Available • Avalanche energy rated (UIS) • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 G G D S S N-Channel MOSFET APPLICATIONS • • • • Server and telecom power supplies Switch mode power supplies (SMPS) Power factor correction power supplies (PFC) Lighting - High-intensity discharge (HID) - Fluorescent ballast lighting • Industrial - Welding - Induction heating - Motor drives - Battery chargers - Renewable energy - Solar (PV inverters) PRODUCT SUMMARY VDS (V) at TJ max. RDS(on) typ. () at 25 °C 850 VGS = 10 V Qg max. (nC) 1.1 32 Qgs (nC) 4 Qgd (nC) 6 Configuration Single ORDERING INFORMATION Package TO-220AB SiHP4N80E-BE3 a Lead (Pb)-free and halogen-free SiHP4N80E-GE3 Note a. “-BE3” denotes alternate manufacturing location ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER Drain-source voltage Gate-source voltage Continuous drain current (TJ = 150 °C) Pulsed drain current a Linear derating factor Single pulse avalanche energy b Maximum power dissipation Operating junction and storage temperature range Drain-source voltage slope Reverse diode dv/dt d Soldering recommendations (peak temperature) c VGS at 10 V TC = 25 °C TC = 100 °C SYMBOL LIMIT VDS VGS 800 ± 30 4.3 2.7 11 0.56 56 69 -55 to +150 70 0.3 300 ID IDM EAS PD TJ, Tstg TJ = 125 °C For 10 s dv/dt UNIT V A W/°C mJ W °C V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature b. VDD = 140 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 , IAS = 2.0 A c. 1.6 mm from case d. ISD  ID, di/dt = 100 A/μs, starting TJ = 25 °C S22-0949-Rev. C, 21-Nov-2022 Document Number: 92017 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHP4N80E www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum junction-to-ambient RthJA - 62 Maximum junction-to-case (drain) RthJC - 1.8 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-source breakdown voltage VDS temperature coefficient Gate-source threshold Voltage (N) Gate-source leakage Zero gate voltage drain current VDS VGS = 0 V, ID = 250 μA 800 - - V VDS/TJ Reference to 25 °C, ID = 1 mA - 1.1 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V VGS = ± 20 V - - ± 100 nA VGS = ± 30 V - - ±1 μA VDS = 800 V, VGS = 0 V - - 1 VDS = 640 V, VGS = 0 V, TJ = 125 °C - - 10 IGSS IDSS μA - 1.1 1.27  gfs VDS = 30 V, ID = 2 A - 1.5 - S Input capacitance Ciss VGS = 0 V, VDS = 100 V, f = 1 MHz - 622 - - 34 - - 5 - - 21 - - 91 - Drain-source on-state resistance Forward transconductance RDS(on) VGS = 10 V ID = 2 A Dynamic Output capacitance Coss Reverse transfer capacitance Crss Effective output capacitance, energy related a Co(er) Effective output capacitance, time  related b Co(tr) pF VDS = 0 V to 480 V, VGS = 0 V Total gate charge Qg Gate-source charge Qgs Gate-drain charge Qgd Turn-on delay time Rise time Turn-off delay time - 16 32 - 4 - - 6 - td(on) - 12 24 tr - 7 14 - 26 52 td(off) Fall time tf Gate input resistance Rg VGS = 10 V ID = 2 A, VDS = 480 V VDD = 480 V, ID = 2 A, VGS = 10 V, Rg = 9.1  f = 1 MHz, open drain - 20 40 0.6 1.2 2.4 - - 4.4 nC ns  Drain-Source Body Diode Characteristics Continuous source-drain diode current IS Pulsed diode forward current ISM Diode forward voltage VSD Reverse recovery time trr Reverse recovery charge Qrr Reverse recovery current IRRM MOSFET symbol showing the  integral reverse p - n junction diode D A G TJ = 25 °C, IS = 2 A, VGS = 0 V TJ = 25 °C, IF = IS = 2 A, di/dt = 100 A/μs, VR = 25 V S - - 11 - - 1.2 - 248 496 ns - 1.4 2.8 μC - 9.2 - A V Notes a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 V to 480 V VDSS b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 V to 480 V VDSS S22-0949-Rev. C, 21-Nov-2022 Document Number: 92017 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHP4N80E www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 3.0 12 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V 9 TJ = 25 °C ID = 2 A RDS(on), Drain-to-Source On-Resistance (Normalized) 6 3 0 2.0 1.5 1.0 VGS = 10 V 0.5 0 0 5 10 15 VDS, Drain-to-Source Voltage (V) -60 -40 -20 20 6 TOP 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V 10 000 TJ = 150 °C 1000 C, Capacitance (pF) 4 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 4 - Normalized On-Resistance vs. Temperature Fig. 1 - Typical Output Characteristics ID, Drain-to-Source Current (A) 2.5 2 Ciss 100 Coss 10 0 VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds shorted Crss = Cgd Coss = Cds + Cgd Crss 1 0 5 10 15 VDS, Drain-to-Source Voltage (V) 20 0 100 200 300 400 500 VDS, Drain-to-Source Voltage (V) 600 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 2 - Typical Output Characteristics 10 000 12 4.5 4.0 Coss, Output Capacitance (pF) ID, Drain-to-Source Current (A) TJ = 25 °C 9 TJ = 150 °C 6 3 3.5 1000 3.0 2.5 Eoss Coss 2.0 100 1.5 1.0 0.5 VDS = 31.2 V 10 0 0 5 10 15 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S22-0949-Rev. C, 21-Nov-2022 20 Eoss, Output Capacitance Stored Energy (μJ) ID, Drain-to-Source Current (A) TOP 0 0 100 200 300 400 500 VDS, Drain-to-Source Voltage (V) 600 Fig. 6 - Coss and Eoss vs. VDS Document Number: 92017 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHP4N80E www.vishay.com Vishay Siliconix 5 VDS = 480 V VDS = 300 V VDS = 120 V 4 9 ID, Drain Current (A) VGS, Gate-to-Source Voltage (V) 12 6 2 3 1 0 0 0 5 10 15 Qg, Total Gate Charge (nC) 20 Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage 25 50 75 100 125 TC, Case Temperature (°C) 150 Fig. 10 - Maximum Drain Current vs. Case Temperature 100 1050 VDS, Drain-to-Source Breakdown Voltage (V) ISD, Reverse Drain Current (A) 3 10 TJ = 150 °C 1 TJ = 25 °C VGS = 0 V 0.1 0.0 0.3 0.6 0.9 1.2 VSD, Source-Drain Voltage (V) 1.5 Fig. 8 - Typical Source-Drain Diode Forward Voltage 1025 1000 975 950 925 900 875 850 825 800 ID = 250 μA 775 -60 -40 -20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 11 - Temperature vs. Drain-to-Source Voltage 100 Operation in this area limited by RDS(on) ID, Drain Current (A) 10 IDM limited 100 μs 1 Limited by RDS(on)* 0.1 1 ms TC = 25 °C TJ = 150 °C single pulse 10 ms BVDSS limited 0.01 1 10 100 1000 VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Fig. 9 - Maximum Safe Operating Area S22-0949-Rev. C, 21-Nov-2022 Document Number: 92017 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHP4N80E www.vishay.com Vishay Siliconix 1 Normalized Effective Transient Thermal Impedance Duty cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single pulse 0.01 0.0001 0.001 0.01 Pulse Time (s) 0.1 1 Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case RD VDS VDS tp VGS D.U.T. VDD Rg + - VDD VDS 10 V Pulse width ≤ 1 μs Duty factor ≤ 0.1 % IAS Fig. 13 - Switching Time Test Circuit Fig. 16 - Unclamped Inductive Waveforms VDS Qg 10 V 90 % Qgs 10 % VGS Qgd VG td(on) td(off) tr tf Charge Fig. 14 - Switching Time Waveforms Fig. 17 - Basic Gate Charge Waveform Current regulator Same type as D.U.T. L VDS Vary tp to obtain required IAS 50 kΩ D.U.T. Rg 12 V 0.2 μF 0.3 μF + - VDD + D.U.T. IAS - VDS 10 V tp 0.01 Ω VGS 3 mA Fig. 15 - Unclamped Inductive Test Circuit IG ID Current sampling resistors Fig. 18 - Gate Charge Test Circuit S22-0949-Rev. C, 21-Nov-2022 Document Number: 92017 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHP4N80E www.vishay.com Vishay Siliconix Peak Diode Recovery dv/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer 3 + 2 - - 4 + 1 Rg • • • • 1 Driver gate drive Period P.W. + V - DD dv/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test D= P.W. Period V GS = 10 V a 2 D.U.T. ISD waveform Reverse recovery current 3 D.U.T. VDS Body diode forward current di/dt waveform Diode recovery dv/dt Re-applied voltage V DD Body diode forward drop 4 Inductor current Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 19 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see www.vishay.com/ppg?92017. S22-0949-Rev. C, 21-Nov-2022 Document Number: 92017 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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