SiHS36N50D
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Vishay Siliconix
D Series Power MOSFET
FEATURES
• Optimal design
- Low area specific on-resistance
- Low input capacitance (Ciss)
- Reduced capacitive switching losses
- High body diode ruggedness
- Avalanche energy rated (UIS)
• Optimal efficiency and operation
- Low cost
- Simple gate drive circuitry
- Low figure-of-merit (FOM): Ron x Qg
- Fast switching
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
D
Super-247
S
G
D
G
S
N-Channel MOSFET
PRODUCT SUMMARY
VDS (V) at TJ max.
RDS(on) max. at 25 °C (Ω)
APPLICATIONS
550
VGS = 10 V
Qg max. (nC)
0.130
Qgs (nC)
23
Qgd (nC)
37
Configuration
• Consumer electronics
- Displays (LCD or Plasma TV
• Server and telecom power supplies
- SMPS
• Industrial
- Welding, induction heating, motor drives
• Battery chargers
125
Single
ORDERING INFORMATION
Package
Super-247
Lead (Pb)-free and halogen-free
SiHS36N50D-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
Drain-source voltage
Gate-source voltage
LIMIT
VDS
500
VGS
Gate-source voltage AC (f > 1 Hz)
Continuous drain current (TJ = 150 °C)
SYMBOL
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed drain current a
ID
Maximum power dissipation
Operating junction and storage temperature range
Drain-source voltage slope
TJ = 125 °C
Reverse diode dV/dt d
Soldering recommendations (peak temperature)
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature
b. VDD = 50 V, starting TJ = 25 °C, L = 2.3 mH, Rg = 25 Ω, IAS = 17 A
c. 1.6 mm from case
d. ISD ≤ ID, starting TJ = 25 °C
S21-0019-Rev. B, 18-Jan-2021
V
30
36
23
A
IDM
112
3.6
W/°C
EAS
332
mJ
Linear derating factor
Single pulse avalanche energy b
± 30
UNIT
PD
446
W
TJ, Tstg
- 55 to + 150
°C
dV/dt
24
0.1
300 c
V/ns
°C
Document Number: 91514
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THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum junction-to-ambient
RthJA
-
40
Maximum junction-to-case (drain)
RthJC
-
0.28
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
VDS temperature coefficient
Gate threshold voltage (N)
Gate-source leakage
Zero gate voltage drain current
VDS
VGS = 0 V, ID = 250 μA
500
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 250 μA
-
0.52
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
3.0
-
5.0
V
nA
VGS = ± 30 V
-
-
± 100
VDS = 500 V, VGS = 0 V
-
-
1
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
10
IGSS
IDSS
μA
-
0.105
0.130
Ω
gfs
VDS = 50 V, ID = 18 A
-
12.8
-
S
Input capacitance
Ciss
3233
-
Coss
-
285
-
Reverse transfer capacitance
Crss
VGS = 0 V,
VDS = 100 V,
f = 1 MHz
-
Output capacitance
-
25
-
Effective output capacitance, energy
related a
Co(er)
-
240
-
Effective output capacitance, time
related b
Co(tr)
-
352
-
Qg
-
83
125
-
23
-
-
37
-
Drain-source on-state resistance
Forward transconductance a
RDS(on)
VGS = 10 V
ID = 18 A
Dynamic
Total gate charge
pF
VGS = 0 V, VDS = 0 V to 400 V
VGS = 10 V
Gate-source charge
Qgs
Gate-drain charge
Qgd
Turn-on delay time
td(on)
-
33
66
tr
VDD = 400 V, ID = 18 A,
VGS = 10 V, Rg = 9.1 Ω
-
89
134
-
79
119
-
68
102
f = 1 MHz, open drain
-
1.8
-
-
-
36
-
-
144
-
-
1.2
-
490
-
ns
-
8.2
-
μC
-
31
-
A
Rise time
Turn-off delay time
td(off)
Fall time
tf
Gate input resistance
Rg
ID = 18 A, VDS = 400 V
nC
ns
Ω
Drain-source body diode characteristics
Continuous source-drain diode current
IS
Pulsed diode forward current
ISM
Diode forward voltage
VSD
Reverse recovery time
trr
Reverse recovery charge
Qrr
Reverse recovery current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 18 A, VGS = 0 V
TJ = 25 °C, IF = IS = 18 A,
dI/dt = 100 A/μs, VR = 20 V
V
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS
S21-0019-Rev. B, 18-Jan-2021
Document Number: 91514
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SiHS36N50D
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
90
3
TJ = 25 °C
ID = 18 A
RDS(on), Drain-to-Source
On Resistance (Normalized)
ID, Drain-to-Source Current (A)
120
60
30
2.5
2
1.5
1
0.5
0
0
5
10
15
20
25
0
- 60 - 40 - 20 0
30
TJ, Junction Temperature (°C)
Fig. 1 - Typical Output Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
10 000
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
Ciss
Capacitance (pF)
60
TJ = 150 °C
40
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
1000
Coss
100
Crss
10
20
1
0
0
5
10
15
20
25
0
30
VDS, Drain-to-Source Voltage (V)
100
200
400
500
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
120
VGS, Gate-to-Source Voltage (V)
24
TJ = 25 °C
90
60
300
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
ID, Drain-to-Source Current (A)
20 40 60 80 100 120 140 160
VDS, Drain-to-Source Voltage (V)
80
ID, Drain-to-Source Current (A)
VGS = 10 V
TJ = 150 °C
30
VDSS = 400 V
VDS = 250 V
VDSS = 100 V
20
16
12
8
4
0
0
0
5
10
15
20
25
0
30
60
90
120
150
VGS, Gate-to-Source Voltage (V)
Qg, Total Gate Charge (nC)
Fig. 3 - Typical Transfer Characteristics
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
S21-0019-Rev. B, 18-Jan-2021
Document Number: 91514
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SiHS36N50D
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40
ID, Drain Current (A)
ISD, Reverse Drain Current (A)
1000 ġ
100
ġ
TJ = 150 °C
ġ
10
TJ = 25 °Cġġ
ġ
1
30
20
10
VGS = 0 Vġ
ġ
0.1 ġ
0.2
0
0.4
0.6
0.8
1
1.2
1.4
1.6
25
VSD, Source-Drain Voltage (V)
75
100
125
150
TJ, Case Temperature (°C)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 9 - Maximum Drain Current vs. Case Temperature
1000
625
VDS, Drain-to-Source
Breakdown Voltage (V)
IDM = Limited
Operation in this Area
Limited by RDS(on)
100
ID, Drain Current (A)
50
Limited by RDS(on)*
10
100 μs
1 ms
1
TC = 25 °C
TJ = 150 °C
Single Pulse
10 ms
600
575
550
525
500
BVDSS Limited
0.1
475
1
10
100
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is s
1000
- 60 - 40 - 20 0
Fig. 8 - Maximum Safe Operating Area
Normalized Effective Transient
Thermal Impedance
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 10 - Temperature vs. Drain-to-Source Voltage
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
Single Pulse
0.02
0.01
0.0001
0.001
0.01
0.1
1
Pulse Time (s)
Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case
S21-0019-Rev. B, 18-Jan-2021
Document Number: 91514
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SiHS36N50D
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Vishay Siliconix
RD
V DS
QG
10 V
V GS
D.U.T.
RG
QGS
+
- V DD
QGD
VG
10 V
Pulse width ≤ 1 μs
Duty factor ≤ 0.1 %
Charge
Fig. 12 - Switching Time Test Circuit
Fig. 16 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
V DS
90 %
50 kΩ
12 V
0.2 μF
0.3 μF
+
10 %
V GS
D.U.T.
td(on)
td(off)
tr
tf
-
VDS
VGS
3 mA
Fig. 13 - Switching Time Waveforms
IG
ID
Current sampling resistors
Fig. 17 - Gate Charge Test Circuit
L
Vary t p to obtain
required IAS
VDS
D.U.T.
RG
+
-
I AS
V DD
10 V
0.01 Ω
tp
Fig. 14 - Unclamped Inductive Test Circuit
V DS
tp
V DD
V DS
IAS
Fig. 15 - Unclamped Inductive Waveforms
S21-0019-Rev. B, 18-Jan-2021
Document Number: 91514
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SiHS36N50D
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Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 18 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91514.
S21-0019-Rev. B, 18-Jan-2021
Document Number: 91514
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Package Information
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Vishay Siliconix
TO-274AA (High Voltage)
VERSION 1: FACILITY CODE = Y
B
A
E
E4
A
D2
E1
A1
R
D1
D
L1
L
Detail “A”
C
b
e
A2
0.10 (0.25) M B A M
10°
b4
b2
Lead Tip
5°
Detail “A”
Scale: 2:1
MILLIMETERS
INCHES
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
DIM.
MIN.
MAX.
MIN.
A
4.70
5.30
0.185
0.209
D1
15.50
16.10
0.610
0.634
A1
1.50
2.50
0.059
0.098
D2
0.70
1.30
0.028
0.051
A2
2.25
2.65
0.089
0.104
E
15.10
16.10
0.594
0.634
13.30
13.90
0.524
0.547
b
1.30
1.60
0.051
0.063
E1
b2
1.80
2.20
0.071
0.087
e
5.45 BSC
MAX.
0.215 BSC
b4
3.00
3.25
0.118
0.128
L
13.70
14.70
0.539
0.579
c (1)
0.38
0.89
0.015
0.035
L1
1.00
1.60
0.039
0.063
D
19.80
20.80
0.780
0.819
R
2.00
3.00
0.079
0.118
Notes
• Dimensioning and tolerancing per ASME Y14.5M-1994
• Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outer extremes of the plastic body
• Outline conforms to JEDEC® outline to TO-274AA
(1) Dimension measured at tip of lead
Revision: 19-Oct-2020
Document Number: 91365
1
For technical questions, contact: hvm@vishay.com
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Package Information
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Vishay Siliconix
VERSION 2: FACILITY CODE = N
A
E
A
E3
B
D
D1
D2
E2
Q
A2
L1
F
F
H
H
C
G
L
G
A1
e
b
3x
0.25 M B A M
b1
C
b3
E4
E1
b’, b2, b4
C
C’
Base metal
b, b1, b3
Plating
SECTION "F-F", "G-G" AND "H-H"
SCALE: NONE
MILLIMETERS
MILLIMETERS
DIM.
MIN.
MAX.
DIM.
MIN.
MAX.
A
4.83
5.21
D1
16.25
17.65
A1
2.29
2.54
D2
0.50
0.80
A2
1.91
2.16
E
15.75
16.13
b’
1.07
1.28
E1
13.10
14.15
b
1.07
1.33
E2
3.68
5.10
b1
1.91
2.41
E3
1.00
1.90
b2
1.91
2.16
E4
12.38
13.43
b3
2.87
3.38
e
b4
2.87
3.13
N
c’
0.55
0.65
L
19.81
c
0.55
0.68
L1
3.70
4.00
D
20.80
21.10
Q
5.49
6.00
5.44 BSC
3
20.32
ECN: E20-0538-Rev. C, 19-Oct-2020
DWG: 5975
Notes
• Dimensioning and tolerancing per ASME Y14.5M-1994
• Outline conforms to JEDEC® outline to TO-274AD
• Dimensions are measured in mm, angles are in degree
• Metal surfaces are tin plated, except area of cut
Revision: 19-Oct-2020
Document Number: 91365
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