SIHU4N80E-GE3

SiHU4N80E www.vishay.com Vishay Siliconix E Series Power MOSFET FEATURES D • Low figure-of-merit (FOM) Ron x Qg IPAK (TO-251) • Low input capacitance (Ciss) • Reduced switching and conduction losses D G • Ultra low gate charge (Qg) • Avalanche energy rated (UIS) G D S • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 S N-Channel MOSFET APPLICATIONS PRODUCT SUMMARY • Server and telecom power supplies VDS (V) at TJ max. RDS(on) typ. () at 25 °C • Switch mode power supplies (SMPS) 850 VGS = 10 V 1.1 Qg max. (nC) 32 Qgs (nC) 4 Qgd (nC) 6 Configuration • Power factor correction power supplies (PFC) • Lighting - High-intensity discharge (HID) - Fluorescent ballast lighting Single • Industrial - Welding - Induction heating - Motor drives - Battery chargers - Renewable energy - Solar (PV inverters) ORDERING INFORMATION Package IPAK (TO-251) Lead (Pb)-free and halogen-free SiHU4N80E-GE3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-source voltage VDS 800 Gate-source voltage VGS ± 30 Continuous drain current (TJ = 150 °C) VGS at 10 V TC = 25 °C TC = 100 °C Pulsed drain current a ID IDM Linear derating factor UNIT V 4.3 2.7 A 11 0.56 W/°C Single pulse avalanche energy b EAS 56 mJ Maximum power dissipation PD 69 W TJ, Tstg -55 to +150 °C Operating junction and storage temperature range Drain-source voltage slope TJ = 125 °C Reverse diode dv/dt d Soldering recommendations (peak temperature) c For 10 s dv/dt 70 0.3 300 V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature b. VDD = 140 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 , IAS = 2.0 A c. 1.6 mm from case d. ISD  ID, di/dt = 100 A/μs, starting TJ = 25 °C S17-1345-Rev. A, 04-Sep-17 Document Number: 92018 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHU4N80E www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum junction-to-ambient RthJA - 62 Maximum junction-to-case (drain) RthJC - 1.8 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-source breakdown voltage VDS temperature coefficient Gate-source threshold Voltage (N) Gate-source leakage Zero gate voltage drain current VDS VGS = 0 V, ID = 250 μA 800 - - V VDS/TJ Reference to 25 °C, ID = 1 mA - 1.1 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V VGS = ± 20 V - - ± 100 nA VGS = ± 30 V - - ±1 μA VDS = 800 V, VGS = 0 V - - 1 VDS = 640 V, VGS = 0 V, TJ = 125 °C - - 10 IGSS IDSS μA - 1.1 1.27  gfs VDS = 30 V, ID = 2 A - 1.5 - S Input capacitance Ciss VGS = 0 V, VDS = 100 V, f = 1 MHz - 622 - - 34 - - 5 - - 21 - - 91 - Drain-source on-state resistance Forward transconductance RDS(on) VGS = 10 V ID = 2 A Dynamic Output capacitance Coss Reverse transfer capacitance Crss Effective output capacitance, energy related a Co(er) Effective output capacitance, time  related b Co(tr) pF VDS = 0 V to 480 V, VGS = 0 V Total gate charge Qg Gate-source charge Qgs Gate-drain charge Qgd Turn-on delay time Rise time Turn-off delay time - 16 32 - 4 - - 6 - td(on) - 12 24 tr - 7 14 - 26 52 td(off) Fall time tf Gate input resistance Rg VGS = 10 V ID = 2 A, VDS = 480 V VDD = 480 V, ID = 2 A, VGS = 10 V, Rg = 9.1  f = 1 MHz, open drain - 20 40 0.6 1.2 2.4 - - 4.4 nC ns  Drain-Source Body Diode Characteristics Continuous source-drain diode current IS Pulsed diode forward current ISM Diode forward voltage VSD Reverse recovery time trr Reverse recovery charge Qrr Reverse recovery current IRRM MOSFET symbol showing the  integral reverse p - n junction diode D A G TJ = 25 °C, IS = 2 A, VGS = 0 V TJ = 25 °C, IF = IS = 2 A, di/dt = 100 A/μs, VR = 25 V S - - 11 - - 1.2 - 248 496 ns - 1.4 2.8 μC - 9.2 - A V Notes a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 V to 480 V VDSS b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 V to 480 V VDSS S17-1345-Rev. A, 04-Sep-17 Document Number: 92018 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHU4N80E www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 3.0 12 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V 9 TJ = 25 °C ID = 2 A RDS(on), Drain-to-Source On-Resistance (Normalized) 6 3 0 2.0 1.5 1.0 VGS = 10 V 0.5 0 0 5 10 15 VDS, Drain-to-Source Voltage (V) -60 -40 -20 20 6 TOP 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V 10 000 TJ = 150 °C 1000 C, Capacitance (pF) 4 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 4 - Normalized On-Resistance vs. Temperature Fig. 1 - Typical Output Characteristics ID, Drain-to-Source Current (A) 2.5 2 Ciss 100 Coss 10 0 VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds shorted Crss = Cgd Coss = Cds + Cgd Crss 1 0 5 10 15 VDS, Drain-to-Source Voltage (V) 20 0 100 200 300 400 500 VDS, Drain-to-Source Voltage (V) 600 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 2 - Typical Output Characteristics 10 000 12 4.5 4.0 Coss, Output Capacitance (pF) ID, Drain-to-Source Current (A) TJ = 25 °C 9 TJ = 150 °C 6 3 3.5 1000 3.0 2.5 Eoss Coss 2.0 100 1.5 1.0 0.5 VDS = 31.2 V 10 0 0 5 10 15 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S17-1345-Rev. A, 04-Sep-17 20 Eoss, Output Capacitance Stored Energy (μJ) ID, Drain-to-Source Current (A) TOP 0 0 100 200 300 400 500 VDS, Drain-to-Source Voltage (V) 600 Fig. 6 - Coss and Eoss vs. VDS Document Number: 92018 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHU4N80E www.vishay.com Vishay Siliconix 5 VDS = 480 V VDS = 300 V VDS = 120 V 4 9 ID, Drain Current (A) VGS, Gate-to-Source Voltage (V) 12 6 2 3 1 0 0 0 5 10 15 Qg, Total Gate Charge (nC) 20 Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage 25 50 75 100 125 TC, Case Temperature (°C) 150 Fig. 10 - Maximum Drain Current vs. Case Temperature 100 1050 VDS, Drain-to-Source Breakdown Voltage (V) ISD, Reverse Drain Current (A) 3 10 TJ = 150 °C 1 TJ = 25 °C VGS = 0 V 0.1 0.0 0.3 0.6 0.9 1.2 VSD, Source-Drain Voltage (V) 1.5 Fig. 8 - Typical Source-Drain Diode Forward Voltage 1025 1000 975 950 925 900 875 850 825 800 ID = 250 μA 775 -60 -40 -20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 11 - Temperature vs. Drain-to-Source Voltage 100 Operation in this area limited by RDS(on) ID, Drain Current (A) 10 IDM limited 100 μs 1 Limited by RDS(on)* 0.1 1 ms TC = 25 °C TJ = 150 °C single pulse 10 ms BVDSS limited 0.01 1 10 100 1000 VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Fig. 9 - Maximum Safe Operating Area S17-1345-Rev. A, 04-Sep-17 Document Number: 92018 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHU4N80E www.vishay.com Vishay Siliconix 1 Normalized Effective Transient Thermal Impedance Duty cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single pulse 0.01 0.0001 0.001 0.01 Pulse Time (s) 0.1 1 Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case RD VDS VDS tp VGS D.U.T. VDD Rg + - VDD VDS 10 V Pulse width ≤ 1 μs Duty factor ≤ 0.1 % IAS Fig. 13 - Switching Time Test Circuit Fig. 16 - Unclamped Inductive Waveforms VDS Qg 10 V 90 % Qgs 10 % VGS Qgd VG td(on) td(off) tr tf Charge Fig. 14 - Switching Time Waveforms Fig. 17 - Basic Gate Charge Waveform Current regulator Same type as D.U.T. L VDS Vary tp to obtain required IAS 50 kΩ D.U.T. Rg + - VDD 12 V 0.2 μF 0.3 μF + IAS D.U.T. - VDS 10 V tp 0.01 Ω VGS 3 mA Fig. 15 - Unclamped Inductive Test Circuit IG ID Current sampling resistors Fig. 18 - Gate Charge Test Circuit S17-1345-Rev. A, 04-Sep-17 Document Number: 92018 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHU4N80E www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer 3 + 2 - - 4 + 1 Rg • • • • 1 Driver gate drive Period P.W. + V - DD dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test D= P.W. Period V GS = 10 V a 2 D.U.T. ISD waveform Reverse recovery current 3 D.U.T. VDS Body diode forward current dI/dt waveform Diode recovery dV/dt Re-applied voltage V DD Body diode forward drop 4 Inductor current Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 19 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?92018. S17-1345-Rev. A, 04-Sep-17 Document Number: 92018 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix Case Outline for TO-251AA (High Voltage) OPTION 1: 4 E1 3 E Thermal PAD 4 b4 θ2 4 A 0.010 0.25 M C A B L2 4 c2 A θ1 B D D1 A C 3 Seating plane 5 C L1 L3 (Datum A) C L B B A A1 3 x b2 View A - A 2xe c 3xb 0.010 0.25 M C A B Plating 5 b1, b3 Base metal Lead tip 5 c1 (c) (b, b2) Section B - B and C - C MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. A 2.18 2.39 0.086 0.094 D1 5.21 - 0.205 - A1 0.89 1.14 0.035 0.045 E 6.35 6.73 0.250 0.265 b 0.64 0.89 0.025 0.035 E1 4.32 - 0.170 - 2.29 BSC MAX. b1 0.65 0.79 0.026 0.031 e b2 0.76 1.14 0.030 0.045 L 8.89 9.65 0.350 2.29 BSC 0.380 b3 0.76 1.04 0.030 0.041 L1 1.91 2.29 0.075 0.090 b4 4.95 5.46 0.195 0.215 L2 0.89 1.27 0.035 0.050 0.060 c 0.46 0.61 0.018 0.024 L3 1.14 1.52 0.045 c1 0.41 0.56 0.016 0.022 θ1 0' 15' 0' 15' c2 0.46 0.86 0.018 0.034 θ2 25' 35' 25' 35' D 5.97 6.22 0.235 0.245 ECN: E21-0605-Rev. B, 25-Oct-2021 DWG: 5968 Notes • Dimensioning and tolerancing per ASME Y14.5M-1994 • Dimension are shown in inches and millimeters • Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body • Thermal pad contour optional with dimensions b4, L2, E1 and D1 • Lead dimension uncontrolled in L3 • Dimension b1, b3 and c1 apply to base metal only • Outline conforms to JEDEC® outline TO-251AA Document Number: 91362 1 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Revision: 25-Oct-2021 Package Information www.vishay.com Vishay Siliconix OPTION 2: FACILITY CODE = N E A L2 b4 c2 E1 D2 θ1 CL L4 θ1 D D1 Ø 1.00 x 0.10 deep C B B L L3 L1 C b2 A1 b b1, b3 c c e c1 θ2 Third angle projection b, b2 Section “B-B” and “C-C” DIM. MIN. NOM. MAX. DIM. MIN. NOM. A 2.180 2.285 2.390 D2 5.380 - MAX. - A1 0.890 1.015 1.140 E 6.350 6.540 6.730 b 0.640 0.765 0.890 E1 4.32 - - b1 0.640 0.715 0.790 e b2 0.760 0.950 1.140 L 8.890 2.29 BSC 9.270 9.650 b3 0.760 0.900 1.040 L1 1.910 2.100 2.290 b4 4.950 5.205 5.460 L2 0.890 1.080 1.270 c 0.460 - 0.610 L3 1.140 1.330 1.520 c1 0.410 - 0.560 L4 1.300 1.400 1.500 c2 0.460 - 0.610 θ1 0° 7.5° 15° D 5.970 6.095 6.220 θ2 4° - - D1 4.300 - - ECN: E21-0605-Rev. B, 25-Oct-2021 DWG: 5968 Notes • Dimensioning and tolerancing per ASME Y14.5M-1994 • All dimension are in millimeters, angles are in degrees • Heat sink side flash is max. 0.8 mm Document Number: 91362 2 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Revision: 25-Oct-2021 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR DPAK (TO-252) 0.224 0.243 0.087 (2.202) 0.090 (2.286) (10.668) 0.420 (6.180) (5.690) 0.180 0.055 (4.572) (1.397) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE Document Number: 72594 Revision: 21-Jan-08 www.vishay.com 3 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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ALL RIGHTS RESERVED Revision: 09-Jul-2021 1 Document Number: 91000