SiP32431DN, SiP32431DR, SiP32432DN, SiP32432DR
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Vishay Siliconix
10 pA, Ultra Low Leakage and Quiescent Current,
Load Switch with Reverse Blocking
DESCRIPTION
FEATURES
The SiP32431 and SiP32432 are ultra low leakage and
quiescent current slew rate controlled high side switches
with reverse blocking capability. The switches are of a low
on resistance p-channel MOSFET that supports continuous
current up to 1.4 A.
• 1.5 V to 5.5 V input voltage range
• No bias power rail required
• Low on-resistance RDS(on),
typically 105 m at 5 V and 135 m at 3 V for
TDFN4 1.2 mm x 1.6 mm package
The SiP32431 and SiP32432 operate with an input voltage
from 1.5 V to 5.5 V.
• Typical 147 m at 5 V and 178 m at 3 V for
SC-70-6 package
The SiP32431 and SiP32432 feature low input logic level to
interface with low control voltage from microprocessors.
The SiP32431 is of logic high enable control, while SiP32432
is of logic low enable control. Both devices have a very low
operating current, typically 10 pA at 3.3 V power supply.
• Slew rate controlled turn-on time: 100 μs
• Ultra low leakage and quiescent current:
- VIN quiescent current = 0.01 nA
Available
- VIN shutdown leakage = 0.20 nA
• Reverse blocking capability
• SC-70-6 and TDFN4 1.2 mm x 1.6 mm packages
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
The SiP32431 and SiP32432 are available in lead (Pb)-free
package options including 6 pin SC-70-6, and 4 pin TDFN4
1.2 mm x 1.6 mm DFN4 packages. The operation
temperature range is specified from -40 °C to +85 °C.
APPLICATIONS
The SiP32431 and SiP32432 compact package options,
operation voltage range, and low operating current make it
a good fit for battery power applications.
•
•
•
•
•
•
•
•
Wireless sensor network
Smart meters
Wearable
Internet of things
Portable medical devices
Security systems
Battery powered devices
Portable Instruments
TYPICAL APPLICATION CIRCUIT
VIN
IN
OUT
VOUT
SiP32431 / SiP32432
C IN
1 µF
C OUT
0.1 µF
ON/OFF
GND
ON/OFF
GND
GND
Fig. 1 - SiP32431, SiP32432 Typical Application Circuit
ORDERING INFORMATION
PART NUMBER
MARKING
ENABLE
SiP32431DR3-T1GE3
MAxx
High enable
SiP32432DR3-T1GE3
MDxx
Low enable
SiP32431DNP3-T1GE4
Dx
High enable
SiP32432DNP3-T1GE4
Vx
Low enable
PACKAGE
TEMPERATURE RANGE
SC-70-6
-40 °C to +85 °C
TDFN4 1.2 mm x 1.6 mm
Notes
• x = lot code
S20-0532-Rev. G, 06-Jul-2020
Document Number: 66597
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For technical questions, contact: powerictechsupport@vishay.com
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• -GE3 denotes halogen-free and RoHS-compliant
• Please use the SiP32431DR3-T1GE3 to replace SiP32431DR3-T1-E3
ABSOLUTE MAXIMUM RATINGS
PARAMETER
LIMIT
Supply input voltage (VIN)
-0.3 to +6
Enable input voltage (VON/OFF)
-0.3 to +6
Output voltage (VOUT)
Maximum continuous switch current (Imax.)
1.2
TDFN4 1.2 mm x 1.6 mm
1.4
VIN 2.5 V
3
VIN < 2.5 V
A
1.6
ESD rating (HBM)
Junction temperature (TJ)
Power dissipation (PD) a
V
-0.3 to +6
SC-70-6 package
Maximum pulsed current (IDM) VIN
(pulsed at 1 ms, 10 % duty cycle)
Thermal resistance (JA) a
UNIT
6 pin SC-70-6 b
4000
V
-40 to +125
°C
220
4 pin TDFN4 1.2 mm x 1.6 mm
c
°C/W
170
6 pin SC-70- 6 b
250
4 pin TDFN4 1.2 mm x 1.6 mm c
324
mW
Notes
a. Device mounted with all leads and power pad soldered or welded to PC board
b. Derate 4.5 mW/°C above TA = 70 °C
c. Derate 5.9 mW/°C above TA = 70 °C, see PCB layout
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating / conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
PARAMETER
LIMIT
UNIT
Input voltage range (VIN)
1.5 to 5.5
V
Operating temperature range
-40 to +85
°C
S20-0532-Rev. G, 06-Jul-2020
Document Number: 66597
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SPECIFICATIONS
PARAMETER
SYMBOL
Operating voltage c
LIMITS
-40 °C to +85 °C
TEST CONDITIONS UNLESS SPECIFIED
VIN = 5, TA = -40 °C to +85 °C
(Typical values are at TA = 25 °C)
MIN. a
VIN
Quiescent current
IQ
Off supply current
IQ(off)
Off switch current
ISD(off)
Reverse blocking current
IRB
1.5
-
5.5
-
0.01
100
1000
VIN = 5 V, Von/off = 5 V
-
0.05
VIN = 3.3 V, Von/off = 0 V, OUT = open
-
0.01
100
VIN = 5 V, Von/off = 0 V, OUT = open
-
-
1000
VIN = 3.3 V, Von/off = 0 V, OUT = 1 V
-
0.2
100
VIN = 5 V, Von/off = 0 V, OUT = 0 V
-
-
1000
VOUT = 5.5 V, VIN = 0, Von/off = inactive
-
130
1000
-
147
105
155
110
178
135
275
230
395
350
VIN = 4.2 V, IL = 500 mA, TA = 25 °C
RDS(on)
VIN = 3 V, IL = 500 mA, TA = 25 °C
VIN = 1.8 V, IL = 500 mA, TA = 25 °C
VIN = 1.5 V, IL = 500 mA, TA = 25 °C
On-resistance temp.-coefficient
On / off input low voltage c
On / off input low voltage c
VIH
On / off input leakage
SC-70-6
TDFN4
SC-70-6
TDFN4
SC-70-6
TDFN4
SC-70-6
TDFN4
SC-70-6
TDFN4
ION/OFF
Output turn-on delay time
td(on)
Output turn-on rise time
t(on)
290
m
480
520
-
2800
-
-
0.3
VIN 1.8 V to < 2.7 V
-
-
0.4
VIN 2.7 V to 5.5 V
-
-
0.6
VIN 1.5 V to < 2.7 V
1.3
-
-
VIN 2.7 V to < 4.2 V
1.5
-
-
VIN 4.2 V to 5.5 V
1.8
-
-
Von/off = 3.3 V
-
0.014
100
Von/off = 5.5 V
-
0.042
1000
-
20
40
-
140
180
4
10
Output turn-off delay time
td(off)
Notes
a. The algebriac convention whereby the most negative value is a minimum and the most positive a maximum
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing
c. For VIN outside this range consult typical on / off threshold curve
nA
250
-
VIN = 5 V, Rload = 10 , TA = 25 °C
V
230
VIN 1.5 V to < 1.8 V
TDRDS
VIL
UNIT
MAX. a
VIN = 3.3 V, Von/off = 3.3 V
VIN = 5 V, IL = 500 mA, TA = 25 °C
On-resistance
TYP. b
ppm/°C
V
nA
μs
PIN CONFIGURATION
OUT
1
6
N/C
GND
2
5
GND
ON/OFF
3
4
IN
ON/OFF
4
1
OUT
2
GND
GND
IN
3
Bottom View
Top View
Fig. 2 - SC-70-6 Package
Fig. 3 - TDFN4 1.2 mm x 1.6 mm Package
PIN DESCRIPTION
PIN NUMBER
SC-70-6
TDFN4
4
3
S20-0532-Rev. G, 06-Jul-2020
NAME
FUNCTION
IN
This pin is the p-channel MOSFET source connection. Bypass to ground through a 1 μF capacitor
Document Number: 66597
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PIN DESCRIPTION
PIN NUMBER
SC-70-6
TDFN4
2, 5
3
1
2
4
1
NAME
FUNCTION
GND
ON / OFF
OUT
Ground connection
Enable input
This pin is the p-channel MOSFET drain connection. Bypass to ground through a 0.1 μF capacitor
S20-0532-Rev. G, 06-Jul-2020
Document Number: 66597
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TYPICAL CHARACTERISTICS (internally regulated, 25 °C, unless otherwise noted)
0.12
300
VIN = 5 V
ISD(OFF) - Off Switch Current (nA)
IQ - Quiescent Current (nA)
0.10
0.08
0.06
0.04
0.02
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
200
150
100
50
0
- 40
5.5
- 20
0
20
40
60
80
100
VIN (V)
Temperature (°C)
Fig. 4 - Quiescent Current vs. Input Voltage
Fig. 7 - Off Switch Current vs. Temperature
350
550
for SC70-6 package
500
300
IL = 1.2 A
450
RDS - On-Resistance (mΩ)
ISD(OFF) - Off Switch Current (nA)
250
250
200
150
100
400
300
250
200
150
50
IL = 500 mA
350
IL = 100 mA
100
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
50
1.0
6.0
VIN (V)
3.0 3.5
VIN (V)
Fig. 5 - Off Switch Current vs. Input Voltage
Fig. 8 - RDS(on) vs. VIN for SC-70-6 Package
10
1.5
2.0
2.5
4.0
4.5
5.0
5.5
550
500
for TDFN4 package
RDS - On-Resistance (mΩ)
IQ - Quiescent Current (nA)
450
1
0.1
VIN = 5 V
0.01
400
IL = 1.2 A
350
300
IL = 500 mA
250
200
150
IL = 100 mA
VIN = 3 V
0.001
- 40
- 20
0
20
40
100
60
80
100
Temperature (°C)
Fig. 6 - Quiescent Current vs. Temperature
S20-0532-Rev. G, 06-Jul-2020
50
1.5
2.0
2.5
3.0
3.5
4.0
VIN (V)
4.5
5.0
5.5
Fig. 9 - RDS(on) vs. Input Voltage
Document Number: 66597
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TYPICAL CHARACTERISTICS (internally regulated, 25 °C, unless otherwise noted)
600
VIN = 0 V
IRB - Reverse Blocking Current (nA)
IRB - Reverse Blocking Current (nA)
1000
100
10
1
0.1
0.01
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
400
300
200
100
0
- 40
5.5
- 20
0
20
40
60
80
100
VOUT (V)
Temperature (°C)
Fig. 10 - Reverse Blocking Current vs. VOUT
Fig. 13 - Reverse Blocking Current vs. Temperature
1.6
220
210
ILOAD = 500 mA
for SC70-6 package
1.4
On/Off Threshold Voltage (V)
200
RDS - On-Resistance (mΩ)
VOUT = 5.5 V
VIN = 0 V
500
190
180
170
160
VIN = 3 V
VIN = 5 V
150
140
1.2
VIH
1.0
VIL
0.8
0.6
130
120
- 40
- 20
0
20
40
60
80
0.4
1.5
100
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Temperature (°C)
VIN (V)
Fig. 11 - RDS(on) vs. Temperature
Fig. 14 - On / Off Threshold vs. Input Voltage
Axis Title
180
40 000
ILOAD = 500 mA
for TDFN4 package
35 000
140
VIN = 3 V
120
100
VIN = 5 V
30 000
VEN = 5 V
1000
25 000
1 t li
IEN Current (pA)
RDS - On-Resistance (mΩ)
160
20 000
15 000
VEN = 3.6 V
100
10,000
80
60
- 40
10000
5000
- 20
0
20
40
60
80
100
0
-40
10
-20
0
20
40
60
80
100 120
Temperature (°C)
Temperature (°C)
Fig. 12 - RDS(on) vs. Temperature
Fig. 15 - IEN Current vs. Temperature
S20-0532-Rev. G, 06-Jul-2020
Document Number: 66597
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TYPICAL WAVEFORMS
Fig. 16 - Switching (VIN = 3 V)
Fig. 18 - Turn-Off (VIN = 3 V)
Fig. 17 - Switching (VIN = 5 V)
Fig. 19 - Turn-Off (VIN = 5 V)
BLOCK DIAGRAM
Reverse
Blocking
OUT
IN
Turn-On
Slew Rate
Control
Level
Shift
ON/OFF
GND
Fig. 20 - Functional Block Diagram
S20-0532-Rev. G, 06-Jul-2020
Document Number: 66597
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PCB LAYOUT
Fig. 21 - Top, TDFN4 1.2 mm x 1.6 mm PCB Layout
Fig. 22 - Bottom, TDFN4 1.2 mm x 1.6 mm PCB Layout
DETAILED DESCRIPTION
Protection Against Reverse Voltage Condition
The SiP32431 and SiP32432 are p-channel MOSFET power
switches designed for high-side slew rate controlled
load-switching applications. Once turned on, the slew-rate
control circuitry is activated and current is ramped in a linear
fashion until it reaches the level required for the output load
condition. This is accomplished by first elevating the gate
voltage of the MOSFET up to its threshold voltage and then
by linearly increasing the gate voltage until the MOSFET
becomes fully enhanced. At this point, the gate voltage is
then quickly increased to the full input voltage to reduce
RDS(on) of the MOSFET switch and minimize any associated
power losses.
The SiP32431 and SiP32432 contain a body snatcher that
normally connects the body to the source (IN) when the
device is enabled. In case where the device is disabled but
the VOUT is higher than the VIN, the n-type body is switched
to out, reverse bias the body diode to prevent the current
from going back to the input.
APPLICATION INFORMATION
Input Capacitor
While a bypass capacitor on the input is not required, a 1 μF
or larger capacitor for CIN is recommended in almost all
applications. The bypass capacitor should be placed as
physically close as possible to the input pin to be effective
in minimizing transients on the input. Ceramic capacitors are
recommended over tantalum because of their ability to
withstand input current surges from low impedance sources
such as batteries in portable devices.
Output Capacitor
A 0.1 μF capacitor or larger across VOUT and GND is
recommended to insure proper slew operation. COUT may
be increased without limit to accommodate any load
transient condition with only minimal affect on the SiP32431
and SiP32432 turn on slew rate time. There are no ESR or
capacitor type requirement.
Enable
The on / off pin is compatible with both TTL and CMOS logic
voltage levels.
S20-0532-Rev. G, 06-Jul-2020
Thermal Considerations
The physical limitations of the layout and assembly of the
device limit the maximum current levels as stated in the
Absolute Maximum Ratings table. However, another limiting
characteristic for the safe operating load current is the
thermal power dissipation of the package. To obtain the
highest power dissipation, the power pad of the TDFN4
package should be connected to a heat sink on the printed
circuit board.
The maximum power dissipation in any application is
dependent on the maximum junction temperature,
TJ (max.) = 125 °C, the junction-to-ambient thermal resistance
for the TDFN4 1.2 mm x 1.6 mm package, J-A = 170 °C/W,
and the ambient temperature, TA, which may be
formulaically expressed as:
125 – T A
T J (max.) – T A
P (max.) = --------------------------------- = ---------------------J – A
170
It then follows that, assuming an ambient temperature of
70 °C, the maximum power dissipation will be limited to
about 324 mW.
So long as the load current is below the absolute maximum
limits, the maximum continuous switch current becomes a
function two things: the package power dissipation and the
RDS(on) at the ambient temperature.
As an example let us calculate the worst case maximum
load current at TA = 70 °C. The worst case RDS(on) at 25 °C
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occurs at an input voltage of 1.5 V and is equal to 520 m.
The RDS(on) at 70 °C can be extrapolated from this data using
the following formula
RDS(on) (at 70 °C) = RDS(on) (at 25 °C) x (1 + TC x T)
Where TC is 3300 ppm/°C. Continuing with the calculation
we have
RDS(on) (at 70 °C) = 520 m x (1 + 0.0033 x (70 °C - 25 °C)) =
597 m
The maximum current limit is then determined by
P (max.)
I LOAD (max.) ---------------------R DS on
which in case is 0.74 A. Under the stated input voltage
condition, if the 0.74 A current limit is exceeded the internal
die temperature will rise and eventually, possibly damage
the device.
S20-0532-Rev. G, 06-Jul-2020
Vishay Siliconix
Document Number: 66597
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PRODUCT SUMMARY
Part number
SiP32431DN
SiP32431DR
SiP32432DN
SiP32432DR
Description
1.5 V to 5.5 V, 105
m, 10 pA IQ,
bidirectional off
isolation, EN active
high
1.5 V to 5.5 V, 147
m, 10 pA IQ,
bidirectional off
isolation, EN active
high
1.5 V to 5.5 V, 105
m, 10 pA IQ,
bidirectional off
isolation, EN active
low
1.5 V to 5.5 V, 147
m, 10 pA IQ,
bidirectional off
isolation, EN active
low
Configuration
Single
Single
Single
Single
Slew rate time (μs)
140
140
140
140
On delay time (μs)
20
20
20
20
Input voltage min. (V)
1.5
1.5
1.5
1.5
Input voltage max. (V)
5.5
5.5
5.5
5.5
On-resistance at input voltage min. (m)
350
395
350
395
105
147
105
147
Quiescent current at input voltage min. (μA)
On-resistance at input voltage max. (m)
0.000002
0.000002
0.000002
0.000002
Quiescent current at input voltage max. (μA)
0.00004
0.00004
0.00004
0.00004
Output discharge (yes / no)
No
No
No
No
Reverse blocking (yes / no)
Yes
Yes
Yes
Yes
Continuous current (A)
1.4
1.4
1.4
1.4
Package type
Package size (W, L, H) (mm)
TDFN4
SC-70-6
TDFN4
SC-70-6
1.2 x 1.6 x 0.5
2.0 x 2.0 x 0.5
1.2 x 1.6 x 0.5
2.0 x 2.0 x 0.5
Status code
2
2
2
2
Product type
Slew rate
Slew rate
Slew rate
Slew rate
Applications
Computers,
consumer, industrial,
healthcare,
networking, portable
Computers,
consumer, industrial,
healthcare,
networking, portable
Computers,
consumer, industrial,
healthcare,
networking, portable
Computers,
consumer, industrial,
healthcare,
networking, portable
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?66597.
S20-0532-Rev. G, 06-Jul-2020
Document Number: 66597
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Package Information
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Vishay Siliconix
TDFN4 1.2 x 1.6 Case Outline
D
D2
4
b
3
Pin #1 ID
(Optional)
4
K
E
E2
3
1
2
e
Index Area
(D/2 x E/2)
Bottom View
A
A1
Top View
A3
1
L
2
Side View
DIM.
MILLIMETERS
INCHES
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A
0.45
0.55
0.60
0.017
0.022
0.024
A1
0.00
-
0.05
0.00
-
A3
0.15 REF. or 0.127 REF.
(1)
0.006 or 0.005
0.002
(1)
b
0.20
0.25
0.30
0.008
0.010
0.012
D
1.15
1.20
1.25
0.045
0.047
0.049
D2
0.81
0.86
0.91
0.032
0.034
0.036
e
0.50 BSC
0.020
E
1.55
1.60
1.65
0.061
0.063
0.065
E2
0.45
0.50
0.55
0.018
0.020
0.022
K
L
0.25 typ.
0.25
0.30
0.010 typ.
0.35
0.010
0.012
0.014
ECN: T16-0143-Rev. C, 18-Apr-16
DWG: 5995
Note
(1) The dimension depends on the leadframe that assembly house used.
Revision: 18-Apr-16
Document Number: 65734
1
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
SC-70:
3/4/5/6-LEADS (PIC ONLY)
0.15 (0.006)
D
C
e1
A
A
D
N5
N4
N3
E/2
E1/2
E
E/1
0.15 (0.006)
C
Pin 1
N1
N2
B
e
See Detail A
C
0.10 (0.004)
M
C
A
b
B
U1
A2
A
SEATING
PLANE
0.10 (0.004)
C
A1
C
H
(b)
0.15 (0.0059)
b1
c1
GAGE PLANE
c
Base Metal
DETAIL A
SECTIION A-A
Pin
Code
N1
N2
N3
N4
N5
U
L
LEAD COUNT
NOTES:
3
4
5
6
1.
Dimensioning and tolerancing per ANSI Y14.5M-1994.
−
−
2
2
2.
2
2
3
3
Controlling dimensions: millimeters converted to inch dimensions are
not necessarily exact.
−
3
4
4
3.
3
−
−
5
Dimension “D” does not include mold flash, protrusion or gate burr.
Mold flash, protrusion or gate burr shall not exceed 0.15 mm
(0.006 inch) per side.
−
4
5
6
4.
The package top shall be smaller than the package bottom.
Dimension “D” and “E1” are determined at the outer most extremes
of the plastic body exclusive of mold flash, tie bar burrs, gate burrs
and interlead flash, but including any mismatch between the top and
bottom of the plastic body.
Document Number: 73201
19-Nov-04
www.vishay.com
1
Package Information
Vishay Siliconix
MILLIMETERS
INCHES
Dim
Min
Nom
Max
Min
Nom
Max
A
0.80
−
1.10
0.031
−
0.043
A1
0.00
−
0.10
0.000
−
0.004
A2
0.80
0.90
1.00
0.031
0.035
0.040
b
0.15
−
0.30
0.006
−
0.012
b1
0.15
0.20
0.25
0.006
0.008
0.010
c
0.08
−
0.25
0.003
−
0.010
c1
0.08
0.13
0.20
0.003
0.005
0.008
D
1.90
2.10
2.15
0.074
0.082
0.084
E
2.00
2.10
2.20
0.078
0.082
0.086
E1
1.15
1.25
1.35
0.045
0.050
0.055
e
0.65 BSC
0.0255 BSC
e1
1.30 BSC
0.0512 BSC
L
0.26
0.36
0.46
0.010
0.014
0.018
U
0_
−
8_
0_
−
8_
U1
4_
10_
4_
10_
ECN: S-42145—Rev. A, 22-Nov-04
DWG: 5941
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2
Document Number: 73201
19-Nov-04
PAD Pattern
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR TDFN4 1.2 x 1.6
0.86
0.50
3
1
2
2.0
0.55
0.20
0.50
0.20
4
0.55
0.30
Recommended Minimum Pads
Dimensions in mm
Document Number: 66558
Revision: 05-Mar-10
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1
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Revision: 01-Jan-2022
1
Document Number: 91000