SiP32441
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Vishay Siliconix
3 A, Fault Protected, Slew Rate Controlled Load Switch
DESCRIPTION
FEATURES
The SiP32441 is an integrated slew rate control load switch
operates in the voltage range of 1.7 V to 5.5 V. The
integrated charge pump drivers enable the part with low on
resistance over the wide input voltage range. Its VIN can
tolerate over -2 V without causing damage or device
malfunction.
• 1.7 V to 5.5 V input voltage range
• Negative input voltage tolerance down to -2 V
• 38 mΩ typical RON from 1.8 V to 5 V
• 3 A maximum continuous switch current
• Slew rate controlled turn-on: 2.5 ms at 3.6 V
The SiP32441 features a controlled soft-on slew rate of
typical 2.5 ms that limits the inrush current for designs of
heavy capacitive load and minimizes the resulting voltage
droop at the power rails.
Available
• 2.3 V UVLO when EN is open
• Reverse current blocking when switch is off or VIN is ground
• ESD protected
- HBM: > 6 kV
- MM: > 300 V
- IEC61000-4-2 air discharge: > 15 kV
- IEC61000-4-2 contact discharge: > 8 kV
The SiP32441 integrated a special logic circuit to define the
status of the power switch. This is to meet system design of
both removable and embedded types.
The SiP32441 has exceptionally low shutdown current and
provides reverse blocking to prevent high current flowing
into the power source when the switch is off or VIN is ground.
• Compact TDFN4 package
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
The switch blocks the current flow at both forward and
reverse directions at off state. When VIN and EN are OPEN,
the switch will remains OFF in case voltage is applied on
OUT pin.
APPLICATIONS
• PDAs / smart phones
• Notebook / netbook computers
This device is specified to operate over the industrial
temperature range of -40 °C to +85 °C
• Tablet PC
• Portable media players
• Digital camera
• GPS navigation devices
• Data storage devices
• Optical, industrial, medical, and healthcare devices
TYPICAL APPLICATION CIRCUIT
VIN
IN
OUT
VOUT
SiP32441
C IN
2.2 μF
C OUT
1 μF
EN
EN
GND
GND
GND
Fig. 1 - SiP32441 Typical Application Circuit
S15-1921-Rev. A, 17-Aug-15
Document Number: 65763
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SiP32441
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ORDERING INFORMATION
Part Number
SiP32441DNP-T1-GE4
Package
Marking
Temperature Range
TDFN4 1.2 mm x 1.6 mm
Tx
-40 °C to +85 °C
Notes
• x = Lot code
• GE4 denotes halogen-free and RoHS compliant
ABSOLUTE MAXIMUM RATINGS
Parameter
Limit
Supply Input Voltage (VIN)
-2 to +6
Enable Input Voltage (VEN)
-2 to +6
Output Voltage (VOUT)
V
-0.3 to +6
Maximum Continuous Switch Current (Imax.) c
3.5
Maximum Repetitive Pulsed Current (1 ms, 10 % Duty Cycle)
c
Maximum Non-Repetitive Pulsed Current (100 μs, EN = Active)
Thermal Resistance (qJA)
12
-40 to +150
°C
170
°C/W
a
a,b
ESD Rating
A
7
c
Junction Temperature (TJ)
Power Dissipation (PD)
Unit
735
mW
HBM
6
kV
V
MM
300
IEC41000-4-2 Air Discharge d
15
IEC41000-4-2 Contact Discharge d
8
kV
Notes
a. Device mounted with all leads and power pad soldered or welded to PC board, see PCB layout.
b. Derate 5.9 mW/°C above TA = 25 °C, see PCB layout.
c. TA = 25 °C, see PCB layout.
d. Tested on VIN with 2.2 μF CIN. VIN connected to micro-USB connector.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating/conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Parameter
Input Voltage Range (VIN)
Operating Junction Temperature Range (TJ)
S15-1921-Rev. A, 17-Aug-15
Limit
Unit
1.7 to 5.5
V
-40 to +125
°C
Document Number: 65763
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SiP32441
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SPECIFICATIONS
Parameter
Operating Voltage
Negative Input Voltage Tolerance
Under Voltage Lock Out
UVLO Hysteresis
Quiescent Current
Symbol
Test Conditions Unless Specified
VIN = 1.8 V to 5 V, TA = -40 °C to +85 °C
(typical values are at TA = 25 °C)
VIN
Limits
-40 °C to +85 °C
Unit
Min. a
Typ. b
Max. a
1.8
-
5.5
V
mA
INEG
VIN = -2 V
-
-15
-
UVLOH-L
EN = open, 25 °C (switch On to Off)
-
-
2
UVLOL-H
EN = open, 25 °C (switch Off to On)
2.5
2.3
-
UVLOHYS
IQ
EN = open, 25 °C
-
0.25
-
VIN = 1.8 V, EN = active
-
38
50
VIN = 2.5 V
-
58
70 d
VIN = 3.6 V
-
82
100 d
VIN = 4.3 V
-
101
120 d
VIN = 5 V
-
119
150
Off Supply Current
IQ(off)
VIN = 2 V, VEN = 0 V, OUT = open
-
6.3
10
Off Switch Current
IDS(off)
VIN = 2 V, VEN = 0 V, VOUT = 0 V
-
-
1
IRB
VOUT = 5 V, VIN = 0 V, VEN = 0 V or open
-
-
10
VIN = 1.8 V, IL = 500 mA, TA = 25 °C
-
38
43
VIN = 2.5 V, IL = 500 mA, TA = 25 °C
-
38
43
VIN = 3.6 V, IL = 500 mA, TA = 25 °C
-
38
43
Reverse Blocking Current
On-Resistance
Input Logic Low c
Input Logic High c
Enable Pin Bias Current
RDS(on)
VIL
VIH
IEN
Output Turn-On Delay Time
td(on)
Output Turn-On Rise Time
t(on)
Output Turn-Off Delay Time
td(off)
VIN = 4.3 V, IL = 500 mA, TA = 25 °C
-
38
43
VIN = 5 V, IL = 500 mA, TA = 25 °C
-
38
43
VIN = 1.8 V
-
-
0.5
VIN = 2.5 V
-
-
0.7 d
VIN = 3.6 V
-
-
1.1 d
VIN = 4.3 V
-
-
1.3 d
VIN = 5 V
-
-
1.5 d
VIN = 1.8 V
1.3
-
-
VIN = 2.5 V
1.6 d
-
-
VIN = 3.6 V
1.9 d
-
-
VIN = 4.3 V
2.1
d
-
-
d
VIN = 5 V
2.4
VEN = 5 V
-
VIN = 3.6 V, Rload = 10 Ω,
CL = 0.1 μF, TA = 25 °C
-
1.3
-
-
1.8
2.5
-
0.0002
-
-
-
5.4
7
V
μA
mΩ
V
μA
ms
Notes
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
c. For VIN outside this range consult typical EN threshold curve.
d. Not tested, guarantee by design.
S15-1921-Rev. A, 17-Aug-15
Document Number: 65763
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SiP32441
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PIN CONFIGURATION
OUT
4
1
IN
Bottom View
GND
EN
3
2
GND
Fig. 2 - TDFN4 1.2 mm x 1.6 mm Package
PIN DESCRIPTION
Pin Number
Name
Function
1
IN
This is the input pin of the switch
2
GND
Ground connection
3
EN
Enable input
4
OUT
This is the output pin of the switch
BLOCK DIAGRAM
Reverse
Blocking
VOUT
VIN
Negative Volt
Detect / Clamp
UVLO
EN
Control
Logic
Charge
Pump
Turn-On
Slew Rate Control
False
Detect
GND
Fig. 3 - Functional Block Diagram
TRUTH TABLE
IN
OUT
EN
SWITCH
L
X
X
OFF
> UVLO
X
ON
> 1.5
< UVLO
H
ON
L
OFF
H
L
X
OFF
H
ON
H
L
OFF
H
(1)
ON
H
Notes
It will be depending on the status of latch of the OR gate output. If latch is at high, then EN cannot off the switch. If latch is low, then EN can
off the switch.
• IN has UVLO. High at IN column means a voltage source is applied to IN, that is high enough to power the logic circuit but could be lower
than the UVLO threshold.
• EN pin has a pull down of ~1 MΩ.
• UVLO threshold is about 2.3 V.
(1)
S15-1921-Rev. A, 17-Aug-15
Document Number: 65763
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SiP32441
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DETAILED DESCRIPTION
SiP32441 is an advanced slew rate controlled high side load
switch with an integrated N-channel power switch. When
the device is on the gate of the power switch is turned on at
a controlled rate to avoid excessive inrush current. Once
fully on the gate to source voltage of the power switch is
biased at a constant level. The design gives a flat on
resistance throughout the operating voltages. A special
reverse blocking circuitry prevents current flowing from
output to input when the switch is off. The VIN and EN pin
can tolerate -2 V voltage without drawing excessive current.
The device is turn-on after the UVLO voltage regardless the
condition of the EN pin. A fault protection circuitry is
incorporated to define the status of the switch. Its states are
described in the truth table.
APPLICATION INFORMATION
Input Capacitor
In general, under steady state conditions the SiP32441 does
not require an input capacitor. Nevertheless, an input
bypass capacitor is recommended in order to reduce the
input voltage drop caused by transient inrush currents.
Commonly, a 2.2 μF ceramic capacitor is sufficient and
should be placed in close proximity to VIN and GND pins. A
higher value input capacitor can help to further reduce the
voltage drop. Ceramic capacitors are recommended for
their low ESR characteristic.
Output Capacitor
While these devices work without an output capacitor, a
1 μF or higher value capacitor across VOUT and GND is
recommended in order to handle potential load transient
conditions. In the event that the switch is turning of while
running high current, circuit stray inductances might force
the output to some negative voltage in order to mitigate this
phenomenon a proper output capacitor is required.
Enable
The device is logic high active, the enable pin voltage can
exceed VIN as long as it is within the absolute maximum
rating range.
If the input voltage is available before output voltage and
either input or output voltage is above input UVLO
threshold, the switch is on regardless of the enable pin
voltage even if the input pin is left open later. In this case, the
enable pin cannot be used to turn off the switch except in
the certain fault conditions as described by the truth table.
If the input voltage is available before output voltage and
both the input voltage and output voltage are lower than the
input UVLO threshold and above 1.5 V, the enable pin can
be used to turn on and off the switch even if either input pin
or output pin is left open later.
If the output voltage is available before the input voltage, the
enable pin can be used to turn on/off the switch.
Reverse Voltage Protection
The SiP32441 contains a reverse blocking circuitry to
protect the current from going to the input from the output
when the switch is off. Reverse blocking works for input
voltage as low as 0 V.
THERMAL CONSIDERATIONS
The maximum allowed DC Current depends on the thermal
condition in which the device operates. In order to calculate
max allowed DC current, first the max power dissipation
should be considered.
The SiP32441 is packaged in a TDFN4 1.2 mm x 1.6 mm
package which has a thermal resistance of θJ-A a = 170 °C/W.
Note
a. Device mounted with all leads and power pad soldered or
welded to PC board, see PCB layout. For any other layout
configuration the actual junction to ambient thermal impedance
should be considered
The following formula shows the maximum allowed power
dissipation as a function of the ambient temperature TA
when the maximum junction temperature is limited to
TJ (max.) = 125 °C:
Pmax. =
TJ (max.) - TA
θJ-A
=
125 - TA
170
For example at ambient temperature of 70 °C, the maximum
power dissipation will be limited to about 324 mW.
In order to calculate the maximum allowed DC current the
switch RDS(on) temperature dependency should be
considered.
As an example let us calculate maximum load current
at TA = 70 °C and input voltage of 1.8 V. At this input voltage
the RDS(on) at 25 °C 43 mΩ (see specification table). The
RDS(on) at 125 °C can be extrapolated from this data using
the following formula:
RDS(on)_125 °C = RDS(on)_25 °C x (1 + TC x (TJ max. - 25)/100 )
Where TC is the RDS(on) temperature coefficient expressed in
percent change per ° C.
For SiP32441 the approximated value is 0.31 %/°C. TJ max.
is the maximum allowed junction temperature (125 °C).
Therefore,
RDS(on) (at 125 °C) =
43 mΩ x (1 + 0.31 x (125 - 25)/100) ≈ 57 mΩ
The maximum current limit is then determined by
I LOAD (max.) <
P (max.)
R DS(on)
Which in this case is 2.38 A.
S15-1921-Rev. A, 17-Aug-15
Document Number: 65763
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SiP32441
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BOARD LAYOUT
Due to device limitation the max switch DC current
should not exceed 3 A in any condition.
To obtain the highest power dissipation the power pad of
the device should be connected to a heat sink on the printed
circuit board. Fig. 4 shows a typical PCB layout. All copper
traces and vias for the VIN and VOUT pins should be sized
adequately to carry the maximum continuous current.
Negative Input Voltage
The SiP32441 can withstand maximum negative 2 V at its
input due to any spike from abnormal or fault condition of
the system.
Recommended Board Layout
For improved performance, all traces should be as short as
possible to minimize stray inductances and parasitic effects.
The input and output capacitors should be kept as close
as possible to the input and output pins respectively.
Connecting the central exposed pad to GND, using wide
traces for input, output, and GND help reducing the case to
ambient thermal impedance. See fig. 4.
Fig. 4 - Recommended Board Layout
TYPICAL APPLICATION SCHEMATIC
J5
EN
VIN
1
U1
IN
OUT
VOUT
4
J3
EN
2
3
GND
J1
2
C2
2.2 μF
1
1
2
SiP32441
C3
1 μF
GND
GND
J2
J4
Fig. 5 - Application Schematic
S15-1921-Rev. A, 17-Aug-15
Document Number: 65763
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TYPICAL TURN-ON AND TURN-OFF WAVEFORMS
Turn-On Time
VIN = 0 V to 3.6 V, RL = 7.2 Ω, CL = 0.1 μF
Turn-Off Time
VIN = 3.6 V to 0 V, RL = 7.2 Ω, CL = 0.1 μF
Turn-On Time
VIN = 3.6 V, RL = 10 Ω between OUT and 2.5 V, CL = 0.1 μF
Turn-Off Time
VIN = 3.6 V, RL = 10 Ω between OUT and 2.5 V, CL = 0.1 μF
S15-1921-Rev. A, 17-Aug-15
Document Number: 65763
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SiP32441
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160
160
140
140
120
120
IQ - Quiescent Current (μA)
IQ - Quiescent Current (μA)
TYPICAL CHARACTERISTICS (internally regulated, 25 °C, unless otherwise noted)
100
80
60
40
100
80
VIN = 3.6 V
60
40
20
VIN = 1.7 V
20
0
1.5
2.0
2.5
3.0
3.5
VIN (V)
4.0
4.5
5.0
0
- 40
5.5
10
7.5
9
IIQ(OFF) - Off Supply Current (μA)
8.0
7.0
6.5
6.0
5.5
5.0
- 20
0
60
80
100
8
VIN = 2.0 V
7
6
VIN = 1.7 V
5
4
3
4.5
2
4.0
1.7
1.8
1.9
2.0
2.1
- 40
2.2
- 20
0
VIN (V)
20
40
60
80
100
Temperature (°C)
Fig. 10 - Off Supply Current vs. Temperature
Fig. 7 - Off Supply Current vs. Input Voltage
-0.5
20
-0.55
0
IDS(off) - Off Switch Current (nA)
IDS(off) - Off Switch Current (nA)
20
40
Temperature (°C)
Fig. 9 - Quiescent Current vs. Temperature
Fig. 6 - Quiescent Current vs. Input Voltage
IQ(OFF) - Off Supply Current (μA)
VIN = 5.5 V
-0.6
-0.65
-0.7
-0.75
-0.8
-0.85
-20
-40
VIN = 1.7 V
-60
-80
VIN = 2.0 V
-100
-120
-140
-0.9
1.7
1.8
1.9
2.0
2.1
2.2
-160
- 40
- 20
0
20
40
60
80
100
VIN (V)
Temperature (°C)
Fig. 8 - Off Switch Current vs. Input Voltage
Fig. 11 - Off Switch Current vs. Temperature
S15-1921-Rev. A, 17-Aug-15
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42.0
50
41.5
48
41.0
46
40.5
RDS - On-Resistance (mΩ)
RDS - On-Resistance (mΩ)
TYPICAL CHARACTERISTICS (internally regulated, 25 °C, unless otherwise noted)
IO = 2.0 A
40.0
IO = 1.2 A
39.5
39.0
38.5
IO = 0.5 A
38.0
IO = 0.5 A
VIN = 5 V
44
42
40
38
36
34
37.5
32
37.0
1.5
30
2.0
2.5
3.0
3.5
4.0
VIN (V)
4.5
5.0
5.5
- 40
- 20
0
20
40
60
80
100
Temperature (°C)
Fig. 12 - On-Resistance vs. Input Voltage
Fig. 15 - On-Resistance vs. Temperature
2
0.0
0
-0.5
IIN - Input Current (nA)
IVIN - Input Current (mA)
-2
-4
-6
-8
-10
-12
-1.0
VIN = 0V
-1.5
-2.0
-2.5
-3.0
-14
-3.5
-16
-18
-4.0
0.5
-2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0
1.0
1.5
2.0
VIN (V)
Fig. 13 - Input Current vs. Negative Input Voltage
3.0 3.5
VOUT (V)
4.0
4.5
5.0
5.5
Fig. 16 - Reverse Blocking Current vs. Output Voltage
2.00
1.00
1.90
1.80
0.95
1.70
1.60
tr - Rise Time (ms)
EN Threshold Voltage (V)
2.5
VIH
1.50
VIL
1.40
1.30
1.20
1.10
VIN = 5 V
CL = 0.1 μF
RL = 10 Ω to 3.5V
0.90
0.85
0.80
1.00
0.75
0.90
0.80
0.70
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
Fig. 14 - Threshold Voltage vs. Input Voltage
S15-1921-Rev. A, 17-Aug-15
0.70
- 40
- 20
0
20
40
Temperature (°C)
60
80
100
Fig. 17 - Rise Time vs. Temperature
Document Number: 65763
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TYPICAL CHARACTERISTICS (internally regulated, 25 °C, unless otherwise noted)
0.35
2.6
VIN = 5 V
CL = 0.1 μF
RL = 10 Ω to 3.5 V
td(off) - Turn-Off Delay Time (μs)
td(on) - Turn-On Delay Time (ms)
2.5
VIN = 5 V
CL = 0.1 μF
RL = 10 Ω to 3.5 V
0.30
2.4
2.3
2.2
2.1
0.25
0.20
0.15
0.10
0.05
2.0
- 40
- 20
0
20
40
60
Temperature (°C)
80
100
Fig. 18 - Turn-On Delay Time vs. Temperature
0.00
- 40
- 20
0
20
40
Temperature (°C)
60
80
100
Fig. 19 - Turn-Off Delay Time vs. Temperature
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Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?65763.
S15-1921-Rev. A, 17-Aug-15
Document Number: 65763
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Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk.
Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for
such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document
or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
Revision: 13-Jun-16
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Document Number: 91000
