SiP41111
Vishay Siliconix
75 V/2 A Peak, Low Cost, High Frequency Half Bridge Driver
DESCRIPTION
FEATURES
• Drives N-Channel MOSFET Half Bridge
SiP41111 is the MOSFET driver, which is designed to simplify the converter design for the topologies, which requires
the high-side switch such as half bridge, two switch forward
and active clamping forward. The high-side and low-side
drivers can be configured to meet different driving requirement for these topologies because the high-side and low
side drivers are independent controlled. The built-in bootstrap diode eliminates the external diode to improve the flexibility PCB layout. The VDD undervoltage lockout prevents
the abnormal operation.
Topology
• SOIC, SOIC (PowerPAK®) Package Options
• Lead (Pb)-free Product Available
(RoHS Compliant)
• Bootstrap Supply Maximum Voltage to 75 VDC
• Built-In Bootstrap Diode
RoHS
COMPLIANT
• Fast Propagation Times Meet High Frequency
Converter Circuits
• Drives 1000 pF Load with Rise and Fall Times Typical
15 ns to meet 400 kHz typical Switching Requirement
• Independent Driver Channel for Two Switch Forward and
Active Clamp Forward Topologies
• Low Power Consumption
• Supply Under Voltage Lockout
• 2.0 A Peak Sink and Source Gate Driver Current
APPLICATIONS
•
•
•
•
Half Bridge Converter
Two-Switch Forward Converters
Active Clamp Forward Converters
Bus Converters
• Motor Control
TYPICAL APPLICATION CIRCUIT
+ 48 V
+ 12 V
V DD
HB
HO
HI
V OUT
HS
+
PWM Controller
SiP41111
LI
+
LO
GND
VSS
Document Number: 74292
S-61214–Rev. A, 17-Jul-06
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SiP41111
Vishay Siliconix
BLOCK DIAGRAMS
HB
V DD
LEVEL SHIFT
HO
HI
HS
UNDER VOLTAGE
LI
LO
V SS
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage, VDD, VHB-VHS
Limit
a
Unit
- 0.3 to 14
LI and HI Voltagea
- 0.3 to VDD + 0.3
Voltage on LOa
- 0.3 to VDD + 0.3
Voltage on HOa
VHS - 0.3 to VHB + 0.3
Voltage on HSa
Continuous
- 1 to + 89
Voltage on HBa
VDD = 12 V
+ 89
Average Current in VDD to HB diode
ESD Classification
Class 1
V
100
mA
1
kV
THERMAL INFORMATION
Parameter
Limit
b
Thermal Resistance (Typical) θJA
Max Power Dissipation
Unit
SOIC
SOIC (PowerPak)b
153
at 70 °C in Free Air (SOIC)c
522
mW
at 70 °C in Free Air (SOIC PowerPAK)d
2.0
W
°C/W
40
Junction Temperature Range
- 65 to 150
Storage Temperature Range
- 55 to 150
°C
Notes:
a. All voltages are referenced to ground unless otherwise specified.
b. Device mounted with all leads soldered or welded to PC board.
c. Derate 6.5 mW/°C above + 70 °C.
d. Derate 25 mW/°C above + 70 °C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Parameter
Supply Voltage
Limit
VDD
Unit
+ 9 to 13.2
Voltage on HS
- 1 to 75
Voltage on HB
VHS + 8 to VHS + 13.2 and VDD - 1 to VDD + 75
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V
Document Number: 74292
S-61214–Rev. A, 17-Jul-06
SiP41111
Vishay Siliconix
ELECTRICAL SPECIFICATIONS VDD = VHB = 12 V, VSS = VHS = 0 V, no load on LO or HO, unless otherwise specified
TJ = 40 °C to
125 °C
TJ = 25 °C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Min
Max
VDD Quiescent Current
IDD
LI = HI = 0 V
-
0.18
0.24
-
0.27
VDD Operating Current
IDDO
f = 500 kHz
-
1.7
2.5
-
3
Total HB Quiescent Current
IHB
LI = HI = 0 V
-
0.02
0.10
-
0.15
Unit
Supply Currents
mA
Total HB Operating Current
IHBO
f = 500 kHz
-
1.5
2.5
-
3
HB to VSS Quiescent
Current
IHBS
VHS = VHB = 89 V
-
7
12
-
15
µA
HB to VSS Operating
Current
IHBSO
f = 500 kHz
-
0.6
-
-
-
mA
Input Pins
Low Level Input Voltage
Thresold
VIL
4
4.5
-
3
-
High Level Input Voltage
Threshold
VIH
-
5.5
7
-
8
Input Voltage Hysteresis
VIHYS
-
1.0
-
-
-
RI
-
300
-
100
600
VDD Rising Threshold
VDDR
6.6
7.1
7.6
6.4
7.8
VDD Threshold Hysteresis
VDDH
-
1.3
-
-
-
Input Pulldown Resistance
V
kΩ
Supply Undervoltage Protection
V
Bootstrap Diode
Low-Current Forward Drop
Out Voltage
High-Current Forward Drop
Out Voltage
VDL
IVDD-HB = 100 µA
-
1.25
1.4
-
1.8
VDH
IVDD-HB = 100 mA
-
1.8
2.0
-
2.2
Dynamic Resistance
RD
IVDD-HB = 100 mA
-
1.5
-
-
-
VOLL
ILO = 100 mA
-
0.25
0.3
-
0.4
High Level Output Voltage
VOHL
ILO - 100 mA,
VOHL = VDD - VLO
-
0.25
0.3
-
0.4
Peak Sourcing Current
IOHL
VLO = 0 V
-
2
-
-
-
Peak Sinking Current
IOLL
VLO = 12 V
-
2
-
-
-
Low Level Output Voltage
VOLH
IHO = 100 mA
-
0.25
0.3
-
0.4
V
High Level Output Voltage
VOHH
IHO = - 100 mA
VOHH = VHB - VHO
-
0.25
0.3
-
0.4
V
Peak Sourcing Current
IOHH
VHO = 0 V
-
2
-
-
-
A
Peak Sinking Current
IOLH
VHO = 12 V
-
2
-
-
-
A
V
Ω
LO Gate Driver
Low Level Output Voltage
V
A
HO Gate Driver
Document Number: 74292
S-61214–Rev. A, 17-Jul-06
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SiP41111
Vishay Siliconix
ELECTRICAL SPECIFICATIONS VDD = VHB = 12 V, VSS = VHS = 0 V, no load on LO or HO, unless otherwise specified
TJ = 25 °C
Parameter
Lower Turn-Off Propagation
Delay (LI Falling to LO Falling)
Upper Turn-Off Propagation
Delay (HI Falling to HO Falling)
Lower Turn-On Propagation Delay
(LI Rising to LO Rising)
Upper Turn-On Propagation Delay
(HI Rising to HO Rising)
Delay Matching: Lower Turn-On and
Upper Turn-Off
Delay Matching: Lower Turn-Off and
Upper Turn-On
Symbol
Test Conditions
Min
Typ
Max
tLPHL
-
18
-
tHPHL
-
18
-
tLPLH
-
23
-
tHPLH
-
23
-
tMON
-
5.5
-
tMOFF
-
6.5
-
Low-side Output Rise Time
tRCL
-
14
-
High-side Output Rise Time
tRCH
-
13
-
Low-side Output Fall Time
tFCL
-
15
-
High-side Output Fall Time
tFCH
-
15
-
Either Output Rise Time
Driving DMOS
tRD
-
27
-
Either Output Fall Time
Driving DMOS
Minimum Input Pulse Width
that Changes the Output
Bootstrap Diode Turn-On or Turn-Off
Time
tFD
-
30
-
tPW
-
-
65
tBS
-
10
-
Unit
ns
CL = 1000 pF
CL = Si7456DP
Ciss = 3100 pF
CL = Si7456DP
Ciss = 3100 pF
TIMING DIAGRAMS
LI
HI, LI
t HPLH , t LPLH
HO, LO
HI
t HPHL, t LPHL
LO
t MON
t MOFF
HO
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Document Number: 74292
S-61214–Rev. A, 17-Jul-06
SiP41111
Vishay Siliconix
PIN CONFIGURATION
TOP VIEW
TOP VIEW
VDD
LO
VDD
HB
VSS
HB
LO
VSS
PowerPak
HO
LI
HO
LI
HS
HI
HS
HI
SOIC-8
SOIC-8 (PowerPak)
PIN DESCRIPTIONS
Symbol
Descriptions
VDD
Input power supply to IC and lower gate drivers
HB
Floating boostrap supply for the upper MOSFET. External bootstrap capacitor is required
HO
Output drive for upper MOSFET. Connect to gate of upper power MOSFET
HS
Floating GND for the upper MOSFET. Connect to source of upper power MOSFET
HI
Input for upper drive
LI
Input for lower drive
VSS
Ground supply
LO
Output drive for lower MOSFET. Connect to gate of lower power MOSFET
PowerPAK
Exposed PowerPAK is for heat dissipation. Exposed PowerPAK is floating or grounded. The PowerPad is not
guaranteed electrically isolated from all other pins
ORDERING INFORMATION
Part Number
SiP41111DY-T1-E3
SiP41111DYP-T1-E3
Marking
41111
41111
Temperature Range
- 40 to 85 °C
- 40 to 85 °C
Package
SOIC-8
SOIC-8 PowerPAK
TYPICAL APPLICATION CIRCUITS
+ 48 V
+ 12 V
VDD
HB
HO
HI
V OUT
HS
+
PWM Controller
SiP41111
+
LO
LI
GND
V SS
Two Switch Forward Application Circuit
Document Number: 74292
S-61214–Rev. A, 17-Jul-06
www.vishay.com
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SiP41111
Vishay Siliconix
+ 24 V
+ 12 V
V OUT
+
VDD
HB
HO
HI
HS
+
PWM Controller
SiP41111
LI
GND
LO
V SS
Active Clamp Forward Application Circuit
TYPICAL CHARACTERISTICS
10
10
1
I HB (mA)
I DDO (mA)
1
T = - 40 °C
T = 25 °C
T = 150 °C
T = 125 °C
0.1
T = - 40 °C
T = 25 °C
T = 150 °C
T = 125 °C
0.1
10
100
1000
0.01
10
100
Frequency (kHz)
Frequency (kHz)
1000
HB Operating Current vs. Frequency
Operating Current vs. Frequency
400
10
VDD = VHB = 9 V
300
VOHL, VOHH (mV)
I HBSO (mA)
1
T = - 40 °C
T = 25 °C
T = 150 °C
T = 125 °C
0.1
VDD = VHB = 12 V
200
VDD = VHB = 13.2 V
100
0.01
10
100
Frequency (kHz)
HB to Vss Operating Current vs. Frequency
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1000
0
- 45
- 10
25
60
95
130
Temperature (°C)
High Level Output Voltage vs. Temperature
Document Number: 74292
S-61214–Rev. A, 17-Jul-06
SiP41111
Vishay Siliconix
TYPICAL CHARACTERISTICS
400
7.8
VDD = VHB = 12 V
VDD = VHB = 9 V
7.6
7.4
VDDR (V)
VOLL, VOLH (mV)
300
200
7.2
VDD = VHB = 13.2 V
7
100
6.8
0
6.6
- 45
- 10
25
60
95
130
- 45
- 10
25
Temperature (°C)
95
130
Temperature (°C)
Undervoltage Lockout Threshold vs. Temperature
Low Level Output Voltage vs. Temperature
40
t LPLH,t LPHL,t HPLH,t HPHL(ns)
1.5
1.4
VDDH (V)
60
1.3
1.2
t LPLH
tHPLH
35
30
25
t HPHL
t LPHL
20
15
- 10
25
60
95
130
- 50
0
50
100
150
Temperature (°C)
Temperature (°C)
Undervoltage Lockout Hysteresis vs. Temperature
Propagation Delay vs. Temperature
2
2
1.8
1.8
1.6
1.6
1.4
1.4
1.2
1.2
ILO,I HO (A)
IHO ,ILO (A)
1.1
- 45
1
0.8
1
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
0
2
4
6
8
10
11
VHO ,VLO (V)
Peak Source Current vs. Output Voltage
Document Number: 74292
S-61214–Rev. A, 17-Jul-06
12
0
2
4
6
8
10
11
12
VLO,VHO (V)
Peak Sink Current vs. Output Voltage
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SiP41111
Vishay Siliconix
TYPICAL CHARACTERISTICS
1
250
1-1
IDD vs VDD
1-2
1
IDD, IHB (mA)
Forward Current (A)
200
-3
1-4
150
100
IHB vs VHB
50
-5
1
1-6
0
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
0
5
Forward Voltage (V)
Bootstrap Diode I-V Characteristics
10
15
VDD, VHB (V)
Quiescent Current vs. Voltage
DETAIL DESCRIPTION
The SiP41111 IC is the high-speed 2 A half bridge MOSFET
drivers, which operating between 9 V to 13.2 V. The drivers
are designed to drive the upper MOSFET switch directly
without any isolation devices for half bridge topology and
other topologies, which require the upper switch MOSFET.
without significant voltage drop on the bootstrap capacitor.
Low ESR ceramic capacitor is recommended for this application.
Built-in Bootstrap Diode
The thermally enhanced PowerPak SOIC package can dissipate more heat to meet the aggressive 400 kHz switching
frequency while driving 1000 pf total gate capacitance
MOSFET with typical 15 ns rise and fall time.
Bootstrap Supply Operation
The power to drive the high-side MOSFET gate comesfrom
the external bootstrap capacitor. This capacitor charges
through built-in diode during the time when the low-side
MOSFET is on (HS is at GND potential), and then provides
the necessary charge to turn on the high-side MOSFET.
A built-in bootstrap diode eliminates the external discrete
diode to improve flexibility of PCB layout in field application.
The bootstrap diode is connected between Pin VDD and HB.
The diode is used to charge up the external bootstrap capacitor while the lower MOSFET is on, and isolated VDD while
the lower MOSFET is off. The voltage rating of the built-in
diode is 89 V. This voltage rating enables the half bridge and
two switch forward design for 48 V input converter and 24 V
input active clamp forward converter. The typical forward
drop out voltage is 1.8 V and the reverse time is 10 ns to
meet 400 kHz-switching requirement.
Under Voltage Lockout Function
Bootstrap Capacitor Selection
The capacitance of bootstrap capacitor should be carefully
selected to avoid the unexpected oscillations at HO pin. The
typical capacitance value for the bootstrap capacitor should
be at least 0.1 uf to 1 uf or at least 20 time of the total gate
capacitance of MOSFET. The energy in the bootstrap capacitor should large enough to supply the driving current for the
upper MOSFET during the on time of the upper MOSFET
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The SiP41111 has an internal under-voltage lockout feature
to prevent driving the MOSFET gates when the supply voltage (at VDD) is less than the under-voltage lockout specification (VDDR). This prevents the output MOSFET from being
turned on without sufficient gate voltage to ensure they are
fully on.
Document Number: 74292
S-61214–Rev. A, 17-Jul-06
SiP41111
Vishay Siliconix
Thermal Consideration
Layout Consideration
The thermal issue of the IC cannot be ignored because the
driver IC is the power conversion device. The IC can generate unexpected amount of heat to have high temperature if
the thermal issue is not carefully considered at begin of the
system level design. The additional heat sink for the IC will
increase the cost of materials. The best solution to settle the
thermal issue to improve the reliability of the system design
is to increase the trace copper area as much as possible for
heat dissipation. The PCB traces are not only for electrical
connection. It is also used for heat dissipation.
Careful PCB layout design is absolutely necessary for any
high frequency switching device to avoid circuit function and
EMI issues. The following guideline should be carefully followed to optimize the performance of SiP41111 driver.
1. It is strongly recommended to place a 0.1 uf lower ESR
decoupling ceramic capacitor right next to the IC from
VDD to VSS.
The PowerPAK SOIC package is designed to meet the
higher ambient environment operation. A heat dissipation
pad is built under the body of the SOIC package. Availability
of heat dissipation pad under the body of the package
doesn't means the thermal issue can be ignored because the
PowerPAK is designed to mount the body of the package on
the PCB trace for heat dissipation. The PowerPAK cannot
dissipate enough heat to provide a cool environment for the
IC because the surface area of PowerPAK is small. Large
trace area is the best way to control the temperature of the
IC in the high ambient environment.
2. The loops formed between device and the gate of the
MOSFET should be as small as possible. It is strongly
recommended to place the IC right next to the gate of the
MOSFET to form small driving loop between pin HO, HS,
LO and Vss because high frequency, huge instantaneous current is being sunk and sourced in these loop to
drive the gate of the MOSFET, which look like a large
capacitive load to the device. If the physical distance can
not be minimized due to PCB layout mechanical specification, the width of the loop traces should be increased
as much as possible to reduce the impedance of the loop
traces.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability
data, see http://www.vishay.com/ppg?74292.
Document Number: 74292
S-61214–Rev. A, 17-Jul-06
www.vishay.com
9
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Vishay
Disclaimer
All product specifications and data are subject to change without notice.
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(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
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Document Number: 91000
Revision: 18-Jul-08
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