SiR150DP
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Vishay Siliconix
N-Channel 45 V (D-S) MOSFET
FEATURES
PowerPAK® SO-8 Single
D
5
D
6
D
7
• TrenchFET® Gen IV power MOSFET
D
8
• 45 V Drain-source break-down voltage
• Tuned for low Qg and Qoss
• 100 % Rg and UIS tested
6.
15
m
m
m
1
5m
5.1
Top View
3
4 S
G
Bottom View
2
S
1
S
APPLICATIONS
D
• Synchronous rectification
PRODUCT SUMMARY
VDS (V)
RDS(on) max. () at VGS = 10 V
RDS(on) max. () at VGS = 4.5 V
Qg typ. (nC)
ID (A) a
Configuration
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
• High power density DC/DC
45
0.00271
0.00397
21.4
110
Single
• Motor drive control
G
S
N-Channel MOSFET
ORDERING INFORMATION
Package
Lead (Pb)-free and halogen-free
PowerPAK SO-8
SiR150DP-T1-RE3
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER
Drain-source voltage
Gate-source voltage
Continuous drain current (TJ = 150 °C)
SYMBOL
VDS
VGS
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
Pulsed drain current (t = 100 μs)
ID
IDM
Continuous source-drain diode current
TC = 25 °C
TA = 25 °C
IS
Single pulse avalanche current
Single pulse avalanche Energy
L = 0.1 mH
IAS
EAS
Maximum power dissipation
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
PD
Operating junction and storage temperature range
Soldering recommendations (peak temperature) d, e
TJ, Tstg
LIMIT
45
+20, -16
110
88
30.9 b, c
24.6 b, c
300
59.7
4.7 b, c
30
45
65.7
42
5.2 b, c
3.3 b, c
-55 to +150
260
UNIT
V
A
mJ
W
°C
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYPICAL
MAXIMUM
UNIT
Maximum junction-to-ambient b, f
t 10 s
RthJA
20
24
°C/W
Maximum junction-to-case (drain)
Steady state
RthJC
1.5
1.9
Notes
a. Based on TC = 25 °C
b. Surface mounted on 1" x 1" FR4 board
c. t = 10 s
d. See solder profile (www.vishay.com/doc?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper
(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not
required to ensure adequate bottom side solder interconnection
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components
f. Maximum under steady state conditions is 62.5 °C/W
g. Package limited
S19-0653-Rev. A, 05-Aug-2019
Document Number: 77131
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For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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SiR150DP
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Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
Static
Drain-source breakdown voltage
VDS
VGS = 0 V, ID = 1 mA
45
-
-
VDS/TJ
ID = 1 mA
-
28
-
VGS(th) temperature coefficient
VGS(th)/TJ
ID = 250 μA
-
-5.4
-
Gate-source threshold voltage
VDS temperature coefficient
mV/°C
VGS(th)
VDS = VGS, ID = 250 μA
1.1
-
2.3
V
Gate-source leakage
IGSS
VDS = 0 V, VGS = +20, -16 V
-
-
± 100
nA
Zero gate voltage drain current
IDSS
On-state drain current a
ID(on)
Drain-source on-state resistance a
Forward transconductance a
RDS(on)
gfs
VDS = 45 V, VGS = 0 V
-
-
1
VDS = 45 V, VGS = 0 V, TJ = 75 °C
-
-
20
VDS 5 V, VGS = 10 V
50
-
-
VGS = 10 V, ID = 15 A
-
0.00225 0.00271
VGS = 4.5 V, ID = 15 A
-
0.00305 0.00397
VDS = 10 V, ID = 15 A
-
72
-
μA
A
S
Dynamic b
Input capacitance
Ciss
-
4000
-
Output capacitance
Coss
-
630
-
Reverse transfer capacitance
Crss
-
56
-
-
0.014
0.028
-
46.7
70
-
21.4
32
-
11.1
-
-
3.6
-
VDS = 20 V, VGS = 0 V, f = 1 MHz
Crss/Ciss ratio
Total gate charge
Qg
VDS = 20 V, VGS = 10 V, ID = 15 A
VDS = 20 V, VGS = 4.5 V, ID = 15 A
Gate-source charge
Qgs
Gate-drain charge
Qgd
Output charge
Qoss
VDS = 20 V, VGS = 0 V
-
28
-
Gate resistance
Rg
f = 1 MHz
0.5
1.15
2
-
15
30
-
6
12
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Turn-on delay time
Rise time
Turn-off delay time
Fall time
td(on)
tr
td(off)
VDD = 20 V, RL = 2
ID 10 A, VGEN = 10 V, Rg = 1
pF
-
nC
-
30
60
tf
-
6
12
td(on)
-
30
60
-
67
134
-
28
56
-
10
20
-
-
59.7
-
-
300
-
0.72
1.1
V
-
32
64
ns
-
24
48
nC
-
17
-
-
18
-
tr
td(off)
VDD = 20 V, RL = 2
ID 10 A, VGEN = 4.5 V, Rg = 1
tf
ns
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
IS
Pulse diode forward current (tp = 100 μs)
ISM
Body diode voltage
VSD
Body diode reverse recovery time
trr
Body diode reverse recovery charge
Qrr
Reverse recovery fall time
ta
Reverse recovery rise time
tb
TC = 25 °C
IS = 5 A
IF = 15 A, di/dt = 100 A/μs,
TJ = 25 °C
A
ns
Notes
a. Pulse test; pulse width 300 μs, duty cycle 2 %
b. Guaranteed by design, not subject to production testing
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S19-0653-Rev. A, 05-Aug-2019
Document Number: 77131
2
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiR150DP
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Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Axis Title
Axis Title
10000
200
10000
250
VGS = 10 V thru 4 V
80
100
VGS = 3 V
1000
150
1st line
2nd line
1000
120
2nd line
ID - Drain Current (A)
200
1st line
2nd line
100
TC = 25 °C
50
40
1
2
3
4
10
0
10
0
0
TC = -55 °C
TC = 125 °C
VGS = 2 V
0
5
1
2
3
5
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
6
Axis Title
10000
0.0058
10000
10 000
Ciss
VGS = 4.5 V
0.0038
0.0028
100
0.0018
Coss
1000
1000
1st line
2nd line
1000
2nd line
C - Capacitance (pF)
0.0048
1st line
2nd line
2nd line
RDS(on) - On-Resistance (Ω)
4
VDS - Drain-to-Source Voltage (V)
Axis Title
Crss
100
100
VGS = 10 V
0
40
80
120
160
10
10
10
0.0008
0
200
9
18
36
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
Capacitance
Axis Title
1000
1st line
2nd line
VDS = 10 V, 20 V, 30 V
4
100
2
10
0
20
30
40
50
2nd line
RDS(on) - On-Resistance (Normalized)
ID = 15 A
6
10000
1.9
8
10
45
Axis Title
10000
0
27
ID - Drain Current (A)
10
2nd line
VGS - Gate-to-Source Voltage (V)
100
VGS = 10 V, 15 A
1.6
1000
1.3
1.0
VGS = 4.5 V, 15 A
100
0.7
10
0.4
-50
-25
0
25
50
75
100 125 150
Qg - Total Gate Charge (nC)
TJ - Junction Temperature (°C)
Gate Charge
On-Resistance vs. Junction Temperature
S19-0653-Rev. A, 05-Aug-2019
1st line
2nd line
2nd line
ID - Drain Current (A)
160
Document Number: 77131
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SiR150DP
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Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Axis Title
Axis Title
10000
0.015
10000
100
1000
TJ = 150 °C
1
TJ = 25 °C
100
0.1
1000
0.009
1st line
2nd line
2nd line
RDS(on) - On-Resistance (Ω)
10
1st line
2nd line
2nd line
IS - Source Current (A)
ID = 15 A
0.012
0.006
100
TJ = 125 °C
0.003
TJ = 25 °C
0.01
10
0
0.2
0.4
0.6
0.8
1.0
10
0
1.2
0
2
4
8
10
VSD - Source-to-Drain Voltage (V)
VGS - Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
Axis Title
Axis Title
10000
0.5
10000
500
0.2
400
-0.4
100
ID = 250 μA
300
1st line
2nd line
ID = 5 mA
1000
2nd line
P - Power (W)
1000
-0.1
1st line
2nd line
2nd line
VGS(th) - Variance (V)
6
200
100
-0.7
100
10
-1.0
-50
-25
0
25
50
75
0
0.0001
100 125 150
10
0.001
0.01
0.1
1
10
TJ - Junction Temperature (°C)
t - Time (s)
Threshold Voltage
Single Pulse Power, Junction-to-Ambient
Axis Title
10000
1000
IDM limited
ID limited
1000
100 μs
10
1 ms
Limited by RDS(on)
a
10 ms
1
1st line
2nd line
2nd line
ID - Drain Current (A)
100
100 100
ms
1s
0.1
10 s
TA = 25 °C,
single pulse
0.01
0.01
BVDSS limited
DC
10
0.1
1
10
100
VDS - Drain-to-Source Voltage (V)
Safe Operating Area
Note
a. VGS > minimum VGS at which RDS(on) is specified
S19-0653-Rev. A, 05-Aug-2019
Document Number: 77131
4
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiR150DP
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Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Axis Title
10000
125
1000
75
1st line
2nd line
2nd line
ID - Drain Current (A)
100
50
100
25
10
0
0
25
50
75
100
125
150
TC - Case Temperature (°C)
Current Derating a
Axis Title
Axis Title
10000
80
2.0
1st line
2nd line
32
100
16
1000
1.5
1st line
2nd line
1000
48
2nd line
P - Power (W)
64
2nd line
P - Power (W)
10000
2.5
1.0
100
0.5
10
0
0
25
50
75
100
125
150
10
0
0
25
50
75
100
125
TC - Case Temperature (°C)
TA - Ambient Temperature (°C)
Power, Junction-to-Case
Power, Junction-to-Ambient
150
Note
a. The power dissipation PD is based on TJ max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the
package limit
S19-0653-Rev. A, 05-Aug-2019
Document Number: 77131
5
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiR150DP
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Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Axis Title
10000
Duty cycle = 0.5
Notes
0.2
PDM
0.1
0.1
1000
1st line
2nd line
Normalized Effective Transient
Thermal Impedance
1
t1
t2
t1
1. Duty cycle, D = t
2
2. Per unit base = RthJA = 62.5 °C/W
0.05
0.02
3. TJM - TA = PDMZthJA
Single pulse
100
(t)
4. Surface mounted
0.01
0.0001
0.001
0.01
0.1
1
10
100
10
1000
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
Axis Title
1
10000
0.2
1000
0.1
1st line
2nd line
Normalized Effective Transient
Thermal Impedance
Duty cycle = 0.5
0.05
0.1
0.02
100
Single pulse
0.01
0.0001
10
0.001
0.01
0.1
1
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Case
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?77131.
S19-0653-Rev. A, 05-Aug-2019
Document Number: 77131
6
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
PowerPAK® SO-8, (Single/Dual)
L
H
E2
K
E4
θ
D4
W
1
M
1
Z
2
D5
D2
e
2
D1
D
2
D
3
4
θ
4
b
3
L1
E3
θ
A1
Backside View of Single Pad
H
K
E2
E4
L
1
D1
D5
2
D2
Detail Z
K1
2
E1
E
D3 (2x) D4
c
A
θ
3
4
Notes
1. Inch will govern.
2 Dimensions exclusive of mold gate burrs.
3. Dimensions exclusive of mold flash and cutting burrs.
DIM.
A
A1
b
c
D
D1
D2
D3
D4
D5
E
E1
E2
E3
E4
e
K
K1
H
L
L1
W
M
b
D2
E3
Backside View of Dual Pad
MILLIMETERS
INCHES
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
0.97
1.04
0.41
0.28
5.15
4.90
3.76
1.50
0.57 typ.
3.98 typ.
6.15
5.89
3.66
3.78
0.75 typ.
1.27 BSC
1.27 typ.
0.61
0.61
0.13
0.25
0.125 typ.
1.12
0.05
0.51
0.33
5.26
5.00
3.91
1.68
0.038
0
0.013
0.009
0.199
0.189
0.140
0.052
0.044
0.002
0.020
0.013
0.207
0.197
0.154
0.066
6.25
5.99
3.84
3.91
0.238
0.228
0.137
0.145
0.71
0.71
0.20
12°
0.36
0.022
0.020
0.020
0.002
0°
0.006
0.041
0.016
0.011
0.203
0.193
0.148
0.059
0.0225 typ.
0.157 typ.
0.242
0.232
0.144
0.149
0.030 typ.
0.050 BSC
0.050 typ.
0.024
0.024
0.005
0.010
0.005 typ.
0.33
0.23
5.05
4.80
3.56
1.32
6.05
5.79
3.48
3.68
0.56
0.51
0.51
0.06
0°
0.15
0.246
0.236
0.151
0.154
0.028
0.028
0.008
12°
0.014
ECN: S17-0173-Rev. L, 13-Feb-17
DWG: 5881
Revison: 13-Feb-17
1
Document Number: 71655
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VISHAY SILICONIX
www.vishay.com
Power MOSFETs
Application Note AN821
PowerPAK® SO-8 Mounting and Thermal Considerations
by Wharton McDaniel
MOSFETs for switching applications are now available with
die on resistances around 1 m and with the capability to
handle 85 A. While these die capabilities represent a major
advance over what was available just a few years ago, it is
important for power MOSFET packaging technology to keep
pace. It should be obvious that degradation of a high
performance die by the package is undesirable. PowerPAK
is a new package technology that addresses these issues.
In this application note, PowerPAK’s construction is
described. Following this mounting information is presented
including land patterns and soldering profiles for maximum
reliability. Finally, thermal and electrical performance is
discussed.
PowerPAK SO-8 SINGLE MOUNTING
The PowerPAK single is simple to use. The pin arrangement
(drain, source, gate pins) and the pin dimensions are the
same as standard SO-8 devices (see figure 2). Therefore, the
PowerPAK connection pads match directly to those of the
SO-8. The only difference is the extended drain connection
area. To take immediate advantage of the PowerPAK SO-8
single devices, they can be mounted to existing SO-8 land
patterns.
THE PowerPAK PACKAGE
The PowerPAK package was developed around the SO-8
package (figure 1). The PowerPAK SO-8 utilizes the same
footprint and the same pin-outs as the standard SO-8. This
allows PowerPAK to be substituted directly for a standard
SO-8 package. Being a leadless package, PowerPAK SO-8
utilizes the entire SO-8 footprint, freeing space normally
occupied by the leads, and thus allowing it to hold a larger
die than a standard SO-8. In fact, this larger die is slightly
larger than a full sized DPAK die. The bottom of the die
attach pad is exposed for the purpose of providing a direct,
low resistance thermal path to the substrate the device is
mounted on. Finally, the package height is lower than the
standard SO-8, making it an excellent choice for
applications with space constraints.
Standard SO-8
PowerPAK SO-8
Fig. 2
The minimum land pattern recommended to take full
advantage of the PowerPAK thermal performance see
Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs. Click on the PowerPAK SO-8 single in the index
of this document.
In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.
Fig. 1
Revision: 16-Mai-13
PowerPAK 1212 Devices
Document Number: 71622
1
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APPLICATION NOTE
This land pattern can be extended to the left, right, and top
of the drawn pattern. This extension will serve to increase
the heat dissipation by decreasing the thermal resistance
from the foot of the PowerPAK to the PC board and
therefore to the ambient. Note that increasing the drain land
area beyond a certain point will yield little decrease
in foot-to-board and foot-to-ambient thermal resistance.
Under specific conditions of board configuration, copper
weight and layer stack, experiments have found that
more than about 0.25 in2 to 0.5 in2 of additional copper
(in addition to the drain land) will yield little improvement in
thermal performance.
Application Note AN821
www.vishay.com
Vishay Siliconix
PowerPAK® SO-8 Mounting and Thermal Considerations
PowerPAK SO-8 DUAL
The pin arrangement (drain, source, gate pins) and the pin
dimensions of the PowerPAK SO-8 dual are the same as
standard SO-8 dual devices. Therefore, the PowerPAK
device connection pads match directly to those of the SO-8.
As in the single-channel package, the only exception is the
extended drain connection area. Manufacturers can likewise
take immediate advantage of the PowerPAK SO-8 dual
devices by mounting them to existing SO-8 dual land
patterns.
For
the
lead
(Pb)-free
www.vishay.com/doc?73257.
solder
profile,
see
To take the advantage of the dual PowerPAK SO-8’s
thermal performance, the minimum recommended land
pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click on the
PowerPAK 1212-8 dual in the index of this document.
The gap between the two drain pads is 24 mils. This
matches the spacing of the two drain pads on the
PowerPAK SO-8 dual package.
Fig. 3 Solder Reflow Temperature Profile
REFLOW SOLDERING
Ramp-Up Rate
Vishay Siliconix surface-mount packages meet solder reflow
reliability requirements. Devices are subjected to solder
reflow as a test preconditioning and are then
reliability-tested using temperature cycle, bias humidity,
HAST, or pressure pot. The solder reflow temperature profile
used, and the temperatures and time duration, are shown in
figures 3 and 4.
Temperature at 150 - 200 °C
+ 3 °C /s max.
120 s max.
Temperature Above 217 °C
60 - 150 s
Maximum Temperature
255 + 5/- 0 °C
Time at Maximum
Temperature
30 s
Ramp-Down Rate
+ 6 °C/s max.
30 s
260 °C
3 °C(max)
6 °C/s (max.)
217 °C
150 - 200 °C
APPLICATION NOTE
150 s (max.)
60 s (min.)
Pre-Heating Zone
Reflow Zone
Maximum peak temperature at 240 °C is allowed.
Fig. 4 Solder Reflow Temperatures and Time Durations
Revision: 16-Mai-13
Document Number: 71622
2
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Application Note AN821
www.vishay.com
Vishay Siliconix
PowerPAK® SO-8 Mounting and Thermal Considerations
THERMAL PERFORMANCE
Introduction
A basic measure of a device’s thermal performance
is the junction-to-case thermal resistance, RthJC, or the
junction-to-foot thermal resistance, RthJF This parameter is
measured for the device mounted to an infinite heat sink and
is therefore a characterization of the device only, in other
words, independent of the properties of the object to which
the device is mounted. Table 1 shows a comparison of
the DPAK, PowerPAK SO-8, and standard SO-8. The
PowerPAK has thermal performance equivalent to the
DPAK, while having an order of magnitude better thermal
performance over the SO-8.
TABLE 1 - DPAK AND POWERPAK SO-8
EQUIVALENT STEADY STATE
PERFORMANCE
Thermal
Resistance RthJC
DPAK
PowerPAK
SO-8
Standard
SO-8
1.2 °C/W
1 °C/W
16 °C/W
Thermal Performance on Standard SO-8 Pad Pattern
Because of the common footprint, a PowerPAK SO-8
can be mounted on an existing standard SO-8 pad pattern.
The question then arises as to the thermal performance
of the PowerPAK device under these conditions. A
characterization was made comparing a standard SO-8 and
a PowerPAK device on a board with a trough cut out
underneath the PowerPAK drain pad. This configuration
restricted the heat flow to the SO-8 land pads. The results
are shown in figure 5.
Because of the presence of the trough, this result suggests
a minimum performance improvement of 10 °C/W by using
a PowerPAK SO-8 in a standard SO-8 PC board mount.
The only concern when mounting a PowerPAK on a
standard SO-8 pad pattern is that there should be no traces
running between the body of the MOSFET. Where the
standard SO-8 body is spaced away from the pc board,
allowing traces to run underneath, the PowerPAK sits
directly on the pc board.
Thermal Performance - Spreading Copper
Designers may add additional copper, spreading copper, to
the drain pad to aid in conducting heat from a device. It is
helpful to have some information about the thermal
performance for a given area of spreading copper.
Figure 6 shows the thermal resistance of a PowerPAK SO-8
device mounted on a 2-in. 2-in., four-layer FR-4 PC board.
The two internal layers and the backside layer are solid
copper. The internal layers were chosen as solid copper to
model the large power and ground planes common in many
applications. The top layer was cut back to a smaller area
and at each step junction-to-ambient thermal resistance
measurements were taken. The results indicate that an area
above 0.3 to 0.4 square inches of spreading copper gives no
additional
thermal
performance
improvement.
A
subsequent experiment was run where the copper on the
back-side was reduced, first to 50 % in stripes to mimic
circuit traces, and then totally removed. No significant effect
was observed.
Rth vs. Spreading Copper
(0 %, 50 %, 100 % Back Copper)
56
Si4874DY vs. Si7446DP PPAK on a 4-Layer Board
SO-8 Pattern, Trough Under Drain
Impedance (C/watts)
60
Impedance (C/watts)
APPLICATION NOTE
50
40
Si4874DY
30
51
46
100 %
41
Si7446DP
0%
20
50 %
36
10
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
Spreading Copper (sq in)
0
0.0001
0.01
1
100
10000
Fig. 6 Spreading Copper Junction-to-Ambient Performance
Pulse Duration (sec)
Fig. 5 PowerPAK SO-8 and Standard SO-0 Land Pad Thermal
Path
Revision: 16-Mai-13
Document Number: 71622
3
For technical questions, contact: powermosfettechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Application Note AN821
www.vishay.com
Vishay Siliconix
PowerPAK® SO-8 Mounting and Thermal Considerations
SYSTEM AND ELECTRICAL IMPACT OF
PowerPAK SO-8
In any design, one must take into account the change in
MOSFET RDS(on) with temperature (figure 7).
On-Resistance vs. Junction Temperature
R DS(on) - On-Resistance ( ) (Normalized)
1.8
VGS = 10 V
ID = 23 A
1.6
1.2
Minimizing the thermal rise above the board temperature by
using PowerPAK has not only eased the thermal design but
it has allowed the device to run cooler, keep rDS(on) low, and
permits the device to handle more current than the same
MOSFET die in the standard SO-8 package.
1.0
CONCLUSIONS
1.4
PowerPAK SO-8 has been shown to have the same thermal
performance as the DPAK package while having the same
footprint as the standard SO-8 package. The PowerPAK
SO-8 can hold larger die approximately equal in size to the
maximum that the DPAK can accommodate implying no
sacrifice in performance because of package limitations.
0.8
0.6
- 50
- 25
0
25
50
75
100
125
150
TJ - Junction Temperature (°C)
Fig. 7 MOSFET RDS(on) vs. Temperature
A MOSFET generates internal heat due to the current
passing through the channel. This self-heating raises the
junction temperature of the device above that of the PC
board to which it is mounted, causing increased power
dissipation in the device. A major source of this problem lies
in the large values of the junction-to-foot thermal resistance
of the SO-8 package.
PowerPAK SO-8 minimizes the junction-to-board thermal
resistance to where the MOSFET die temperature is very
close to the temperature of the PC board. Consider two
devices mounted on a PC board heated to 105 °C by other
components on the board (figure 8).
PowerPAK SO-8
APPLICATION NOTE
Suppose each device is dissipating 2.7 W. Using the
junction-to-foot thermal resistance characteristics of the
PowerPAK SO-8 and the standard SO-8, the die
temperature is determined to be 107 °C for the PowerPAK
(and for DPAK) and 148 °C for the standard SO-8. This is a
2 °C rise above the board temperature for the PowerPAK
and a 43 °C rise for the standard SO-8. Referring to figure 7,
a 2 °C difference has minimal effect on RDS(on) whereas a
43 °C difference has a significant effect on RDS(on).
Recommended PowerPAK SO-8 land patterns are provided
to aid in PC board layout for designs using this new
package.
Thermal considerations have indicated that significant
advantages can be gained by using PowerPAK SO-8
devices in designs where the PC board was laid out for
the standard SO-8. Applications experimental data gave
thermal performance data showing minimum and
typical thermal performance in a SO-8 environment, plus
information on the optimum thermal performance
obtainable including spreading copper. This further
emphasized the DPAK equivalency.
PowerPAK SO-8 therefore has the desired small size
characteristics of the SO-8 combined with the attractive
thermal characteristics of the DPAK package.
Standard SO-8
107 °C
0.8 °C/W
148 °C
16 C/W
PC Board at 105 °C
Fig. 8 Temperature of Devices on a PC Board
Revision: 16-Mai-13
Document Number: 71622
4
For technical questions, contact: powermosfettechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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